coreboot-gerrit April 2021

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Change in coreboot[master]: include/assert.h: Use mock_assert() for ENV_TEST targets
by Jakub Czapiga (Code Review) 06 Apr '21

06 Apr '21

Attention is currently required from: Jakub Czapiga, Julius Werner, Jan Dabros. Hello build bot (Jenkins), Patrick Georgi, Martin Roth, Paul Fagerburg, Julius Werner, Jan Dabros, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/51804 to look at the new patch set (#3). Change subject: include/assert.h: Use mock_assert() for ENV_TEST targets ...................................................................... include/assert.h: Use mock_assert() for ENV_TEST targets Some tests have to be able to catch assertion errors. Adding CMocka mock_assert() enables that. Additionally fix test_imd_create_tiered_empty(), test_full_stack() and test_incorrectly_initialized_stack() by adding missing expect_assert_failure(). Signed-off-by: Jakub Czapiga <jacz(a)semihalf.com> Change-Id: I5e8dd1b198ee6fab61e2be3f92baf1178f79bf18 --- M src/include/assert.h M tests/lib/imd-test.c M tests/lib/stack-test.c 3 files changed, 23 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/04/51804/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/51804 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5e8dd1b198ee6fab61e2be3f92baf1178f79bf18 Gerrit-Change-Number: 51804 Gerrit-PatchSet: 3 Gerrit-Owner: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: Jan Dabros <jsd(a)semihalf.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Fagerburg <pfagerburg(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Jan Dabros <jsd(a)semihalf.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: HACK sc7280: QSIP SPI NOR addressing mode HACK
by build bot (Jenkins) (Code Review) 06 Apr '21

06 Apr '21

Attention is currently required from: Ravi kumar, mturney mturney. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50586 ) Change subject: HACK sc7280: QSIP SPI NOR addressing mode HACK ...................................................................... Patch Set 28: (2 comments) File src/drivers/spi/spi_flash.c: https://review.coreboot.org/c/coreboot/+/50586/comment/85f02d66_aed9bead PS28, Line 493: if (reg8 & 0x20){ space required before the open brace '{' https://review.coreboot.org/c/coreboot/+/50586/comment/faadc000_07ec9100 PS28, Line 497: while (1); trailing statements should be on next line -- To view, visit https://review.coreboot.org/c/coreboot/+/50586 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ied5b647d0fcc8e3effff3bb7c8680ed5a0c1f3d4 Gerrit-Change-Number: 50586 Gerrit-PatchSet: 28 Gerrit-Owner: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Reviewer: Sajida Bhanu <sbhanu(a)codeaurora.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Attention: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Attention: mturney mturney <mturney(a)codeaurora.org> Gerrit-Comment-Date: Tue, 06 Apr 2021 12:59:42 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: sc7280: reserved wlan & wpss dram memory regions
by build bot (Jenkins) (Code Review) 06 Apr '21

06 Apr '21

Attention is currently required from: Shelley Chen, mturney mturney, Julius Werner. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50587 ) Change subject: sc7280: reserved wlan & wpss dram memory regions ...................................................................... Patch Set 26: (4 comments) File src/soc/qualcomm/sc7280/soc.c: https://review.coreboot.org/c/coreboot/+/50587/comment/b7785ff6_80cc0a38 PS26, Line 22: REGION_SIZE(dram_wlan) / KiB); code indent should use tabs where possible https://review.coreboot.org/c/coreboot/+/50587/comment/7981e4af_f180f039 PS26, Line 22: REGION_SIZE(dram_wlan) / KiB); please, no spaces at the start of a line https://review.coreboot.org/c/coreboot/+/50587/comment/e18946fc_5c9489d6 PS26, Line 24: REGION_SIZE(dram_wpss) / KiB); code indent should use tabs where possible https://review.coreboot.org/c/coreboot/+/50587/comment/a05e8816_7d0b7dc5 PS26, Line 24: REGION_SIZE(dram_wpss) / KiB); please, no spaces at the start of a line -- To view, visit https://review.coreboot.org/c/coreboot/+/50587 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic98b5d08a0a7b3f772582bf85d94f901a7c53010 Gerrit-Change-Number: 50587 Gerrit-PatchSet: 26 Gerrit-Owner: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: mturney mturney <mturney(a)codeaurora.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-CC: Ravi Kumar Bokka <c_rbokka(a)qualcomm.corp-partner.google.com> Gerrit-Attention: Shelley Chen <shchen(a)google.com> Gerrit-Attention: mturney mturney <mturney(a)codeaurora.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Comment-Date: Tue, 06 Apr 2021 12:56:31 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: sc7280: cpucp loading changes
by build bot (Jenkins) (Code Review) 06 Apr '21

06 Apr '21

Attention is currently required from: Shelley Chen, Martin Roth, Julius Werner. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49768 ) Change subject: sc7280: cpucp loading changes ...................................................................... Patch Set 27: (42 comments) File src/soc/qualcomm/sc7280/cpucp_load_reset.c: https://review.coreboot.org/c/coreboot/+/49768/comment/7b5ffa71_e9b9c7ba PS27, Line 15: uint32_t val = read32(EPSSTOP_SECURE_ACCESS_OVERRIDE); code indent should use tabs where possible https://review.coreboot.org/c/coreboot/+/49768/comment/2343fb20_6971cf5b PS27, Line 15: uint32_t val = read32(EPSSTOP_SECURE_ACCESS_OVERRIDE); please, no spaces at the start of a line https://review.coreboot.org/c/coreboot/+/49768/comment/85a9baac_eeed702f PS27, Line 16: val |= 0x1; code indent should use tabs where possible https://review.coreboot.org/c/coreboot/+/49768/comment/18998a28_01607cc0 PS27, Line 16: val |= 0x1; please, no spaces at the start of a line https://review.coreboot.org/c/coreboot/+/49768/comment/57b16ed8_b8793c97 PS27, Line 18: /* allow NS access to EPSS memory*/ code indent should use tabs where possible https://review.coreboot.org/c/coreboot/+/49768/comment/2213b215_06dae7d2 PS27, Line 19: write32(EPSSTOP_SECURE_ACCESS_OVERRIDE, val); code indent should use tabs where possible https://review.coreboot.org/c/coreboot/+/49768/comment/1d49687c_2f1970c9 PS27, Line 19: write32(EPSSTOP_SECURE_ACCESS_OVERRIDE, val); please, no spaces at the start of a line https://review.coreboot.org/c/coreboot/+/49768/comment/7ef51e13_37afc06e PS27, Line 21: val = read32(EPSSFAST_EPSS_MUC_CLK_CTRL); code indent should use tabs where possible https://review.coreboot.org/c/coreboot/+/49768/comment/69dc65f2_de60a3f1 PS27, Line 21: val = read32(EPSSFAST_EPSS_MUC_CLK_CTRL); please, no spaces at the start of a line https://review.coreboot.org/c/coreboot/+/49768/comment/a6ddc4c6_f3920ad7 PS27, Line 22: val |= 0x1; code indent should use tabs where possible https://review.coreboot.org/c/coreboot/+/49768/comment/ef9d9c7e_cc77752e PS27, Line 22: val |= 0x1; please, no spaces at the start of a line https://review.coreboot.org/c/coreboot/+/49768/comment/75260d18_2bb24766 PS27, Line 24: /* Enable subsystem clock. Required for CPUCP PDMEM access*/ code indent should use tabs where possible https://review.coreboot.org/c/coreboot/+/49768/comment/da76457c_32671b87 PS27, Line 25: write32(EPSSFAST_EPSS_MUC_CLK_CTRL, val); code indent should use tabs where possible https://review.coreboot.org/c/coreboot/+/49768/comment/904d9d84_68f6bbc0 PS27, Line 25: write32(EPSSFAST_EPSS_MUC_CLK_CTRL, val); please, no spaces at the start of a line https://review.coreboot.org/c/coreboot/+/49768/comment/5b847ebe_e9c318f2 PS27, Line 27: while((read32(EPSSFAST_EPSS_MUC_CLK_CTRL) & 0x1) != 0x1); code indent should use tabs where possible https://review.coreboot.org/c/coreboot/+/49768/comment/93f3b85c_3577e926 PS27, Line 27: while((read32(EPSSFAST_EPSS_MUC_CLK_CTRL) & 0x1) != 0x1); please, no spaces at the start of a line https://review.coreboot.org/c/coreboot/+/49768/comment/3399c768_3bb90c03 PS27, Line 27: while((read32(EPSSFAST_EPSS_MUC_CLK_CTRL) & 0x1) != 0x1); space required before the open parenthesis '(' https://review.coreboot.org/c/coreboot/+/49768/comment/aeb573b6_3803f4ec PS27, Line 27: while((read32(EPSSFAST_EPSS_MUC_CLK_CTRL) & 0x1) != 0x1); trailing statements should be on next line https://review.coreboot.org/c/coreboot/+/49768/comment/ad6560e3_3328c8e7 PS27, Line 32: bool cpucp_fw_entry; code indent should use tabs where possible https://review.coreboot.org/c/coreboot/+/49768/comment/bdd62a49_94629566 PS27, Line 32: bool cpucp_fw_entry; please, no spaces at the start of a line https://review.coreboot.org/c/coreboot/+/49768/comment/f57bae28_22aeb8dc PS27, Line 33: printk(BIOS_DEBUG, "\nSOC:CPUCP image loading.\n"); code indent should use tabs where possible https://review.coreboot.org/c/coreboot/+/49768/comment/fb73b8d7_5bef5cca PS27, Line 33: printk(BIOS_DEBUG, "\nSOC:CPUCP image loading.\n"); please, no spaces at the start of a line https://review.coreboot.org/c/coreboot/+/49768/comment/0173d5d8_2d0ef134 PS27, Line 35: struct prog cpucp_fw_prog = code indent should use tabs where possible https://review.coreboot.org/c/coreboot/+/49768/comment/38364340_1df4f3aa PS27, Line 35: struct prog cpucp_fw_prog = please, no spaces at the start of a line https://review.coreboot.org/c/coreboot/+/49768/comment/fde241e3_b8eb4560 PS27, Line 36: PROG_INIT(PROG_PAYLOAD, CONFIG_CBFS_PREFIX "/cpucp"); code indent should use tabs where possible https://review.coreboot.org/c/coreboot/+/49768/comment/7743cb41_4e33c0f0 PS27, Line 36: PROG_INIT(PROG_PAYLOAD, CONFIG_CBFS_PREFIX "/cpucp"); please, no spaces at the start of a line https://review.coreboot.org/c/coreboot/+/49768/comment/42904cb9_afe40ae7 PS27, Line 38: cpucp_prepare(); code indent should use tabs where possible https://review.coreboot.org/c/coreboot/+/49768/comment/dca5a862_734cf9c1 PS27, Line 38: cpucp_prepare(); please, no spaces at the start of a line https://review.coreboot.org/c/coreboot/+/49768/comment/66ba8a7d_42efd302 PS27, Line 40: if (prog_locate(&cpucp_fw_prog)) code indent should use tabs where possible https://review.coreboot.org/c/coreboot/+/49768/comment/53e209b3_50898f31 PS27, Line 40: if (prog_locate(&cpucp_fw_prog)) please, no spaces at the start of a line https://review.coreboot.org/c/coreboot/+/49768/comment/9c6eb7ab_0cb79ab5 PS27, Line 41: die("SOC imagpe: CPUCP_FW not found"); code indent should use tabs where possible https://review.coreboot.org/c/coreboot/+/49768/comment/36ee6018_9e37d35b PS27, Line 41: die("SOC imagpe: CPUCP_FW not found"); please, no spaces at the start of a line https://review.coreboot.org/c/coreboot/+/49768/comment/6387f58f_f5215255 PS27, Line 43: cpucp_fw_entry = selfload(&cpucp_fw_prog); code indent should use tabs where possible https://review.coreboot.org/c/coreboot/+/49768/comment/11fe4f7a_eb29a38f PS27, Line 43: cpucp_fw_entry = selfload(&cpucp_fw_prog); please, no spaces at the start of a line https://review.coreboot.org/c/coreboot/+/49768/comment/c4c2ebd6_1f7c337d PS27, Line 44: if (!cpucp_fw_entry) code indent should use tabs where possible https://review.coreboot.org/c/coreboot/+/49768/comment/bffc52c3_ec8406f8 PS27, Line 44: if (!cpucp_fw_entry) please, no spaces at the start of a line https://review.coreboot.org/c/coreboot/+/49768/comment/94c0a52a_ab2351cd PS27, Line 45: die("SOC image: CPUCP load failed"); code indent should use tabs where possible https://review.coreboot.org/c/coreboot/+/49768/comment/c1052350_77e5d4d2 PS27, Line 45: die("SOC image: CPUCP load failed"); please, no spaces at the start of a line https://review.coreboot.org/c/coreboot/+/49768/comment/a01f72b8_bdcb9784 PS27, Line 49: printk(BIOS_DEBUG, "\nSOC:CPUCP image loaded successfully.\n"); code indent should use tabs where possible https://review.coreboot.org/c/coreboot/+/49768/comment/f80a49e7_d705cb92 PS27, Line 49: printk(BIOS_DEBUG, "\nSOC:CPUCP image loaded successfully.\n"); please, no spaces at the start of a line File src/soc/qualcomm/sc7280/soc.c: https://review.coreboot.org/c/coreboot/+/49768/comment/24df4a11_86f65144 PS27, Line 20: REGION_SIZE(dram_cpucp) / KiB); code indent should use tabs where possible https://review.coreboot.org/c/coreboot/+/49768/comment/e5fd6969_4b3b569d PS27, Line 20: REGION_SIZE(dram_cpucp) / KiB); please, no spaces at the start of a line -- To view, visit https://review.coreboot.org/c/coreboot/+/49768 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idac22c8cb231658616999bc577bdf49f9aa7ae74 Gerrit-Change-Number: 49768 Gerrit-PatchSet: 27 Gerrit-Owner: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-CC: Ravi Kumar Bokka <c_rbokka(a)qualcomm.corp-partner.google.com> Gerrit-Attention: Shelley Chen <shchen(a)google.com> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Comment-Date: Tue, 06 Apr 2021 12:55:20 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: sc7280: aop blob loading changes
by build bot (Jenkins) (Code Review) 06 Apr '21

06 Apr '21

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Change in coreboot[master]: sc7280: shrm.elf loading changes
by build bot (Jenkins) (Code Review) 06 Apr '21

06 Apr '21

Attention is currently required from: Shelley Chen, Martin Roth, mturney mturney, Julius Werner. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49392 ) Change subject: sc7280: shrm.elf loading changes ...................................................................... Patch Set 28: (1 comment) File src/soc/qualcomm/sc7280/shrm_load_reset.c: https://review.coreboot.org/c/coreboot/+/49392/comment/ee97558d_d8ac6ad0 PS28, Line 9: void shrm_fw_load_reset() Bad function definition - void shrm_fw_load_reset() should probably be void shrm_fw_load_reset(void) -- To view, visit https://review.coreboot.org/c/coreboot/+/49392 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I44484573a829eaefbd34907c6fe78d427506a762 Gerrit-Change-Number: 49392 Gerrit-PatchSet: 28 Gerrit-Owner: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: mturney mturney <mturney(a)codeaurora.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-CC: Ravi Kumar Bokka <c_rbokka(a)qualcomm.corp-partner.google.com> Gerrit-Attention: Shelley Chen <shchen(a)google.com> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: mturney mturney <mturney(a)codeaurora.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Comment-Date: Tue, 06 Apr 2021 12:54:33 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: security/tpm: Add option to init TPM in bootblock
by Arthur Heymans (Code Review) 06 Apr '21

06 Apr '21

Attention is currently required from: Philipp Deppenwiese, Martin Roth, Paul Menzel, Christian Walter, Julius Werner. Hello Philipp Deppenwiese, build bot (Jenkins), Patrick Georgi, Martin Roth, Christian Walter, Julius Werner, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/51923 to look at the new patch set (#5). Change subject: security/tpm: Add option to init TPM in bootblock ...................................................................... security/tpm: Add option to init TPM in bootblock When using a hardware assisted root of trust measurement, like Intel TXT/CBnT, the TPM init needs to happen inside the bootblock to form a proper chain of trust. Change-Id: Ifacba5d9ab19b47968b4f2ed5731ded4aac55022 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/drivers/pc80/tpm/Makefile.inc M src/drivers/tpm/Kconfig M src/lib/bootblock.c M src/security/intel/cbnt/Kconfig M src/security/tpm/Kconfig M src/security/tpm/tspi/tspi.c 6 files changed, 24 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/23/51923/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/51923 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifacba5d9ab19b47968b4f2ed5731ded4aac55022 Gerrit-Change-Number: 51923 Gerrit-PatchSet: 5 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Attention: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: security/tpm: Add option to init TPM in bootblock
by Arthur Heymans (Code Review) 06 Apr '21

06 Apr '21

Attention is currently required from: Philipp Deppenwiese, Martin Roth, Paul Menzel, Christian Walter, Julius Werner. Hello Philipp Deppenwiese, build bot (Jenkins), Patrick Georgi, Martin Roth, Christian Walter, Julius Werner, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/51923 to look at the new patch set (#4). Change subject: security/tpm: Add option to init TPM in bootblock ...................................................................... security/tpm: Add option to init TPM in bootblock When using a hardware assisted root of trust measurement, like Intel TXT/CBnT, the TPM init needs to happen inside the bootblock to form a proper chain of trust. Change-Id: Ifacba5d9ab19b47968b4f2ed5731ded4aac55022 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/drivers/pc80/tpm/Makefile.inc M src/drivers/tpm/Kconfig M src/lib/bootblock.c M src/security/intel/cbnt/Kconfig M src/security/tpm/Kconfig M src/security/tpm/tspi/tspi.c 6 files changed, 24 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/23/51923/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/51923 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifacba5d9ab19b47968b4f2ed5731ded4aac55022 Gerrit-Change-Number: 51923 Gerrit-PatchSet: 4 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Attention: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: drivers/tpm/Kconfig: Rename TPM_INIT to TPM_INIT_RAMSTAGE
by Arthur Heymans (Code Review) 06 Apr '21

06 Apr '21

Attention is currently required from: Martin Roth, Frans Hendriks, Wim Vervoorn. Hello Patrick Georgi, Martin Roth, Frans Hendriks, Wim Vervoorn, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/52133 to look at the new patch set (#2). Change subject: drivers/tpm/Kconfig: Rename TPM_INIT to TPM_INIT_RAMSTAGE ...................................................................... drivers/tpm/Kconfig: Rename TPM_INIT to TPM_INIT_RAMSTAGE Rename the Kconfig parameter to more accurately reflect what it does. TPM can be initialised in a different stage too, for instance with VBOOT it is done in verstage. Change-Id: Ic0126b356e8430c04c7c9fd46d4e20022a648738 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/drivers/tpm/Kconfig M src/drivers/tpm/Makefile.inc M src/mainboard/facebook/fbg1701/Kconfig 3 files changed, 3 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/33/52133/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/52133 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic0126b356e8430c04c7c9fd46d4e20022a648738 Gerrit-Change-Number: 52133 Gerrit-PatchSet: 2 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Wim Vervoorn <wvervoorn(a)eltan.com> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Attention: Wim Vervoorn <wvervoorn(a)eltan.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: security/tpm: Add option to init TPM in bootblock
by Arthur Heymans (Code Review) 06 Apr '21

06 Apr '21

Attention is currently required from: Philipp Deppenwiese, Martin Roth, Paul Menzel, Christian Walter, Julius Werner. Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/51923 ) Change subject: security/tpm: Add option to init TPM in bootblock ...................................................................... Patch Set 2: (6 comments) File src/drivers/tpm/tpm.c: https://review.coreboot.org/c/coreboot/+/51923/comment/c4911455_698602a3 PS2, Line 9: if (CONFIG(TPM_MEASURED_BOOT_INIT_BOOTBLOCK)) > Why not just make compilation of this whole file dependent on that in the Makefile? Then you don't n […] Done File src/lib/bootblock.c: https://review.coreboot.org/c/coreboot/+/51923/comment/b9268a58_fed10ba0 PS2, Line 64: > I would suggest to put this here, since the goal of the init() functions above is to turn on basic p […] Done File src/security/tpm/Kconfig: https://review.coreboot.org/c/coreboot/+/51923/comment/45d8dbfe_9dfec209 PS2, Line 113: Initialize tpm inside the bootblock instead of ramstage. > … for hardware assisted root of trust measurement. Done https://review.coreboot.org/c/coreboot/+/51923/comment/be90d2fa_6a03a8c8 PS2, Line 113: tpm > TPM Done File src/security/tpm/tspi/tspi.c: https://review.coreboot.org/c/coreboot/+/51923/comment/e23debb6_cad3e721 PS2, Line 112: return 1; > Use ternary operator? […] Done https://review.coreboot.org/c/coreboot/+/51923/comment/dd43547c_9abc9b6a PS2, Line 191: if (CONFIG(TPM_MEASURED_BOOT) && !CONFIG(TPM_MEASURED_BOOT_INIT_BOOTBLOCK)) { > braces {} are not necessary for single statement blocks Done -- To view, visit https://review.coreboot.org/c/coreboot/+/51923 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifacba5d9ab19b47968b4f2ed5731ded4aac55022 Gerrit-Change-Number: 51923 Gerrit-PatchSet: 2 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Attention: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Comment-Date: Tue, 06 Apr 2021 12:47:54 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: build bot (Jenkins) <no-reply(a)coreboot.org> Comment-In-Reply-To: Paul Menzel <paulepanter(a)users.sourceforge.net> Comment-In-Reply-To: Julius Werner <jwerner(a)chromium.org> Gerrit-MessageType: comment

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coreboot-gerrit April 2021