coreboot-gerrit April 2021

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Change in coreboot[master]: mb/google/zork/vilboz: Update the ACPI name of ALC1015 AMP
by EricR Lai (Code Review) 08 Apr '21

08 Apr '21

Attention is currently required from: Frank Wu, Martin Roth, Paul Menzel. EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52127 ) Change subject: mb/google/zork/vilboz: Update the ACPI name of ALC1015 AMP ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/52127 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id8f378ad6f3328d7db949ecdb609a2f16acd3884 Gerrit-Change-Number: 52127 Gerrit-PatchSet: 3 Gerrit-Owner: Frank Wu <frank_wu(a)compal.corp-partner.google.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Alan Lee <alan_lee(a)compal.corp-partner.google.com> Gerrit-CC: John Su <john_su(a)compal.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Attention: Frank Wu <frank_wu(a)compal.corp-partner.google.com> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Thu, 08 Apr 2021 07:13:34 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/mediatek: dsi: fine tune the delta time for EoTp
by Hung-Te Lin (Code Review) 08 Apr '21

08 Apr '21

Attention is currently required from: Chen-Tsung Hsieh, jitao shi, Shaoming Chen, Jitao Shi, Yu-Ping Wu. Hung-Te Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/51432 ) Change subject: soc/mediatek: dsi: fine tune the delta time for EoTp ...................................................................... Patch Set 5: Code-Review+2 (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/51432/comment/92038fd7_23b17b4f PS1, Line 9: We seperate the EoTp packet extra data > Shaoming, please address hungte's comment. Ack File src/soc/mediatek/common/dsi.c: https://review.coreboot.org/c/coreboot/+/51432/comment/3586a6a7_abf1604c PS2, Line 207: 10 > But for Kukui projects (NOT using anx7625, NOT enable MIPI_DSI_MODE_EOT_PACKET), […] Ack -- To view, visit https://review.coreboot.org/c/coreboot/+/51432 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0666068cfb04b78eb706278814163f050da32b9c Gerrit-Change-Number: 51432 Gerrit-PatchSet: 5 Gerrit-Owner: jitao shi <jitao.shi(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Chen-Tsung Hsieh <chentsung(a)chromium.org> Gerrit-CC: Chen-Tsung Hsieh <chentsung(a)google.com> Gerrit-CC: Jitao Shi <jitao.shi(a)mediatek.corp-partner.google.com> Gerrit-CC: Shaoming Chen <shaoming.chen(a)mediatek.corp-partner.google.com> Gerrit-Attention: Chen-Tsung Hsieh <chentsung(a)google.com> Gerrit-Attention: Chen-Tsung Hsieh <chentsung(a)chromium.org> Gerrit-Attention: jitao shi <jitao.shi(a)mediatek.com> Gerrit-Attention: Shaoming Chen <shaoming.chen(a)mediatek.corp-partner.google.com> Gerrit-Attention: Jitao Shi <jitao.shi(a)mediatek.corp-partner.google.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Thu, 08 Apr 2021 07:12:25 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Hung-Te Lin <hungte(a)chromium.org> Comment-In-Reply-To: Chen-Tsung Hsieh <chentsung(a)google.com> Comment-In-Reply-To: Chen-Tsung Hsieh <chentsung(a)chromium.org> Comment-In-Reply-To: Shaoming Chen <shaoming.chen(a)mediatek.corp-partner.google.com> Comment-In-Reply-To: Jitao Shi <jitao.shi(a)mediatek.corp-partner.google.com> Comment-In-Reply-To: Yu-Ping Wu <yupingso(a)google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/mancomb: add DXIO and DDI descriptors
by EricR Lai (Code Review) 08 Apr '21

08 Apr '21

Attention is currently required from: Raul Rangel, Martin Roth, Mathew King, EricR Lai, Felix Held. Hello build bot (Jenkins), Raul Rangel, Martin Roth, Mathew King, Felix Held, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/52180 to look at the new patch set (#2). Change subject: mb/google/mancomb: add DXIO and DDI descriptors ...................................................................... mb/google/mancomb: add DXIO and DDI descriptors Sync from guybrush. BUG=b:182211161 TEST=builds Signed-off-by: Eric Lai <ericr_lai(a)compal.corp-partner.google.com> Change-Id: Ica4e6511a5106a958567565b96d5888b8c829ff2 --- M src/mainboard/google/mancomb/port_descriptors.c 1 file changed, 97 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/80/52180/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/52180 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ica4e6511a5106a958567565b96d5888b8c829ff2 Gerrit-Change-Number: 52180 Gerrit-PatchSet: 2 Gerrit-Owner: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Mathew King <mathewk(a)chromium.org> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Mathew King <mathewk(a)chromium.org> Gerrit-Attention: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/mediatek: dsi: fine tune the delta time for EoTp
by Jitao Shi (Code Review) 08 Apr '21

08 Apr '21

Attention is currently required from: Chen-Tsung Hsieh, jitao shi, Shaoming Chen. Jitao Shi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/51432 ) Change subject: soc/mediatek: dsi: fine tune the delta time for EoTp ...................................................................... Patch Set 5: (1 comment) File src/soc/mediatek/common/dsi.c: https://review.coreboot.org/c/coreboot/+/51432/comment/64054281_d99fcb39 PS2, Line 207: 10 > For Jacuzzi projects, yes you keep it as 12. […] But for Kukui projects (NOT using anx7625, NOT enable MIPI_DSI_MODE_EOT_PACKET), Do we really expect to change it from 12 to 10? A: Kukui projects(NOT using anx7625) is enable EOTP, due to MIPI_DSI_MODE_EOT_PACKET actually means disable EoTp before this CL. https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/… On the other hand, I checked the driver in kernel. You use 18 or 12 for the delta according to MIPI_DSI_MODE_VIDEO_BURST. Without checking MIPI_DSI_MODE_EOT_PACKET. A: There is patch for kernel to fix EoTp flag's delta data. https://patchwork.kernel.org/project/linux-mediatek/patch/20210201033603.12… -- To view, visit https://review.coreboot.org/c/coreboot/+/51432 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0666068cfb04b78eb706278814163f050da32b9c Gerrit-Change-Number: 51432 Gerrit-PatchSet: 5 Gerrit-Owner: jitao shi <jitao.shi(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Chen-Tsung Hsieh <chentsung(a)chromium.org> Gerrit-CC: Chen-Tsung Hsieh <chentsung(a)google.com> Gerrit-CC: Jitao Shi <jitao.shi(a)mediatek.corp-partner.google.com> Gerrit-CC: Shaoming Chen <shaoming.chen(a)mediatek.corp-partner.google.com> Gerrit-Attention: Chen-Tsung Hsieh <chentsung(a)google.com> Gerrit-Attention: Chen-Tsung Hsieh <chentsung(a)chromium.org> Gerrit-Attention: jitao shi <jitao.shi(a)mediatek.com> Gerrit-Attention: Shaoming Chen <shaoming.chen(a)mediatek.corp-partner.google.com> Gerrit-Comment-Date: Thu, 08 Apr 2021 07:07:46 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Chen-Tsung Hsieh <chentsung(a)google.com> Comment-In-Reply-To: Chen-Tsung Hsieh <chentsung(a)chromium.org> Comment-In-Reply-To: Shaoming Chen <shaoming.chen(a)mediatek.corp-partner.google.com> Comment-In-Reply-To: Jitao Shi <jitao.shi(a)mediatek.corp-partner.google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/dnv_ns: hook up new gpio device operations
by Patrick Georgi (Code Review) 08 Apr '21

08 Apr '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/48618 ) Change subject: soc/intel/dnv_ns: hook up new gpio device operations ...................................................................... soc/intel/dnv_ns: hook up new gpio device operations This change hooks up the new gpio operations in DNV-NS. Change-Id: I2179e641153da7230467c5766e4ded58fdb90292 Signed-off-by: Michael Niewöhner <foss(a)mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48618 Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/intel/denverton_ns/Makefile.inc M src/soc/intel/denverton_ns/chip.c 2 files changed, 4 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Angel Pons: Looks good to me, approved diff --git a/src/soc/intel/denverton_ns/Makefile.inc b/src/soc/intel/denverton_ns/Makefile.inc index 105f866..093854c 100644 --- a/src/soc/intel/denverton_ns/Makefile.inc +++ b/src/soc/intel/denverton_ns/Makefile.inc @@ -52,6 +52,7 @@ ramstage-y += spi.c ramstage-y += fiamux.c ramstage-y += hob_mem.c +ramstage-y += gpio.c ramstage-$(CONFIG_DRIVERS_UART_8250MEM) += uart_debug.c ramstage-$(CONFIG_HAVE_ACPI_TABLES) += acpi.c ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smm.c diff --git a/src/soc/intel/denverton_ns/chip.c b/src/soc/intel/denverton_ns/chip.c index 77ad8e7..6a87353 100644 --- a/src/soc/intel/denverton_ns/chip.c +++ b/src/soc/intel/denverton_ns/chip.c @@ -9,6 +9,7 @@ #include <fsp/api.h> #include <fsp/util.h> #include <intelblocks/fast_spi.h> +#include <intelblocks/gpio.h> #include <soc/iomap.h> #include <soc/intel/common/vbt.h> #include <soc/pci_devs.h> @@ -39,6 +40,8 @@ dev->ops = &pci_domain_ops; else if (dev->path.type == DEVICE_PATH_CPU_CLUSTER) dev->ops = &cpu_bus_ops; + else if (dev->path.type == DEVICE_PATH_GPIO) + block_gpio_enable(dev); } static void soc_init(void *data) -- To view, visit https://review.coreboot.org/c/coreboot/+/48618 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2179e641153da7230467c5766e4ded58fdb90292 Gerrit-Change-Number: 48618 Gerrit-PatchSet: 27 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Mariusz Szafrański <mariuszx.szafranski(a)intel.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Michal Motyl <michalx.motyl(a)intel.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Suresh Bellampalli <suresh.bellampalli(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/qualcomm: move code to common
by Patrick Georgi (Code Review) 08 Apr '21

08 Apr '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/51758 ) Change subject: soc/qualcomm: move code to common ...................................................................... soc/qualcomm: move code to common This commit includes makefile cleanup to exclude common source file compilation in each stage by using all-y flag. BUG=b:182963902 TEST=trogdor validated on limozeen Change-Id: I48464567974a0729c1c6b6157bcce4fac39a8b38 Signed-off-by: T Michael Turney <mturney(a)codeaurora.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51758 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Shelley Chen <shchen(a)google.com> --- M src/soc/qualcomm/common/include/soc/symbols_common.h M src/soc/qualcomm/common/qclib.c R src/soc/qualcomm/common/timer.c M src/soc/qualcomm/qcs405/Makefile.inc M src/soc/qualcomm/sc7180/Makefile.inc D src/soc/qualcomm/sc7180/qclib.c D src/soc/qualcomm/sc7180/timer.c 7 files changed, 39 insertions(+), 114 deletions(-) Approvals: build bot (Jenkins): Verified Shelley Chen: Looks good to me, approved diff --git a/src/soc/qualcomm/common/include/soc/symbols_common.h b/src/soc/qualcomm/common/include/soc/symbols_common.h index 3a316c4..5180da2 100644 --- a/src/soc/qualcomm/common/include/soc/symbols_common.h +++ b/src/soc/qualcomm/common/include/soc/symbols_common.h @@ -16,14 +16,10 @@ DECLARE_REGION(pmic) DECLARE_REGION(limits_cfg) DECLARE_REGION(aop) -DECLARE_REGION(shrm) -DECLARE_REGION(dram_cpucp) +DECLARE_REGION(modem_id) DECLARE_REGION(aop_code_ram) DECLARE_REGION(aop_data_ram) -DECLARE_REGION(dram_wlan) -DECLARE_REGION(dram_wpss) DECLARE_REGION(dram_modem_wifi_only) DECLARE_REGION(dram_modem_extra) -DECLARE_REGION(modem_id) #endif // _SOC_QUALCOMM_SYMBOLS_COMMON_H_ diff --git a/src/soc/qualcomm/common/qclib.c b/src/soc/qualcomm/common/qclib.c index 6f2a6f1..e016f25 100644 --- a/src/soc/qualcomm/common/qclib.c +++ b/src/soc/qualcomm/common/qclib.c @@ -139,6 +139,24 @@ qclib_add_if_table_entry(QCLIB_TE_DDR_TRAINING_DATA, _ddr_training, REGION_SIZE(ddr_training), 0); + /* Attempt to load PMICCFG Blob */ + data_size = cbfs_load(CONFIG_CBFS_PREFIX "/pmiccfg", + _pmic, REGION_SIZE(pmic)); + if (!data_size) { + printk(BIOS_ERR, "[%s] /pmiccfg failed\n", __func__); + goto fail; + } + qclib_add_if_table_entry(QCLIB_TE_PMIC_SETTINGS, _pmic, data_size, 0); + + /* Attempt to load DCB Blob */ + data_size = cbfs_load(CONFIG_CBFS_PREFIX "/dcb", + _dcb, REGION_SIZE(dcb)); + if (!data_size) { + printk(BIOS_ERR, "[%s] /dcb failed\n", __func__); + goto fail; + } + qclib_add_if_table_entry(QCLIB_TE_DCB_SETTINGS, _dcb, data_size, 0); + /* hook for SoC specific binary blob loads */ if (qclib_soc_blob_load()) { printk(BIOS_ERR, "qclib_soc_blob_load failed\n"); diff --git a/src/soc/qualcomm/qcs405/timer.c b/src/soc/qualcomm/common/timer.c similarity index 100% rename from src/soc/qualcomm/qcs405/timer.c rename to src/soc/qualcomm/common/timer.c diff --git a/src/soc/qualcomm/qcs405/Makefile.inc b/src/soc/qualcomm/qcs405/Makefile.inc index 0766d2f..3e1bccc 100644 --- a/src/soc/qualcomm/qcs405/Makefile.inc +++ b/src/soc/qualcomm/qcs405/Makefile.inc @@ -2,50 +2,26 @@ ifeq ($(CONFIG_SOC_QUALCOMM_QCS405),y) ################################################################################ +all-y += clock.c +all-y += spi.c +all-y += ../common/timer.c +all-y += gpio.c +all-y += i2c.c +all-y += qup.c +all-y += blsp.c +all-$(CONFIG_DRIVERS_UART) += uart.c + +################################################################################ bootblock-y += bootblock.c -bootblock-y += timer.c -bootblock-y += spi.c bootblock-y += mmu.c -bootblock-y += gpio.c -bootblock-y += clock.c -bootblock-y += i2c.c -bootblock-y += qup.c -bootblock-y += blsp.c -bootblock-$(CONFIG_DRIVERS_UART) += uart.c ################################################################################ -verstage-y += timer.c -verstage-y += spi.c -verstage-y += gpio.c -verstage-y += clock.c -verstage-y += i2c.c -verstage-y += qup.c -verstage-y += blsp.c -verstage-$(CONFIG_DRIVERS_UART) += uart.c - -################################################################################ -romstage-y += timer.c -romstage-y += spi.c romstage-y += cbmem.c -romstage-y += gpio.c -romstage-y += clock.c romstage-y += usb.c -romstage-$(CONFIG_DRIVERS_UART) += uart.c -romstage-y += i2c.c -romstage-y += qup.c -romstage-y += blsp.c ################################################################################ ramstage-y += soc.c -ramstage-y += timer.c -ramstage-y += spi.c -ramstage-y += gpio.c -ramstage-y += clock.c -ramstage-y += i2c.c -ramstage-y += qup.c -ramstage-y += blsp.c ramstage-y += usb.c -ramstage-$(CONFIG_DRIVERS_UART) += uart.c ################################################################################ diff --git a/src/soc/qualcomm/sc7180/Makefile.inc b/src/soc/qualcomm/sc7180/Makefile.inc index 07d2652..e347365 100644 --- a/src/soc/qualcomm/sc7180/Makefile.inc +++ b/src/soc/qualcomm/sc7180/Makefile.inc @@ -3,68 +3,40 @@ decompressor-y += decompressor.c decompressor-y += mmu.c -decompressor-y += timer.c +decompressor-y += ../common/timer.c +all-y += ../common/timer.c +all-y += spi.c +all-y += gpio.c +all-y += qupv3_i2c.c +all-y += qupv3_spi.c +all-y += clock.c +all-$(CONFIG_SC7180_QSPI) += qspi.c +all-y += qcom_qup_se.c +all-y += qupv3_config.c ################################################################################ bootblock-y += bootblock.c bootblock-y += mmu.c -bootblock-y += timer.c -bootblock-y += spi.c -bootblock-y += qupv3_spi.c -bootblock-y += gpio.c -bootblock-y += qupv3_i2c.c bootblock-$(CONFIG_DRIVERS_UART) += uart_bitbang.c -bootblock-y += clock.c -bootblock-$(CONFIG_SC7180_QSPI) += qspi.c -bootblock-y += qupv3_config.c -bootblock-y += qcom_qup_se.c ################################################################################ -verstage-y += timer.c -verstage-y += spi.c -verstage-y += qupv3_spi.c -verstage-y += gpio.c -verstage-y += qupv3_i2c.c -verstage-y += clock.c -verstage-$(CONFIG_SC7180_QSPI) += qspi.c -verstage-y += qcom_qup_se.c -verstage-y += qupv3_config.c verstage-$(CONFIG_DRIVERS_UART) += qupv3_uart.c ################################################################################ romstage-y += cbmem.c romstage-y += watchdog.c -romstage-y += timer.c romstage-y += ../common/qclib.c -romstage-y += qclib.c romstage-y += ../common/mmu.c romstage-y += mmu.c romstage-y += usb.c -romstage-y += spi.c -romstage-y += qupv3_spi.c -romstage-y += gpio.c -romstage-y += qupv3_i2c.c -romstage-y += clock.c romstage-y += carve_out.c -romstage-$(CONFIG_SC7180_QSPI) += qspi.c -romstage-y += qcom_qup_se.c -romstage-y += qupv3_config.c romstage-$(CONFIG_DRIVERS_UART) += qupv3_uart.c ################################################################################ ramstage-y += soc.c ramstage-y += carve_out.c -ramstage-y += timer.c -ramstage-y += spi.c -ramstage-y += qupv3_spi.c -ramstage-y += gpio.c -ramstage-y += qupv3_i2c.c -ramstage-y += clock.c -ramstage-$(CONFIG_SC7180_QSPI) += qspi.c ramstage-y += aop_load_reset.c ramstage-y += usb.c -ramstage-y += qupv3_config.c -ramstage-y += qcom_qup_se.c ramstage-$(CONFIG_DRIVERS_UART) += qupv3_uart.c ramstage-$(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT) += display/dsi_phy_pll.c ramstage-$(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT) += display/dsi_phy.c diff --git a/src/soc/qualcomm/sc7180/qclib.c b/src/soc/qualcomm/sc7180/qclib.c deleted file mode 100644 index cafc970..0000000 --- a/src/soc/qualcomm/sc7180/qclib.c +++ /dev/null @@ -1,27 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <cbfs.h> -#include <fmap.h> -#include <soc/symbols_common.h> -#include <soc/qclib_common.h> - -int qclib_soc_blob_load(void) -{ - size_t size; - - /* Attempt to load PMICCFG Blob */ - size = cbfs_load(CONFIG_CBFS_PREFIX "/pmiccfg", - _pmic, REGION_SIZE(pmic)); - if (!size) - return -1; - qclib_add_if_table_entry(QCLIB_TE_PMIC_SETTINGS, _pmic, size, 0); - - /* Attempt to load DCB Blob */ - size = cbfs_load(CONFIG_CBFS_PREFIX "/dcb", - _dcb, REGION_SIZE(dcb)); - if (!size) - return -1; - qclib_add_if_table_entry(QCLIB_TE_DCB_SETTINGS, _dcb, size, 0); - - return 0; -} diff --git a/src/soc/qualcomm/sc7180/timer.c b/src/soc/qualcomm/sc7180/timer.c deleted file mode 100644 index 19e466a..0000000 --- a/src/soc/qualcomm/sc7180/timer.c +++ /dev/null @@ -1,10 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <delay.h> -#include <arch/lib_helpers.h> -#include <commonlib/helpers.h> - -void init_timer(void) -{ - raw_write_cntfrq_el0(19200*KHz); -} -- To view, visit https://review.coreboot.org/c/coreboot/+/51758 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I48464567974a0729c1c6b6157bcce4fac39a8b38 Gerrit-Change-Number: 51758 Gerrit-PatchSet: 9 Gerrit-Owner: mturney mturney <mturney(a)codeaurora.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Julius Werner <jwerner(a)chromium.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-CC: Ravi Kumar Bokka <c_rbokka(a)qualcomm.corp-partner.google.com> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/google/guybrush: Unmask eSPI keyboard IRQ
by Patrick Georgi (Code Review) 08 Apr '21

08 Apr '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/52143 ) Change subject: mb/google/guybrush: Unmask eSPI keyboard IRQ ...................................................................... mb/google/guybrush: Unmask eSPI keyboard IRQ PS/2 keyboard used IRQ 1. BUG=none TEST=Boot guybrush and see internal keyboard working Signed-off-by: Raul E Rangel <rrangel(a)chromium.org> Change-Id: I97b7382eac28aae2cc82f430c58cf8066b9701e1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52143 Reviewed-by: Furquan Shaikh <furquan(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/google/guybrush/mainboard.c 1 file changed, 5 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Furquan Shaikh: Looks good to me, approved diff --git a/src/mainboard/google/guybrush/mainboard.c b/src/mainboard/google/guybrush/mainboard.c index 57f658c..7bcbda6 100644 --- a/src/mainboard/google/guybrush/mainboard.c +++ b/src/mainboard/google/guybrush/mainboard.c @@ -1,5 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ +#include <amdblocks/acpimmio.h> #include <amdblocks/amd_pci_util.h> #include <baseboard/variants.h> #include <device/device.h> @@ -113,6 +114,10 @@ init_tables(); /* Initialize the PIRQ data structures for consumption */ pirq_setup(); + + /* TODO: b/184678786 - Move into espi_config */ + /* Unmask eSPI IRQ 1 (Keyboard) */ + pm_write32(PM_ESPI_INTR_CTRL, PM_ESPI_DEV_INTR_MASK & ~(BIT(1))); } struct chip_operations mainboard_ops = { -- To view, visit https://review.coreboot.org/c/coreboot/+/52143 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I97b7382eac28aae2cc82f430c58cf8066b9701e1 Gerrit-Change-Number: 52143 Gerrit-PatchSet: 5 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Rob Barnes <robbarnes(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/google/guybrush: Remove PS/2 mouse config
by Patrick Georgi (Code Review) 08 Apr '21

08 Apr '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/52145 ) Change subject: mb/google/guybrush: Remove PS/2 mouse config ...................................................................... mb/google/guybrush: Remove PS/2 mouse config Guybrush doesn't have a PS/2 mouse. BUG=none TEST=boot guybrush to the OS Signed-off-by: Raul E Rangel <rrangel(a)chromium.org> Change-Id: I87e51d23b69cfd6ad7bb88b364714d679e92728f Reviewed-on: https://review.coreboot.org/c/coreboot/+/52145 Reviewed-by: Martin Roth <martinroth(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/google/guybrush/variants/baseboard/devicetree.cb 1 file changed, 1 insertion(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Martin Roth: Looks good to me, approved diff --git a/src/mainboard/google/guybrush/variants/baseboard/devicetree.cb b/src/mainboard/google/guybrush/variants/baseboard/devicetree.cb index f5f9018..5e9037a 100644 --- a/src/mainboard/google/guybrush/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/guybrush/variants/baseboard/devicetree.cb @@ -35,7 +35,7 @@ .oob_ch_en = 0, .flash_ch_en = 0, - .vw_irq_polarity = ESPI_VW_IRQ_LEVEL_HIGH(1) | ESPI_VW_IRQ_LEVEL_HIGH(12), + .vw_irq_polarity = ESPI_VW_IRQ_LEVEL_HIGH(1), }" register "i2c_scl_reset" = "GPIO_I2C0_SCL | GPIO_I2C1_SCL | -- To view, visit https://review.coreboot.org/c/coreboot/+/52145 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I87e51d23b69cfd6ad7bb88b364714d679e92728f Gerrit-Change-Number: 52145 Gerrit-PatchSet: 2 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/amd/common: Add PM_ESPI_INTR_CTRL
by Patrick Georgi (Code Review) 08 Apr '21

08 Apr '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/52142 ) Change subject: soc/amd/common: Add PM_ESPI_INTR_CTRL ...................................................................... soc/amd/common: Add PM_ESPI_INTR_CTRL This register is used for masking/unmasking eSPI IRQs. BUG=none TEST=Build guybrush Signed-off-by: Raul E Rangel <rrangel(a)chromium.org> Change-Id: Ia209539b2e0ce390e227757b16c2969b9124a845 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52142 Reviewed-by: Martin Roth <martinroth(a)google.com> Reviewed-by: Rob Barnes <robbarnes(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/amd/common/block/include/amdblocks/acpimmio.h 1 file changed, 2 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Martin Roth: Looks good to me, approved Rob Barnes: Looks good to me, approved diff --git a/src/soc/amd/common/block/include/amdblocks/acpimmio.h b/src/soc/amd/common/block/include/amdblocks/acpimmio.h index 9360650..9c007e7 100644 --- a/src/soc/amd/common/block/include/amdblocks/acpimmio.h +++ b/src/soc/amd/common/block/include/amdblocks/acpimmio.h @@ -26,6 +26,8 @@ #define LEGACY_DMA_IO_EN (1 << 2) #define CF9_IO_EN (1 << 1) #define LEGACY_IO_EN (1 << 0) +#define PM_ESPI_INTR_CTRL 0x40 +#define PM_ESPI_DEV_INTR_MASK 0x00FFFFFF #define PM_RST_CTRL1 0xbe #define SLPTYPE_CONTROL_EN (1 << 5) #define KBRSTEN (1 << 4) -- To view, visit https://review.coreboot.org/c/coreboot/+/52142 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia209539b2e0ce390e227757b16c2969b9124a845 Gerrit-Change-Number: 52142 Gerrit-PatchSet: 2 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Rob Barnes <robbarnes(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/google/guybrush: PCIe GPIOs - enable enables, disable resets
by Patrick Georgi (Code Review) 08 Apr '21

08 Apr '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/52115 ) Change subject: mb/google/guybrush: PCIe GPIOs - enable enables, disable resets ...................................................................... mb/google/guybrush: PCIe GPIOs - enable enables, disable resets To train PCIe devices, the devices need to be enabled and taken out of reset. This patch does the bare minimum needed to train PCIe. It is not intended to handle timings, which will be addressed later. Copy the enables for WWAN & WLAN into early GPIO Init so that they're enabled before FSP-M runs and trains the PCIe busses. Again, this patch is the minimum to let the FSP train the PCIe busses. BUG=b:182202136 TEST=Boot guybrush from NVME. Signed-off-by: Martin Roth <martinroth(a)chromium.org> Change-Id: I3807e02de1e9ae40b0a4162217afd6aabb5b04ed Reviewed-on: https://review.coreboot.org/c/coreboot/+/52115 Reviewed-by: Raul Rangel <rrangel(a)chromium.org> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/google/guybrush/variants/baseboard/gpio.c 1 file changed, 16 insertions(+), 8 deletions(-) Approvals: build bot (Jenkins): Verified Raul Rangel: Looks good to me, approved diff --git a/src/mainboard/google/guybrush/variants/baseboard/gpio.c b/src/mainboard/google/guybrush/variants/baseboard/gpio.c index 719590f..4f04c08 100644 --- a/src/mainboard/google/guybrush/variants/baseboard/gpio.c +++ b/src/mainboard/google/guybrush/variants/baseboard/gpio.c @@ -20,11 +20,11 @@ /* EN_PP5000_PEN */ PAD_GPO(GPIO_5, LOW), /* EN_PP3300_WLAN */ - PAD_GPO(GPIO_6, LOW), + PAD_GPO(GPIO_6, HIGH), /* EN_PP3300_TCHPAD */ PAD_GPO(GPIO_7, HIGH), /* EN_PWR_WWAN_X */ - PAD_GPO(GPIO_8, LOW), + PAD_GPO(GPIO_8, HIGH), /* SOC_TCHPAD_INT_ODL */ PAD_INT(GPIO_9, PULL_NONE, EDGE_HIGH, STATUS_DELIVERY), /* S0A3 */ @@ -51,7 +51,7 @@ /* AC_PRES */ PAD_NF(GPIO_23, AC_PRES, PULL_UP), /* WWAN_RST_L */ - PAD_GPO(GPIO_24, LOW), + PAD_GPO(GPIO_24, HIGH), /* GPIO_25: Not available */ /* PCIE_RST0_L */ /* TODO: change back to PCIE_RST_L when we figure out why PCIE_RST doesn't go high. */ @@ -60,7 +60,7 @@ PAD_NF(GPIO_27, PCIE_RST1_L, PULL_NONE), /* GPIO_28: Not available */ /* WLAN_AUX_RESET */ - PAD_GPO(GPIO_29, HIGH), + PAD_GPO(GPIO_29, LOW), /* ESPI_CS_L */ PAD_NF(GPIO_30, ESPI_CS_L, PULL_NONE), /* SPI_CS3_L */ @@ -69,7 +69,7 @@ PAD_GPO(GPIO_32, LOW), /* GPIO_33 - GPIO_39: Not available */ /* SSD_AUX_RESET_L */ - PAD_GPO(GPIO_40, LOW), + PAD_GPO(GPIO_40, HIGH), /* GPIO_41: Not available */ /* WWAN_DPR_SAR_ODL */ PAD_GPO(GPIO_42, LOW), @@ -81,7 +81,7 @@ /* EN_SPKR */ PAD_GPO(GPIO_69, LOW), /* SD_AUX_RESET_L */ - PAD_GPO(GPIO_70, LOW), + PAD_GPO(GPIO_70, HIGH), /* GPIO_71 - GPIO_73: Not available */ /* RAM_ID_CHAN_SEL */ PAD_GPI(GPIO_74, PULL_NONE), @@ -93,7 +93,7 @@ /* EC_SOC_INT_ODL */ PAD_GPI(GPIO_84, PULL_NONE), /* WWAN_DISABLE */ - PAD_GPO(GPIO_85, HIGH), + PAD_GPO(GPIO_85, LOW), /* ESPI_SOC_CLK */ PAD_NF(GPIO_86, SPI_CLK, PULL_NONE), /* RAM_ID_1 / DEV_BEEP_DATA */ @@ -139,7 +139,7 @@ /* SOC_DISABLE_DISP_BL */ PAD_GPO(GPIO_129, LOW), /* WLAN_DISABLE */ - PAD_GPO(GPIO_130, HIGH), + PAD_GPO(GPIO_130, LOW), /* CLK_REQ3_L */ PAD_NF(GPIO_131, CLK_REQ3_L, PULL_NONE), /* BT_DISABLE */ @@ -166,6 +166,14 @@ /* Early GPIO configuration */ static const struct soc_amd_gpio early_gpio_table[] = { + /* EN_PP3300_WLAN */ + PAD_GPO(GPIO_6, HIGH), + /* EN_PWR_WWAN_X */ + PAD_GPO(GPIO_8, HIGH), + /* WWAN_DISABLE */ + PAD_GPO(GPIO_85, LOW), + /* WLAN_DISABLE */ + PAD_GPO(GPIO_130, LOW), /* GSC_SOC_INT_L */ PAD_INT(GPIO_3, PULL_NONE, EDGE_LOW, STATUS_DELIVERY), /* I2C3_SCL */ -- To view, visit https://review.coreboot.org/c/coreboot/+/52115 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3807e02de1e9ae40b0a4162217afd6aabb5b04ed Gerrit-Change-Number: 52115 Gerrit-PatchSet: 3 Gerrit-Owner: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Furquan Shaikh <furquan(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: merged

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coreboot-gerrit April 2021