coreboot-gerrit April 2021

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Change in coreboot[master]: soc/intel/{cannonlake,icelake}: Drop unhooked `SendVrMbxCmd`
by Patrick Georgi (Code Review) 08 Apr '21

08 Apr '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/52102 ) Change subject: soc/intel/{cannonlake,icelake}: Drop unhooked `SendVrMbxCmd` ...................................................................... soc/intel/{cannonlake,icelake}: Drop unhooked `SendVrMbxCmd` This option's value is not used anywhere. Remove it. Change-Id: I0f30cddd30d459f48b51f377b111bbc04709c5f8 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52102 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Felix Singer <felixsinger(a)posteo.net> Reviewed-by: Michael Niewöhner <foss(a)mniewoehner.de> --- M src/mainboard/clevo/cml-u/variants/l140cu/devicetree.cb M src/mainboard/system76/lemp9/devicetree.cb M src/soc/intel/cannonlake/chip.h M src/soc/intel/icelake/chip.h 4 files changed, 0 insertions(+), 20 deletions(-) Approvals: build bot (Jenkins): Verified Felix Singer: Looks good to me, approved Michael Niewöhner: Looks good to me, but someone else must approve diff --git a/src/mainboard/clevo/cml-u/variants/l140cu/devicetree.cb b/src/mainboard/clevo/cml-u/variants/l140cu/devicetree.cb index fed1325..05f2a56 100644 --- a/src/mainboard/clevo/cml-u/variants/l140cu/devicetree.cb +++ b/src/mainboard/clevo/cml-u/variants/l140cu/devicetree.cb @@ -9,9 +9,6 @@ }, }" - # Send an extra VR mailbox command for the PS4 exit issue - register "SendVrMbxCmd" = "2" - # CPU (soc/intel/cannonlake/cpu.c) # Power limit register "power_limits_config" = "{ diff --git a/src/mainboard/system76/lemp9/devicetree.cb b/src/mainboard/system76/lemp9/devicetree.cb index 313329a..a0b6403 100644 --- a/src/mainboard/system76/lemp9/devicetree.cb +++ b/src/mainboard/system76/lemp9/devicetree.cb @@ -9,9 +9,6 @@ }, }" - # Send an extra VR mailbox command for the PS4 exit issue - register "SendVrMbxCmd" = "2" - # CPU (soc/intel/cannonlake/cpu.c) # Power limit register "power_limits_config" = "{ diff --git a/src/soc/intel/cannonlake/chip.h b/src/soc/intel/cannonlake/chip.h index f9f761b..f84a480 100644 --- a/src/soc/intel/cannonlake/chip.h +++ b/src/soc/intel/cannonlake/chip.h @@ -223,13 +223,6 @@ /* Enables support for Teton Glacier hybrid storage device */ uint8_t TetonGlacierMode; - /* Enable VR specific mailbox command - * 00b - no VR specific cmd sent - * 01b - VR mailbox cmd specifically for the MPS IMPV8 VR will be sent - * 10b - VR specific cmd sent for PS4 exit issue - * 11b - Reserved */ - uint8_t SendVrMbxCmd; - /* Enable/Disable EIST. 1b:Enabled, 0b:Disabled */ uint8_t eist_enable; diff --git a/src/soc/intel/icelake/chip.h b/src/soc/intel/icelake/chip.h index b878fd6..bef9adb 100644 --- a/src/soc/intel/icelake/chip.h +++ b/src/soc/intel/icelake/chip.h @@ -138,13 +138,6 @@ * Setting to 0 (default) disables Heci1 and hides the device from OS */ uint8_t HeciEnabled; - /* Enable VR specific mailbox command - * 00b - no VR specific cmd sent - * 01b - VR mailbox cmd specifically for the MPS IMPV8 VR will be sent - * 10b - VR specific cmd sent for PS4 exit issue - * 11b - Reserved */ - uint8_t SendVrMbxCmd; - /* Enable/Disable EIST. 1b:Enabled, 0b:Disabled */ uint8_t eist_enable; -- To view, visit https://review.coreboot.org/c/coreboot/+/52102 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0f30cddd30d459f48b51f377b111bbc04709c5f8 Gerrit-Change-Number: 52102 Gerrit-PatchSet: 3 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Jeremy Soller <jeremy(a)system76.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/intel/skylake: Drop unnecessary `ignore_vtd` option
by Patrick Georgi (Code Review) 08 Apr '21

08 Apr '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/52101 ) Change subject: soc/intel/skylake: Drop unnecessary `ignore_vtd` option ...................................................................... soc/intel/skylake: Drop unnecessary `ignore_vtd` option It is zero for all mainboards. If one really wanted to ignore VT-d support, a user-visible Kconfig option would be a better approach. Change-Id: I320c10317f3fabee5443c16ebdf1ffd0e24193b8 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52101 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Michael Niewöhner <foss(a)mniewoehner.de> Reviewed-by: Felix Singer <felixsinger(a)posteo.net> --- M src/mainboard/protectli/vault_kbl/devicetree.cb M src/soc/intel/skylake/acpi.c M src/soc/intel/skylake/chip.c M src/soc/intel/skylake/chip.h M src/soc/intel/skylake/romstage/systemagent.c M src/soc/intel/skylake/systemagent.c 6 files changed, 3 insertions(+), 16 deletions(-) Approvals: build bot (Jenkins): Verified Felix Singer: Looks good to me, approved Michael Niewöhner: Looks good to me, approved diff --git a/src/mainboard/protectli/vault_kbl/devicetree.cb b/src/mainboard/protectli/vault_kbl/devicetree.cb index abbfda4..dc73f91 100644 --- a/src/mainboard/protectli/vault_kbl/devicetree.cb +++ b/src/mainboard/protectli/vault_kbl/devicetree.cb @@ -22,9 +22,6 @@ # Disable DPTF register "dptf_enable" = "0" - # Enable VT-d - register "ignore_vtd" = "0" - # Enable SERIRQ continuous register "serirq_mode" = "SERIRQ_CONTINUOUS" diff --git a/src/soc/intel/skylake/acpi.c b/src/soc/intel/skylake/acpi.c index 0d89f29..3434aac 100644 --- a/src/soc/intel/skylake/acpi.c +++ b/src/soc/intel/skylake/acpi.c @@ -460,11 +460,10 @@ unsigned long current, struct acpi_rsdp *const rsdp) { - const struct soc_intel_skylake_config *const config = config_of(dev); acpi_dmar_t *const dmar = (acpi_dmar_t *)current; /* Create DMAR table only if we have VT-d capability. */ - if (config->ignore_vtd || !soc_is_vtd_capable()) + if (!soc_is_vtd_capable()) return current; printk(BIOS_DEBUG, "ACPI: * DMAR\n"); diff --git a/src/soc/intel/skylake/chip.c b/src/soc/intel/skylake/chip.c index 0ae98a9..d4d8938 100644 --- a/src/soc/intel/skylake/chip.c +++ b/src/soc/intel/skylake/chip.c @@ -524,7 +524,7 @@ params->PchIoApicBdfValid = 0; /* Enable VT-d and X2APIC */ - if (!config->ignore_vtd && soc_is_vtd_capable()) { + if (soc_is_vtd_capable()) { params->VtdBaseAddress[0] = GFXVT_BASE_ADDRESS; params->VtdBaseAddress[1] = VTVC0_BASE_ADDRESS; params->X2ApicOptOut = 0; diff --git a/src/soc/intel/skylake/chip.h b/src/soc/intel/skylake/chip.h index 99eb8e6..1c8ca49 100644 --- a/src/soc/intel/skylake/chip.h +++ b/src/soc/intel/skylake/chip.h @@ -78,9 +78,6 @@ /* TCC activation offset */ uint32_t tcc_offset; - /* Whether to ignore VT-d support of the SKU */ - int ignore_vtd; - /* * System Agent dynamic frequency configuration * When enabled memory will be trained at two different frequencies. diff --git a/src/soc/intel/skylake/romstage/systemagent.c b/src/soc/intel/skylake/romstage/systemagent.c index f22fd53..8996bce 100644 --- a/src/soc/intel/skylake/romstage/systemagent.c +++ b/src/soc/intel/skylake/romstage/systemagent.c @@ -13,11 +13,6 @@ static void systemagent_vtd_init(void) { const struct device *const igd_dev = pcidev_path_on_root(SA_DEVFN_IGD); - const struct soc_intel_skylake_config *config = NULL; - - config = config_of_soc(); - if (config->ignore_vtd) - return; const bool vtd_capable = !(pci_read_config32(SA_DEV_ROOT, CAPID0_A) & VTD_DISABLE); diff --git a/src/soc/intel/skylake/systemagent.c b/src/soc/intel/skylake/systemagent.c index 785a5e6..8b64435 100644 --- a/src/soc/intel/skylake/systemagent.c +++ b/src/soc/intel/skylake/systemagent.c @@ -39,12 +39,11 @@ { GDXCBAR, GDXC_BASE_ADDRESS, GDXC_BASE_SIZE, "GDXCBAR" }, { EDRAMBAR, EDRAM_BASE_ADDRESS, EDRAM_BASE_SIZE, "EDRAMBAR" }, }; - const struct soc_intel_skylake_config *const config = config_of(dev); sa_add_fixed_mmio_resources(dev, index, soc_fixed_resources, ARRAY_SIZE(soc_fixed_resources)); - if (!config->ignore_vtd && soc_is_vtd_capable()) { + if (soc_is_vtd_capable()) { if (igd_dev && igd_dev->enabled) sa_add_fixed_mmio_resources(dev, index, &soc_gfxvt_mmio_descriptor, 1); -- To view, visit https://review.coreboot.org/c/coreboot/+/52101 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I320c10317f3fabee5443c16ebdf1ffd0e24193b8 Gerrit-Change-Number: 52101 Gerrit-PatchSet: 3 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/intel: Hook up `SOC_INTEL_DISABLE_IGD` to `InternalGfx` UPD
by Patrick Georgi (Code Review) 08 Apr '21

08 Apr '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/52100 ) Change subject: soc/intel: Hook up `SOC_INTEL_DISABLE_IGD` to `InternalGfx` UPD ...................................................................... soc/intel: Hook up `SOC_INTEL_DISABLE_IGD` to `InternalGfx` UPD Commit 0591348833f730a42e74039d8e2d957ec94a39d5 introduced this Kconfig option inside soc/intel/common scope. However, it was only hooked up in commit d74cd60b8159c3928dba318e6387f200ff3bb0e7 for Alder Lake, and in commit 99157c1f4a80556462ca22a4ade87b2c8d09e674 for Tiger Lake. Hook up the `SOC_INTEL_DISABLE_IGD` Kconfig option to all other platforms which have the `InternalGfx` UPD. Change-Id: Icd1379a835b445a6d4b028ebde5a3e355ee5b67b Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52100 Reviewed-by: Michael Niewöhner <foss(a)mniewoehner.de> Reviewed-by: Felix Singer <felixsinger(a)posteo.net> Reviewed-by: Nico Huber <nico.h(a)gmx.de> Reviewed-by: Subrata Banik <subrata.banik(a)intel.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/intel/cannonlake/romstage/fsp_params.c M src/soc/intel/icelake/romstage/fsp_params.c M src/soc/intel/jasperlake/romstage/fsp_params.c M src/soc/intel/skylake/romstage/fsp_params.c 4 files changed, 7 insertions(+), 5 deletions(-) Approvals: build bot (Jenkins): Verified Nico Huber: Looks good to me, but someone else must approve Subrata Banik: Looks good to me, approved Felix Singer: Looks good to me, approved Michael Niewöhner: Looks good to me, approved diff --git a/src/soc/intel/cannonlake/romstage/fsp_params.c b/src/soc/intel/cannonlake/romstage/fsp_params.c index d55741f..c1fe5a7 100644 --- a/src/soc/intel/cannonlake/romstage/fsp_params.c +++ b/src/soc/intel/cannonlake/romstage/fsp_params.c @@ -12,6 +12,7 @@ #include <soc/msr.h> #include <soc/pci_devs.h> #include <soc/romstage.h> +#include <types.h> #include <vendorcode/google/chromeos/chromeos.h> #include "../chip.h" @@ -29,7 +30,8 @@ * Probe for no IGD and disable InternalGfx and panel power to prevent a * crash in FSP-M. */ - if (dev && dev->enabled && pci_read_config16(SA_DEV_IGD, PCI_VENDOR_ID) != 0xffff) { + const bool igd_on = !CONFIG(SOC_INTEL_DISABLE_IGD) && dev && dev->enabled; + if (igd_on && pci_read_config16(SA_DEV_IGD, PCI_VENDOR_ID) != 0xffff) { /* Set IGD stolen size to 64MB. */ m_cfg->InternalGfx = 1; m_cfg->IgdDvmt50PreAlloc = 2; diff --git a/src/soc/intel/icelake/romstage/fsp_params.c b/src/soc/intel/icelake/romstage/fsp_params.c index 0801da2..a5311d9 100644 --- a/src/soc/intel/icelake/romstage/fsp_params.c +++ b/src/soc/intel/icelake/romstage/fsp_params.c @@ -16,8 +16,8 @@ const struct device *dev = pcidev_path_on_root(SA_DEVFN_IGD); uint32_t mask = 0; - if (!dev || !dev->enabled) { - /* Skip IGD initialization in FSP if device is disabled in devicetree.cb. */ + if (CONFIG(SOC_INTEL_DISABLE_IGD) || !dev || !dev->enabled) { + /* Skip IGD initialization in FSP if device is disabled */ m_cfg->InternalGfx = 0; m_cfg->IgdDvmt50PreAlloc = 0; } else { diff --git a/src/soc/intel/jasperlake/romstage/fsp_params.c b/src/soc/intel/jasperlake/romstage/fsp_params.c index cd70807..7100232 100644 --- a/src/soc/intel/jasperlake/romstage/fsp_params.c +++ b/src/soc/intel/jasperlake/romstage/fsp_params.c @@ -22,7 +22,7 @@ * Otherwise, skip IGD init in FSP. */ dev = pcidev_path_on_root(SA_DEVFN_IGD); - m_cfg->InternalGfx = is_dev_enabled(dev); + m_cfg->InternalGfx = !CONFIG(SOC_INTEL_DISABLE_IGD) && is_dev_enabled(dev); m_cfg->IgdDvmt50PreAlloc = m_cfg->InternalGfx ? 0xFE : 0; m_cfg->TsegSize = CONFIG_SMM_TSEG_SIZE; diff --git a/src/soc/intel/skylake/romstage/fsp_params.c b/src/soc/intel/skylake/romstage/fsp_params.c index 2793c2d..6c6e2e6 100644 --- a/src/soc/intel/skylake/romstage/fsp_params.c +++ b/src/soc/intel/skylake/romstage/fsp_params.c @@ -112,7 +112,7 @@ const struct device *dev; dev = pcidev_path_on_root(SA_DEVFN_IGD); - m_cfg->InternalGfx = dev && dev->enabled; + m_cfg->InternalGfx = !CONFIG(SOC_INTEL_DISABLE_IGD) && dev && dev->enabled; /* * If iGPU is enabled, set IGD stolen size to 64MB. The FBC -- To view, visit https://review.coreboot.org/c/coreboot/+/52100 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icd1379a835b445a6d4b028ebde5a3e355ee5b67b Gerrit-Change-Number: 52100 Gerrit-PatchSet: 3 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/google/brya: Change GPP_D15/D16 default to low
by Patrick Georgi (Code Review) 08 Apr '21

08 Apr '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/52148 ) Change subject: mb/google/brya: Change GPP_D15/D16 default to low ...................................................................... mb/google/brya: Change GPP_D15/D16 default to low WFC Camera driver will control the power sequence. Therefore, set default to low. BUG=b:184024459 TEST=abuilds Signed-off-by: Eric Lai <ericr_lai(a)compal.corp-partner.google.com> Change-Id: I7ce25b83a715a022e36289dc0abf0d39f5798eb0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52148 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Furquan Shaikh <furquan(a)google.com> --- M src/mainboard/google/brya/variants/baseboard/gpio.c 1 file changed, 2 insertions(+), 2 deletions(-) Approvals: build bot (Jenkins): Verified Furquan Shaikh: Looks good to me, approved diff --git a/src/mainboard/google/brya/variants/baseboard/gpio.c b/src/mainboard/google/brya/variants/baseboard/gpio.c index 6482b9c..dd33b49 100644 --- a/src/mainboard/google/brya/variants/baseboard/gpio.c +++ b/src/mainboard/google/brya/variants/baseboard/gpio.c @@ -148,9 +148,9 @@ /* D14 : ISH_UART0_TXD ==> PCH_I2C_CAM_SCL */ PAD_CFG_NF(GPP_D14, NONE, DEEP, NF3), /* D15 : ISH_UART0_RTS# ==> EN_WCAM_SENR_PWR */ - PAD_CFG_GPO(GPP_D15, 1, DEEP), + PAD_CFG_GPO(GPP_D15, 0, DEEP), /* D16 : ISH_UART0_CTS# ==> EN_WCAM_PWR */ - PAD_CFG_GPO(GPP_D16, 1, DEEP), + PAD_CFG_GPO(GPP_D16, 0, DEEP), /* D17 : UART1_RXD ==> SD_PE_PRSNT_L */ PAD_CFG_GPI(GPP_D17, NONE, DEEP), /* D18 : UART1_TXD ==> SD_PE_RST_L */ -- To view, visit https://review.coreboot.org/c/coreboot/+/52148 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7ce25b83a715a022e36289dc0abf0d39f5798eb0 Gerrit-Change-Number: 52148 Gerrit-PatchSet: 3 Gerrit-Owner: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Meera Ravindranath <meera.ravindranath(a)intel.corp-partner.google.com> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/google/guybrush/var/guybrush: Add FPMCU configration
by Ivy Jian (Code Review) 08 Apr '21

08 Apr '21

Attention is currently required from: Mathew King, Bhanu Prakash Maiya, Ivy Jian. Hello build bot (Jenkins), Patrick Georgi, Martin Roth, Mathew King, Bhanu Prakash Maiya, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/52181 to look at the new patch set (#5). Change subject: mb/google/guybrush/var/guybrush: Add FPMCU configration ...................................................................... mb/google/guybrush/var/guybrush: Add FPMCU configration Enable CRFP in devicetree. Update gpios for FPMCU power ready. BUG=b:182201937 BRANCH=None TEST=Boot into OS and check FPMCU is responding. Signed-off-by: Ivy Jian <ivy_jian(a)compal.corp-partner.google.com> Change-Id: I7c56b0db193be6804d07c2f333445c2a1dbf9f59 --- M src/mainboard/google/guybrush/Kconfig M src/mainboard/google/guybrush/mainboard.c M src/mainboard/google/guybrush/variants/baseboard/include/baseboard/variants.h M src/mainboard/google/guybrush/variants/guybrush/Makefile.inc M src/mainboard/google/guybrush/variants/guybrush/overridetree.cb A src/mainboard/google/guybrush/variants/guybrush/variant.c 6 files changed, 41 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/81/52181/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/52181 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7c56b0db193be6804d07c2f333445c2a1dbf9f59 Gerrit-Change-Number: 52181 Gerrit-PatchSet: 5 Gerrit-Owner: Ivy Jian <ivy_jian(a)compal.corp-partner.google.com> Gerrit-Reviewer: Bhanu Prakash Maiya <bhanumaiya(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Mathew King <mathewk(a)chromium.org> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Mathew King <mathewk(a)chromium.org> Gerrit-Attention: Bhanu Prakash Maiya <bhanumaiya(a)google.com> Gerrit-Attention: Ivy Jian <ivy_jian(a)compal.corp-partner.google.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/google/zork/var/shuboz: update USB OC pin mapping
by Kane Chen (Code Review) 08 Apr '21

08 Apr '21

Attention is currently required from: Kangheui Won. Kane Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/51523 ) Change subject: mb/google/zork/var/shuboz: update USB OC pin mapping ...................................................................... Patch Set 5: (1 comment) File src/mainboard/google/zork/variants/shuboz/overridetree.cb: https://review.coreboot.org/c/coreboot/+/51523/comment/2079b317_fe840160 PS5, Line 28: register "usb_port_overcurrent_pin[1]" = "USB_OC_PIN_0" # USB A0 > Got it, but why usb_port_overcurrent_pin[2] is USB_OC_NONE? Isn't it connected to USB A1? Hi Kangheui, usb_port_overcurrent_pin[2] it will use to 2nd camera in Jelboz360, so we modify this setting to none. -- To view, visit https://review.coreboot.org/c/coreboot/+/51523 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icc1fa090109e6be54e2a5f49e364f5502f53aca2 Gerrit-Change-Number: 51523 Gerrit-PatchSet: 5 Gerrit-Owner: Kane Chen <kane_chen(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Kane Chen <kane_chen(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com> Gerrit-CC: Hank Lin <hank2_lin(a)pegatron.corp-partner.google.com> Gerrit-CC: Ken Lu <ken_lu(a)pegatron.corp-partner.google.com> Gerrit-Attention: Kangheui Won <khwon(a)chromium.org> Gerrit-Comment-Date: Thu, 08 Apr 2021 06:07:24 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Kangheui Won <khwon(a)chromium.org> Comment-In-Reply-To: Kane Chen <kane_chen(a)pegatron.corp-partner.google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/guybrush/var/guybrush: Add FPMCU configration
by Furquan Shaikh (Code Review) 08 Apr '21

08 Apr '21

Attention is currently required from: Mathew King, Bhanu Prakash Maiya, Ivy Jian. Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52181 ) Change subject: mb/google/guybrush/var/guybrush: Add FPMCU configration ...................................................................... Patch Set 4: (2 comments) File src/mainboard/google/guybrush/variants/guybrush/overridetree.cb: https://review.coreboot.org/c/coreboot/+/52181/comment/b09d0726_4bc2e0e3 PS4, Line 101: Use tabs instead of spaces here and in the below lines. File src/mainboard/google/guybrush/variants/guybrush/variant.c: https://review.coreboot.org/c/coreboot/+/52181/comment/e293c8b9_3d32c7e5 PS4, Line 8: variant_fpmcu_init I think instead of adding a special function to handle the power-on, we should invest in adding a special driver for the FPMCU device that does the power sequencing as part of ACPI. It will eliminate the need for this variant function completely. -- To view, visit https://review.coreboot.org/c/coreboot/+/52181 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7c56b0db193be6804d07c2f333445c2a1dbf9f59 Gerrit-Change-Number: 52181 Gerrit-PatchSet: 4 Gerrit-Owner: Ivy Jian <ivy_jian(a)compal.corp-partner.google.com> Gerrit-Reviewer: Bhanu Prakash Maiya <bhanumaiya(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Mathew King <mathewk(a)chromium.org> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Mathew King <mathewk(a)chromium.org> Gerrit-Attention: Bhanu Prakash Maiya <bhanumaiya(a)google.com> Gerrit-Attention: Ivy Jian <ivy_jian(a)compal.corp-partner.google.com> Gerrit-Comment-Date: Thu, 08 Apr 2021 06:06:55 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel: reintroduce PAD_CFG_NC macro for unconnected pads w/o pull
by Frans Hendriks (Code Review) 08 Apr '21

08 Apr '21

Attention is currently required from: Felix Singer, Nico Huber, Furquan Shaikh, Matt DeVillier, Michael Niewöhner, Tim Wawrzynczak, Patrick Rudolph. Frans Hendriks has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52139 ) Change subject: soc/intel: reintroduce PAD_CFG_NC macro for unconnected pads w/o pull ...................................................................... Patch Set 4: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/52139 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id01b197ebe8f2b8bb4ecf3d119ec2298b26d9be0 Gerrit-Change-Number: 52139 Gerrit-PatchSet: 4 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Attention: Felix Singer <felixsinger(a)posteo.net> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Attention: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)google.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Thu, 08 Apr 2021 06:05:15 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/*: use new macro PAD_CFG_NC for unconnected pads w/o pull resistor
by Frans Hendriks (Code Review) 08 Apr '21

08 Apr '21

Attention is currently required from: Felix Singer, Furquan Shaikh, Patrick Rudolph, Jonathan Zhang, Jeremy Soller, Michael Niewöhner, Piotr Król, Anjaneya "Reddy" Chagam, Nico Huber, Michał Żygowski, Johnny Lin, Tim Wawrzynczak, Christian Walter, Morgan Jang, Wim Vervoorn. Frans Hendriks has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52146 ) Change subject: mb/*: use new macro PAD_CFG_NC for unconnected pads w/o pull resistor ...................................................................... Patch Set 2: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/52146 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I793d6425756266e37deea1a9bcc93d01904561cb Gerrit-Change-Number: 52146 Gerrit-PatchSet: 2 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Anjaneya "Reddy" Chagam <anjaneya.chagam(a)intel.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Jeremy Soller <jeremy(a)system76.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Morgan Jang <Morgan_Jang(a)wiwynn.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Wim Vervoorn <wvervoorn(a)eltan.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Felix Singer <felixsinger(a)posteo.net> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Attention: Jeremy Soller <jeremy(a)system76.com> Gerrit-Attention: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Attention: Anjaneya "Reddy" Chagam <anjaneya.chagam(a)intel.com> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Morgan Jang <Morgan_Jang(a)wiwynn.com> Gerrit-Attention: Wim Vervoorn <wvervoorn(a)eltan.com> Gerrit-Comment-Date: Thu, 08 Apr 2021 06:05:07 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/guybrush/var/guybrush: Add FPMCU configration
by Ivy Jian (Code Review) 08 Apr '21

08 Apr '21

Attention is currently required from: Mathew King, Bhanu Prakash Maiya. Ivy Jian has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52181 ) Change subject: mb/google/guybrush/var/guybrush: Add FPMCU configration ...................................................................... Patch Set 4: (4 comments) This change is ready for review. File src/mainboard/google/guybrush/mainboard.c: https://review.coreboot.org/c/coreboot/+/52181/comment/bf3cf21f_eebbdbba PS1, Line 121: /* Default weak implementation */ > code indent should use tabs where possible done File src/mainboard/google/guybrush/variants/guybrush/variant.c: https://review.coreboot.org/c/coreboot/+/52181/comment/8d36da67_d817d824 PS1, Line 14: gpio_set(GPIO_32, 1); > please, no spaces at the start of a line done https://review.coreboot.org/c/coreboot/+/52181/comment/ed80f9d7_1214d0f2 PS1, Line 15: mdelay(3); > please, no spaces at the start of a line done https://review.coreboot.org/c/coreboot/+/52181/comment/7bf2e7c8_806870e1 PS1, Line 16: gpio_set(GPIO_11, 1); > please, no spaces at the start of a line done -- To view, visit https://review.coreboot.org/c/coreboot/+/52181 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7c56b0db193be6804d07c2f333445c2a1dbf9f59 Gerrit-Change-Number: 52181 Gerrit-PatchSet: 4 Gerrit-Owner: Ivy Jian <ivy_jian(a)compal.corp-partner.google.com> Gerrit-Reviewer: Bhanu Prakash Maiya <bhanumaiya(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Mathew King <mathewk(a)chromium.org> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Mathew King <mathewk(a)chromium.org> Gerrit-Attention: Bhanu Prakash Maiya <bhanumaiya(a)google.com> Gerrit-Comment-Date: Thu, 08 Apr 2021 06:04:53 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: comment

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