coreboot-gerrit April 2021

coreboot-gerrit@coreboot.org

1 participants
6269 discussions

Change in coreboot[master]: soc/mediatek: add new driver 'msdc' for eMMC
by Wenbin Mei (Code Review) 07 Apr '21

07 Apr '21

Attention is currently required from: Hung-Te Lin, Angel Pons, Wenbin Mei, Yu-Ping Wu. Wenbin Mei has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/51966 ) Change subject: soc/mediatek: add new driver 'msdc' for eMMC ...................................................................... Patch Set 11: (6 comments) File src/soc/mediatek/common/include/soc/msdc.h: https://review.coreboot.org/c/coreboot/+/51966/comment/c8f467e0_479be9e5 PS10, Line 154: Io > IO Ack https://review.coreboot.org/c/coreboot/+/51966/comment/623c7d82_91f5a6cb PS10, Line 155: io > IO Ack File src/soc/mediatek/common/include/soc/msdc.h: https://review.coreboot.org/c/coreboot/+/51966/comment/ced93769_de2a0bd4 PS9, Line 11: > Use tabs for alignment? Done File src/soc/mediatek/common/include/soc/msdc.h: https://review.coreboot.org/c/coreboot/+/51966/comment/102e4774_bfb6198f PS5, Line 18: #define MSDC_CFG 0x0 : #define MSDC_IOCON 0x04 : #define MSDC_PS 0x08 : #define MSDC_INT 0x0c : #define MSDC_INTEN 0x10 : #define MSDC_FIFOCS 0x14 : #define MSDC_TXDATA 0x18 : #define MSDC_RXDATA 0x1c : #define SDC_CFG 0x30 : #define SDC_CMD 0x34 : #define SDC_ARG 0x38 : #define SDC_STS 0x3c : #define SDC_RESP0 0x40 : #define SDC_RESP1 0x44 : #define SDC_RESP2 0x48 : #define SDC_RESP3 0x4c : #define SDC_BLK_NUM 0x50 : #define SDC_ADV_CFG0 0x64 : #define EMMC_IOCON 0x7c : #define SDC_ACMD_RESP 0x80 : #define DMA_SA_H4BIT 0x8c : #define MSDC_DMA_SA 0x90 : #define MSDC_DMA_CTRL 0x98 : #define MSDC_DMA_CFG 0x9c : #define MSDC_PATCH_BIT 0xb0 : #define MSDC_PATCH_BIT1 0xb4 : #define MSDC_PATCH_BIT2 0xb8 : #define MSDC_PAD_TUNE 0xec : #define MSDC_PAD_TUNE0 0xf0 : #define PAD_DS_TUNE 0x188 : #define PAD_CMD_TUNE 0x18c : #define EMMC51_CFG0 0x204 : #define EMMC50_CFG0 0x208 : #define EMMC50_CFG1 0x20c : #define EMMC50_CFG3 0x220 : #define SDC_FIFO_CFG 0x228 : > Will you consider changing this to a struct? […] If we do that, we need to reserve some memory. I think the current way is better. https://review.coreboot.org/c/coreboot/+/51966/comment/66d0a29b_ce5da832 PS5, Line 84: #define MSDC_FIFOCS_CLR (0x1 << 31) /* RW */ > The `MSDC_FIFOCS_TXCNT` mask already contains bit 31 (`MSDC_FIFOCS_CLR`), is this intentional? MSDC_FIFOCS_TXCNT is from bit16 to bit23, not contains bit31. File src/soc/mediatek/common/msdc.c: https://review.coreboot.org/c/coreboot/+/51966/comment/3c55c897_aa513921 PS5, Line 72: static void msdc_reset_hw(struct msdc_ctrlr *host) > nit: should this function return an error if reset and FIFO clear times out? Because we don't care the result, so don't need return an error. -- To view, visit https://review.coreboot.org/c/coreboot/+/51966 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I54a7749ed167c00cd631a76af7c67c654c7bc725 Gerrit-Change-Number: 51966 Gerrit-PatchSet: 11 Gerrit-Owner: Wenbin Mei <wenbin.mei(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Xi Chen <xixi.chen(a)mediatek.com> Gerrit-Reviewer: Yidi Lin <yidi.lin(a)mediatek.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Wenbin Mei <wenbin.mei(a)mediatek.corp-partner.google.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Thu, 08 Apr 2021 04:26:30 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Hung-Te Lin <hungte(a)chromium.org> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Comment-In-Reply-To: Yu-Ping Wu <yupingso(a)google.com> Gerrit-MessageType: comment

1 0

Change in coreboot[master]: mb/google/mancomb: Add Codec configration
by EricR Lai (Code Review) 07 Apr '21

07 Apr '21

EricR Lai has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/52179 ) Change subject: mb/google/mancomb: Add Codec configration ...................................................................... mb/google/mancomb: Add Codec configration Enable I2C2 in devicetree and fill ACPI information for Codec. BUG=b:182211161 TEST=builds Signed-off-by: Eric Lai <ericr_lai(a)compal.corp-partner.google.com> Change-Id: Ib75ef99cbca8b2f38268705704e7616b456f19d9 --- M src/mainboard/google/mancomb/variants/mancomb/overridetree.cb 1 file changed, 14 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/79/52179/1 diff --git a/src/mainboard/google/mancomb/variants/mancomb/overridetree.cb b/src/mainboard/google/mancomb/variants/mancomb/overridetree.cb index 59fe790..891b4eb 100644 --- a/src/mainboard/google/mancomb/variants/mancomb/overridetree.cb +++ b/src/mainboard/google/mancomb/variants/mancomb/overridetree.cb @@ -22,4 +22,18 @@ .early_init = true, }" + device ref i2c_2 on + chip drivers/i2c/generic + register "hid" = ""10EC5682"" + register "name" = ""RT58"" + register "desc" = ""Realtek RT5682"" + register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPIO_90)" + register "property_count" = "1" + register "property_list[0].type" = "ACPI_DP_TYPE_INTEGER" + register "property_list[0].name" = ""realtek,jd-src"" + register "property_list[0].integer" = "1" + device i2c 1a on end + end + end # I2C2 + end # chip soc/amd/cezanne -- To view, visit https://review.coreboot.org/c/coreboot/+/52179 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib75ef99cbca8b2f38268705704e7616b456f19d9 Gerrit-Change-Number: 52179 Gerrit-PatchSet: 1 Gerrit-Owner: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-MessageType: newchange

1 0

Change in coreboot[master]: mb/google/mancomb: Add Bluetooth configuration
by EricR Lai (Code Review) 07 Apr '21

07 Apr '21

EricR Lai has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/52178 ) Change subject: mb/google/mancomb: Add Bluetooth configuration ...................................................................... mb/google/mancomb: Add Bluetooth configuration Configure the BT disable GPIO to logic low in order to enable Bluetooth. BUG=b:182211161 TEST=builds Signed-off-by: Eric Lai <ericr_lai(a)compal.corp-partner.google.com> Change-Id: I7661dea682cbe0ae5e169d87e794ed6ed3c83b5e --- M src/mainboard/google/mancomb/variants/baseboard/gpio.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/78/52178/1 diff --git a/src/mainboard/google/mancomb/variants/baseboard/gpio.c b/src/mainboard/google/mancomb/variants/baseboard/gpio.c index b968cdb..b3d5380 100644 --- a/src/mainboard/google/mancomb/variants/baseboard/gpio.c +++ b/src/mainboard/google/mancomb/variants/baseboard/gpio.c @@ -142,7 +142,7 @@ /* CLK_REQ3_L */ PAD_NF(GPIO_131, CLK_REQ3_L, PULL_NONE), /* BT_DISABLE */ - PAD_GPO(GPIO_132, HIGH), + PAD_GPO(GPIO_132, LOW), /* EGPIO140 */ PAD_NC(GPIO_140), /* UART0_RXD */ -- To view, visit https://review.coreboot.org/c/coreboot/+/52178 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7661dea682cbe0ae5e169d87e794ed6ed3c83b5e Gerrit-Change-Number: 52178 Gerrit-PatchSet: 1 Gerrit-Owner: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-MessageType: newchange

1 0

Change in coreboot[master]: soc/mediatek: add new driver 'msdc' for eMMC
by Hung-Te Lin (Code Review) 07 Apr '21

07 Apr '21

Attention is currently required from: Wenbin Mei. Hung-Te Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/51966 ) Change subject: soc/mediatek: add new driver 'msdc' for eMMC ...................................................................... Patch Set 11: (1 comment) File src/soc/mediatek/common/include/soc/msdc.h: https://review.coreboot.org/c/coreboot/+/51966/comment/950dd5c0_f20afed3 PS5, Line 18: #define MSDC_CFG 0x0 : #define MSDC_IOCON 0x04 : #define MSDC_PS 0x08 : #define MSDC_INT 0x0c : #define MSDC_INTEN 0x10 : #define MSDC_FIFOCS 0x14 : #define MSDC_TXDATA 0x18 : #define MSDC_RXDATA 0x1c : #define SDC_CFG 0x30 : #define SDC_CMD 0x34 : #define SDC_ARG 0x38 : #define SDC_STS 0x3c : #define SDC_RESP0 0x40 : #define SDC_RESP1 0x44 : #define SDC_RESP2 0x48 : #define SDC_RESP3 0x4c : #define SDC_BLK_NUM 0x50 : #define SDC_ADV_CFG0 0x64 : #define EMMC_IOCON 0x7c : #define SDC_ACMD_RESP 0x80 : #define DMA_SA_H4BIT 0x8c : #define MSDC_DMA_SA 0x90 : #define MSDC_DMA_CTRL 0x98 : #define MSDC_DMA_CFG 0x9c : #define MSDC_PATCH_BIT 0xb0 : #define MSDC_PATCH_BIT1 0xb4 : #define MSDC_PATCH_BIT2 0xb8 : #define MSDC_PAD_TUNE 0xec : #define MSDC_PAD_TUNE0 0xf0 : #define PAD_DS_TUNE 0x188 : #define PAD_CMD_TUNE 0x18c : #define EMMC51_CFG0 0x204 : #define EMMC50_CFG0 0x208 : #define EMMC50_CFG1 0x20c : #define EMMC50_CFG3 0x220 : #define SDC_FIFO_CFG 0x228 : > Will you consider changing this to a struct? […] Never mind. Ack -- To view, visit https://review.coreboot.org/c/coreboot/+/51966 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I54a7749ed167c00cd631a76af7c67c654c7bc725 Gerrit-Change-Number: 51966 Gerrit-PatchSet: 11 Gerrit-Owner: Wenbin Mei <wenbin.mei(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Xi Chen <xixi.chen(a)mediatek.com> Gerrit-Reviewer: Yidi Lin <yidi.lin(a)mediatek.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Attention: Wenbin Mei <wenbin.mei(a)mediatek.corp-partner.google.com> Gerrit-Comment-Date: Thu, 08 Apr 2021 04:24:36 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Hung-Te Lin <hungte(a)chromium.org> Gerrit-MessageType: comment

1 0

Change in coreboot[master]: mb/intel/adlrvp: Enable HECI1 communication
by Rizwan Qureshi (Code Review) 07 Apr '21

07 Apr '21

Attention is currently required from: Maulik V Vaghela, Sridhar Siricilla, Balaji Manigandan. Rizwan Qureshi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52149 ) Change subject: mb/intel/adlrvp: Enable HECI1 communication ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/52149 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I34ff842481bdfc7933a76555ff0fd70f4fbbb9a7 Gerrit-Change-Number: 52149 Gerrit-PatchSet: 1 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Attention: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Comment-Date: Thu, 08 Apr 2021 04:22:22 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

Change in coreboot[master]: soc/mediatek: add new driver 'msdc' for eMMC
by Wenbin Mei (Code Review) 07 Apr '21

07 Apr '21

Attention is currently required from: Wenbin Mei. Hello Hung-Te Lin, Xi Chen, build bot (Jenkins), Patrick Georgi, Martin Roth, Angel Pons, Yu-Ping Wu, Yidi Lin, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/51966 to look at the new patch set (#11). Change subject: soc/mediatek: add new driver 'msdc' for eMMC ...................................................................... soc/mediatek: add new driver 'msdc' for eMMC Add MTK host mmc driver support. MTK host controller supports eMMC5.1 spec. BUG=b:177389446 TEST=emerge-asurada coreboot BRANCH=asurada Signed-off-by: Wenbin Mei <wenbin.mei(a)mediatek.com> Change-Id: I54a7749ed167c00cd631a76af7c67c654c7bc725 --- M src/commonlib/include/commonlib/sd_mmc_ctrlr.h A src/soc/mediatek/common/include/soc/msdc.h A src/soc/mediatek/common/msdc.c 3 files changed, 665 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/66/51966/11 -- To view, visit https://review.coreboot.org/c/coreboot/+/51966 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I54a7749ed167c00cd631a76af7c67c654c7bc725 Gerrit-Change-Number: 51966 Gerrit-PatchSet: 11 Gerrit-Owner: Wenbin Mei <wenbin.mei(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Xi Chen <xixi.chen(a)mediatek.com> Gerrit-Reviewer: Yidi Lin <yidi.lin(a)mediatek.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Attention: Wenbin Mei <wenbin.mei(a)mediatek.corp-partner.google.com> Gerrit-MessageType: newpatchset

1 0

Change in coreboot[master]: mb/google/mancomb: Update GPIO configuration
by EricR Lai (Code Review) 07 Apr '21

07 Apr '21

EricR Lai has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/52177 ) Change subject: mb/google/mancomb: Update GPIO configuration ...................................................................... mb/google/mancomb: Update GPIO configuration BUG=b:182211161 TEST=builds Signed-off-by: Eric Lai <ericr_lai(a)compal.corp-partner.google.com> Change-Id: Ie3917c10ecf37c914dbadce5949b8f4f772abd5c --- M src/mainboard/google/mancomb/variants/baseboard/gpio.c 1 file changed, 11 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/77/52177/1 diff --git a/src/mainboard/google/mancomb/variants/baseboard/gpio.c b/src/mainboard/google/mancomb/variants/baseboard/gpio.c index 49752f1..b968cdb 100644 --- a/src/mainboard/google/mancomb/variants/baseboard/gpio.c +++ b/src/mainboard/google/mancomb/variants/baseboard/gpio.c @@ -53,8 +53,8 @@ /* HUB_RST_L */ PAD_GPO(GPIO_24, LOW), /* GPIO_25: Not available */ - /* PCIE_RST0_L */ - PAD_NF(GPIO_26, PCIE_RST_L, PULL_NONE), + /* TODO: change back to PCIE_RST_L when we figure out why PCIE_RST doesn't go high. */ + PAD_GPO(GPIO_26, HIGH), /* PCIE_RST1_L */ PAD_NF(GPIO_27, PCIE_RST1_L, PULL_NONE), /* GPIO_28: Not available */ @@ -93,7 +93,7 @@ PAD_GPI(GPIO_84, PULL_NONE), /* AGPIO85 */ PAD_NC(GPIO_85), - /* SPI_CLK2 */ + /* ESPI_SOC_CLK */ PAD_NF(GPIO_86, SPI_CLK, PULL_NONE), /* AGPIO87 */ PAD_NC(GPIO_87), @@ -116,6 +116,8 @@ PAD_NF(GPIO_106, EMMC_SPI2_WP_L_ESPI2_D2, PULL_NONE), /* ESPI1_DATA3 */ PAD_NF(GPIO_107, SPI2_HOLD_L_ESPI2_D3, PULL_NONE), + /* ESPI_ALERT_L */ + PAD_NF(GPIO_108, ESPI_ALERT_D1, PULL_NONE), /* EGPIO109 */ PAD_NC(GPIO_109), /* GPIO_110 - GPIO_112: Not available */ @@ -169,6 +171,12 @@ PAD_NF(GPIO_19, I2C3_SCL, PULL_NONE), /* I2C3_SDA */ PAD_NF(GPIO_20, I2C3_SDA, PULL_NONE), + /* PCIE_RST0_L */ + PAD_GPO(GPIO_26, HIGH), + /* ESPI_CS_L */ + PAD_NF(GPIO_30, ESPI_CS_L, PULL_NONE), + /* ESPI_SOC_CLK */ + PAD_NF(GPIO_86, SPI_CLK, PULL_NONE), /* ESPI1_DATA0 */ PAD_NF(GPIO_104, SPI2_DO_ESPI2_D0, PULL_NONE), /* ESPI1_DATA1 */ -- To view, visit https://review.coreboot.org/c/coreboot/+/52177 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie3917c10ecf37c914dbadce5949b8f4f772abd5c Gerrit-Change-Number: 52177 Gerrit-PatchSet: 1 Gerrit-Owner: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-MessageType: newchange

1 0

Change in coreboot[master]: mb/google/mancomb: Temporary fix to set eSPI mux
by EricR Lai (Code Review) 07 Apr '21

07 Apr '21

Attention is currently required from: Raul Rangel, Martin Roth, Mathew King. EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52176 ) Change subject: mb/google/mancomb: Temporary fix to set eSPI mux ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: When can we get the proper fix? -- To view, visit https://review.coreboot.org/c/coreboot/+/52176 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ief59bdea392ab3f141ccf7444c608aef99701d2e Gerrit-Change-Number: 52176 Gerrit-PatchSet: 1 Gerrit-Owner: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Mathew King <mathewk(a)chromium.org> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Mathew King <mathewk(a)chromium.org> Gerrit-Comment-Date: Thu, 08 Apr 2021 03:57:16 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Change in coreboot[master]: mb/google/mancomb: Temporary fix to set eSPI mux
by EricR Lai (Code Review) 07 Apr '21

07 Apr '21

EricR Lai has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/52176 ) Change subject: mb/google/mancomb: Temporary fix to set eSPI mux ...................................................................... mb/google/mancomb: Temporary fix to set eSPI mux BUG=b:182211161 TEST=builds Signed-off-by: Eric Lai <ericr_lai(a)compal.corp-partner.google.com> Change-Id: Ief59bdea392ab3f141ccf7444c608aef99701d2e --- M src/mainboard/google/mancomb/bootblock.c 1 file changed, 22 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/76/52176/1 diff --git a/src/mainboard/google/mancomb/bootblock.c b/src/mainboard/google/mancomb/bootblock.c index 11391ef..dd38c34 100644 --- a/src/mainboard/google/mancomb/bootblock.c +++ b/src/mainboard/google/mancomb/bootblock.c @@ -1,15 +1,37 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include <amdblocks/acpimmio.h> #include <bootblock_common.h> #include <baseboard/variants.h> +#include <console/console.h> +#include <device/pci_ops.h> +#include <soc/pci_devs.h> void bootblock_mainboard_early_init(void) { size_t num_gpios; + uint32_t dword; const struct soc_amd_gpio *gpios; if (!CONFIG(VBOOT_STARTS_BEFORE_BOOTBLOCK)) { gpios = variant_early_gpio_table(&num_gpios); program_gpios(gpios, num_gpios); } + + printk(BIOS_DEBUG, "Bootblock configure eSPI\n"); + + dword = pci_read_config32(SOC_LPC_DEV, 0x78); + dword &= 0xFFFFF9F3; + dword |= 0x200; + pci_write_config32(SOC_LPC_DEV, 0x78, dword); + pci_write_config32(SOC_LPC_DEV, 0x44, 0); + pci_write_config32(SOC_LPC_DEV, 0x48, 0); + + dword = pm_read32(0x90); + dword |= 1 << 16; + pm_write32(0x90, dword); + + dword = pm_read32(0x74); + dword |= 3 << 10; + pm_write32(0x74, dword); } -- To view, visit https://review.coreboot.org/c/coreboot/+/52176 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ief59bdea392ab3f141ccf7444c608aef99701d2e Gerrit-Change-Number: 52176 Gerrit-PatchSet: 1 Gerrit-Owner: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-MessageType: newchange

1 0

Change in coreboot[master]: mb/google/dedede/var/metaknight: Add support to handle pen detection
by Karthik Ramasubramanian (Code Review) 07 Apr '21

07 Apr '21

Karthik Ramasubramanian has submitted this change. ( https://review.coreboot.org/c/coreboot/+/51709 ) Change subject: mb/google/dedede/var/metaknight: Add support to handle pen detection ...................................................................... mb/google/dedede/var/metaknight: Add support to handle pen detection Update devicetree and gpio setting of metaknight to handle pen detection. BUG=b:180426949 TEST=Build and check behavior is expected. Signed-off-by: David Wu <david_wu(a)quanta.corp-partner.google.com> Change-Id: Ieeca20eff57b16217a13d996dca3f662911f3e5a Reviewed-on: https://review.coreboot.org/c/coreboot/+/51709 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub(a)google.com> --- M src/mainboard/google/dedede/variants/metaknight/gpio.c M src/mainboard/google/dedede/variants/metaknight/overridetree.cb 2 files changed, 14 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified David Wu: Looks good to me, but someone else must approve Karthik Ramasubramanian: Looks good to me, approved diff --git a/src/mainboard/google/dedede/variants/metaknight/gpio.c b/src/mainboard/google/dedede/variants/metaknight/gpio.c index d6a7fd5..2645e26 100644 --- a/src/mainboard/google/dedede/variants/metaknight/gpio.c +++ b/src/mainboard/google/dedede/variants/metaknight/gpio.c @@ -10,6 +10,9 @@ /* A10 : WWAN_EN => LTE_PWR_OFF_ODL */ PAD_CFG_GPO(GPP_A10, 1, PWROK), + /* C12 : AP_PEN_DET_ODL */ + PAD_CFG_GPI_GPIO_DRIVER(GPP_C12, NONE, DEEP), + /* H17 : WWAN_RST_L => LTE_RESET_R_ODL */ PAD_CFG_GPO(GPP_H17, 0, PLTRST), }; diff --git a/src/mainboard/google/dedede/variants/metaknight/overridetree.cb b/src/mainboard/google/dedede/variants/metaknight/overridetree.cb index 322f72c..a92d969 100644 --- a/src/mainboard/google/dedede/variants/metaknight/overridetree.cb +++ b/src/mainboard/google/dedede/variants/metaknight/overridetree.cb @@ -116,6 +116,17 @@ end end # I2C 0 device pci 15.2 on + chip drivers/generic/gpio_keys + register "name" = ""PENH"" + register "gpio" = "ACPI_GPIO_INPUT_ACTIVE_LOW(GPP_C12)" + register "key.wakeup_route" = "WAKEUP_ROUTE_GPIO_IRQ" + register "key.wakeup_event_action" = "EV_ACT_DEASSERTED" + register "key.dev_name" = ""EJCT"" + register "key.linux_code" = "SW_PEN_INSERTED" + register "key.linux_input_type" = "EV_SW" + register "key.label" = ""pen_eject"" + device generic 0 on end + end chip drivers/i2c/hid register "generic.hid" = ""GDIX0000"" register "generic.desc" = ""Goodix Touchscreen"" -- To view, visit https://review.coreboot.org/c/coreboot/+/51709 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ieeca20eff57b16217a13d996dca3f662911f3e5a Gerrit-Change-Number: 51709 Gerrit-PatchSet: 4 Gerrit-Owner: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Reviewer: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Evan Green <evgreen(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Henry Sun <henrysun(a)google.com> Gerrit-Reviewer: Justin TerAvest <teravest(a)chromium.org> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: merged

1 0

Jump to page:

2025

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit April 2021