coreboot-gerrit April 2021

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Change in coreboot[master]: mb/ocp/deltalake: Add VPD option to force memory training
by Tim Chu (Code Review) 08 Apr '21

08 Apr '21

Attention is currently required from: Anjaneya "Reddy" Chagam, Jonathan Zhang, Johnny Lin, Morgan Jang. Tim Chu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/51972 ) Change subject: mb/ocp/deltalake: Add VPD option to force memory training ...................................................................... Patch Set 2: (1 comment) File src/mainboard/ocp/deltalake/romstage.c: https://review.coreboot.org/c/coreboot/+/51972/comment/b40e2f40_158510a5 PS1, Line 157: if > Please print message when force memory training is enabled. Done -- To view, visit https://review.coreboot.org/c/coreboot/+/51972 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I53a923b51b36f9f5db491ef142109f58f9a4611d Gerrit-Change-Number: 51972 Gerrit-PatchSet: 2 Gerrit-Owner: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: Anjaneya "Reddy" Chagam <anjaneya.chagam(a)intel.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Morgan Jang <Morgan_Jang(a)wiwynn.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Anjaneya "Reddy" Chagam <anjaneya.chagam(a)intel.com> Gerrit-Attention: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Morgan Jang <Morgan_Jang(a)wiwynn.com> Gerrit-Comment-Date: Thu, 08 Apr 2021 06:00:59 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/ocp/deltalake: Add VPD option to force memory training
by Tim Chu (Code Review) 07 Apr '21

07 Apr '21

Attention is currently required from: Anjaneya "Reddy" Chagam, Jonathan Zhang, Morgan Jang, Tim Chu. Hello build bot (Jenkins), Anjaneya "Reddy" Chagam, Jonathan Zhang, Johnny Lin, Morgan Jang, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/51972 to look at the new patch set (#2). Change subject: mb/ocp/deltalake: Add VPD option to force memory training ...................................................................... mb/ocp/deltalake: Add VPD option to force memory training Add function to force memory training and add VPD variable to operate this function. Tested=On OCP Delta Lake, memory training can be forced via VPD. Signed-off-by: Tim Chu <Tim.Chu(a)quantatw.com> Change-Id: I53a923b51b36f9f5db491ef142109f58f9a4611d --- M src/mainboard/ocp/deltalake/romstage.c M src/mainboard/ocp/deltalake/vpd.h 2 files changed, 13 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/72/51972/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/51972 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I53a923b51b36f9f5db491ef142109f58f9a4611d Gerrit-Change-Number: 51972 Gerrit-PatchSet: 2 Gerrit-Owner: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: Anjaneya "Reddy" Chagam <anjaneya.chagam(a)intel.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Morgan Jang <Morgan_Jang(a)wiwynn.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Anjaneya "Reddy" Chagam <anjaneya.chagam(a)intel.com> Gerrit-Attention: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Attention: Morgan Jang <Morgan_Jang(a)wiwynn.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/google/guybrush/var/guybrush: Add FPMCU configration
by build bot (Jenkins) (Code Review) 07 Apr '21

07 Apr '21

Attention is currently required from: Martin Roth. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52181 ) Change subject: mb/google/guybrush/var/guybrush: Add FPMCU configration ...................................................................... Patch Set 1: (4 comments) File src/mainboard/google/guybrush/mainboard.c: https://review.coreboot.org/c/coreboot/+/52181/comment/dc2787e7_0377b7d8 PS1, Line 121: /* Default weak implementation */ code indent should use tabs where possible File src/mainboard/google/guybrush/variants/guybrush/variant.c: https://review.coreboot.org/c/coreboot/+/52181/comment/60d9519e_e5052f8c PS1, Line 14: gpio_set(GPIO_32, 1); please, no spaces at the start of a line https://review.coreboot.org/c/coreboot/+/52181/comment/03edf64b_5cb22cef PS1, Line 15: mdelay(3); please, no spaces at the start of a line https://review.coreboot.org/c/coreboot/+/52181/comment/4a174074_fdf2d9a4 PS1, Line 16: gpio_set(GPIO_11, 1); please, no spaces at the start of a line -- To view, visit https://review.coreboot.org/c/coreboot/+/52181 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7c56b0db193be6804d07c2f333445c2a1dbf9f59 Gerrit-Change-Number: 52181 Gerrit-PatchSet: 1 Gerrit-Owner: Ivy Jian <ivy_jian(a)compal.corp-partner.google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Comment-Date: Thu, 08 Apr 2021 05:45:14 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/guybrush/var/guybrush: Add FPMCU configration
by Ivy Jian (Code Review) 07 Apr '21

07 Apr '21

Ivy Jian has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/52181 ) Change subject: mb/google/guybrush/var/guybrush: Add FPMCU configration ...................................................................... mb/google/guybrush/var/guybrush: Add FPMCU configration Enable CRFP in devicetree. Update gpios for FPMCU power ready. BUG=b:182201937 BRANCH=None TEST=Boot into OS then FPMCU is responding. Signed-off-by: Ivy Jian <ivy_jian(a)compal.corp-partner.google.com> Change-Id: I7c56b0db193be6804d07c2f333445c2a1dbf9f59 --- M src/mainboard/google/guybrush/Kconfig M src/mainboard/google/guybrush/mainboard.c M src/mainboard/google/guybrush/variants/baseboard/include/baseboard/variants.h M src/mainboard/google/guybrush/variants/guybrush/Makefile.inc M src/mainboard/google/guybrush/variants/guybrush/overridetree.cb A src/mainboard/google/guybrush/variants/guybrush/variant.c 6 files changed, 42 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/81/52181/1 diff --git a/src/mainboard/google/guybrush/Kconfig b/src/mainboard/google/guybrush/Kconfig index 9f43d5e..84b6a1d 100644 --- a/src/mainboard/google/guybrush/Kconfig +++ b/src/mainboard/google/guybrush/Kconfig @@ -28,6 +28,7 @@ select MAINBOARD_HAS_TPM2 select SOC_AMD_CEZANNE select SOC_AMD_COMMON_BLOCK_USE_ESPI + select DRIVERS_UART_ACPI config CHROMEOS select EC_GOOGLE_CHROMEEC_SWITCHES diff --git a/src/mainboard/google/guybrush/mainboard.c b/src/mainboard/google/guybrush/mainboard.c index 57f658c..f26784a 100644 --- a/src/mainboard/google/guybrush/mainboard.c +++ b/src/mainboard/google/guybrush/mainboard.c @@ -102,6 +102,7 @@ { mainboard_configure_gpios(); mainboard_ec_init(); + variant_fpmcu_init(); } static void mainboard_enable(struct device *dev) @@ -115,6 +116,11 @@ pirq_setup(); } +void __weak variant_fpmcu_init(void) +{ + /* Default weak implementation */ +} + struct chip_operations mainboard_ops = { .init = mainboard_init, .enable_dev = mainboard_enable, diff --git a/src/mainboard/google/guybrush/variants/baseboard/include/baseboard/variants.h b/src/mainboard/google/guybrush/variants/baseboard/include/baseboard/variants.h index dccaed0..afac157 100644 --- a/src/mainboard/google/guybrush/variants/baseboard/include/baseboard/variants.h +++ b/src/mainboard/google/guybrush/variants/baseboard/include/baseboard/variants.h @@ -24,4 +24,7 @@ /* This function provides GPIO settings before entering sleep. */ const struct soc_amd_gpio *variant_sleep_gpio_table(size_t *size); +/* FPCMU power init*/ +void variant_fpmcu_init(void); + #endif /* __BASEBOARD_VARIANTS_H__ */ diff --git a/src/mainboard/google/guybrush/variants/guybrush/Makefile.inc b/src/mainboard/google/guybrush/variants/guybrush/Makefile.inc index 88e75bd..82fe6f5 100644 --- a/src/mainboard/google/guybrush/variants/guybrush/Makefile.inc +++ b/src/mainboard/google/guybrush/variants/guybrush/Makefile.inc @@ -1,3 +1,5 @@ # SPDX-License-Identifier: GPL-2.0-or-later subdirs-y += ./memory +ramstage-y += variant.c + diff --git a/src/mainboard/google/guybrush/variants/guybrush/overridetree.cb b/src/mainboard/google/guybrush/variants/guybrush/overridetree.cb index 707a63f..dc1f211 100644 --- a/src/mainboard/google/guybrush/variants/guybrush/overridetree.cb +++ b/src/mainboard/google/guybrush/variants/guybrush/overridetree.cb @@ -98,4 +98,17 @@ end end # I2C2 + device mmio 0xfedca000 on + chip drivers/uart/acpi + register "name" = ""CRFP"" + register "desc" = ""Fingerprint Reader"" + register "hid" = "ACPI_DT_NAMESPACE_HID" + register "compat_string" = ""google,cros-ec-uart"" + register "irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPIO_21)" + register "wake" = "GEVENT_5" + register "uart" = "ACPI_UART_RAW_DEVICE(3000000, 64)" + device generic 0 on end + end + end + end # chip soc/amd/cezanne diff --git a/src/mainboard/google/guybrush/variants/guybrush/variant.c b/src/mainboard/google/guybrush/variants/guybrush/variant.c new file mode 100644 index 0000000..eacf550 --- /dev/null +++ b/src/mainboard/google/guybrush/variants/guybrush/variant.c @@ -0,0 +1,17 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <delay.h> +#include <gpio.h> +#include <baseboard/variants.h> +#include <soc/gpio.h> + +void variant_fpmcu_init(void) +{ + /* + * Enable the FPMCU by enabling EN_PWR_FP, then bringing it out + * of reset by setting FPMCU_RST_L high 3ms later. + */ + gpio_set(GPIO_32, 1); + mdelay(3); + gpio_set(GPIO_11, 1); +} -- To view, visit https://review.coreboot.org/c/coreboot/+/52181 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7c56b0db193be6804d07c2f333445c2a1dbf9f59 Gerrit-Change-Number: 52181 Gerrit-PatchSet: 1 Gerrit-Owner: Ivy Jian <ivy_jian(a)compal.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/intel/shadowmountain: Enable TCSS
by Deepti Deshatty (Code Review) 07 Apr '21

07 Apr '21

Attention is currently required from: Maulik V Vaghela, Rizwan Qureshi, Sridhar Siricilla, Subrata Banik. Deepti Deshatty has removed Sowmya V from this change. ( https://review.coreboot.org/c/coreboot/+/52130 ) Change subject: mb/intel/shadowmountain: Enable TCSS ...................................................................... Removed reviewer Sowmya V. -- To view, visit https://review.coreboot.org/c/coreboot/+/52130 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I816ca1b92ae17afdce8ed087366bb2d7ede6a30e Gerrit-Change-Number: 52130 Gerrit-PatchSet: 2 Gerrit-Owner: Deepti Deshatty <deepti.deshatty(a)intel.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Attention: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-MessageType: deleteReviewer

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Change in coreboot[master]: soc/mediatek: add new driver 'msdc' for eMMC
by Yu-Ping Wu (Code Review) 07 Apr '21

07 Apr '21

Attention is currently required from: Angel Pons, Wenbin Mei. Yu-Ping Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/51966 ) Change subject: soc/mediatek: add new driver 'msdc' for eMMC ...................................................................... Patch Set 11: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/51966 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I54a7749ed167c00cd631a76af7c67c654c7bc725 Gerrit-Change-Number: 51966 Gerrit-PatchSet: 11 Gerrit-Owner: Wenbin Mei <wenbin.mei(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Xi Chen <xixi.chen(a)mediatek.com> Gerrit-Reviewer: Yidi Lin <yidi.lin(a)mediatek.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Wenbin Mei <wenbin.mei(a)mediatek.corp-partner.google.com> Gerrit-Comment-Date: Thu, 08 Apr 2021 05:43:57 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/mancomb: add DXIO and DDI descriptors
by EricR Lai (Code Review) 07 Apr '21

07 Apr '21

EricR Lai has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/52180 ) Change subject: mb/google/mancomb: add DXIO and DDI descriptors ...................................................................... mb/google/mancomb: add DXIO and DDI descriptors Sync from guybrush. BUG=b:182211161 TEST=builds Signed-off-by: Eric Lai <ericr_lai(a)compal.corp-partner.google.com> Change-Id: Ica4e6511a5106a958567565b96d5888b8c829ff2 --- M src/mainboard/google/mancomb/port_descriptors.c 1 file changed, 96 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/80/52180/1 diff --git a/src/mainboard/google/mancomb/port_descriptors.c b/src/mainboard/google/mancomb/port_descriptors.c index 8a761fe..916c05d 100644 --- a/src/mainboard/google/mancomb/port_descriptors.c +++ b/src/mainboard/google/mancomb/port_descriptors.c @@ -4,9 +4,105 @@ #include <types.h> static const fsp_dxio_descriptor mancomb_czn_dxio_descriptors[] = { + { /* WLAN */ + .engine_type = PCIE_ENGINE, + .port_present = true, + .start_logical_lane = 0, + .end_logical_lane = 0, + .device_number = 2, + .function_number = 1, + .turn_off_unused_lanes = true, + .clk_req = CLK_REQ0, + .gpio_group_id = GPIO_29, + .port_params = {PP_PSPP_AC, 0x133, PP_PSPP_DC, 0x122} + }, + { /* SD */ + .engine_type = PCIE_ENGINE, + .port_present = true, + .start_logical_lane = 1, + .end_logical_lane = 1, + .device_number = 2, + .function_number = 2, + .turn_off_unused_lanes = true, + .clk_req = CLK_REQ1, + .gpio_group_id = GPIO_70, + .port_params = {PP_PSPP_AC, 0x133, PP_PSPP_DC, 0x122} + }, + { /* LAN */ + .engine_type = PCIE_ENGINE, + .port_present = true, + .start_logical_lane = 2, + .end_logical_lane = 2, + .device_number = 2, + .function_number = 3, + .turn_off_unused_lanes = true, + .clk_req = CLK_REQ2, + .gpio_group_id = GPIO_18, + .port_params = {PP_PSPP_AC, 0x133, PP_PSPP_DC, 0x122} + }, + { /* NVME */ + .engine_type = PCIE_ENGINE, + .port_present = true, + .start_logical_lane = 4, + .end_logical_lane = 7, + .device_number = 2, + .function_number = 4, + .turn_off_unused_lanes = true, + .clk_req = CLK_REQ3, + .gpio_group_id = GPIO_40, + .port_params = {PP_PSPP_AC, 0x133, PP_PSPP_DC, 0x122} + }, + { /* TODO: remove this temporay workaround */ + .engine_type = PCIE_ENGINE, + .port_present = true, + .start_logical_lane = 8, + .end_logical_lane = 11, + .device_number = 2, + .function_number = 5, + .turn_off_unused_lanes = true, + .clk_req = CLK_REQ5, + .port_params = {PP_PSPP_AC, 0x133, PP_PSPP_DC, 0x122} + }, + { /* TODO: remove this temporay workaround */ + .engine_type = PCIE_ENGINE, + .port_present = true, + .start_logical_lane = 16, + .end_logical_lane = 23, + .device_number = 1, + .function_number = 1, + .turn_off_unused_lanes = true, + .clk_req = CLK_REQ6, + .port_params = {PP_PSPP_AC, 0x133, PP_PSPP_DC, 0x122} + } }; +/* TODO: verify the DDI table, since this is mostly an educated guess right now */ static const fsp_ddi_descriptor mancomb_czn_ddi_descriptors[] = { + { /* DDI0 - eDP */ + .connector_type = DDI_UNUSED_TYPE, + .aux_index = DDI_AUX1, + .hdp_index = DDI_HDP1 + }, + { /* DDI1 - HDMI */ + .connector_type = DDI_HDMI, + .aux_index = DDI_AUX2, + .hdp_index = DDI_HDP2 + }, + { /* DDI2 */ + .connector_type = DDI_UNUSED_TYPE, + .aux_index = DDI_AUX3, + .hdp_index = DDI_HDP3, + }, + { /* DDI3 - DP (type C) */ + .connector_type = DDI_DP, + .aux_index = DDI_AUX3, + .hdp_index = DDI_HDP3, + }, + { /* DDI4 - DP (type C) */ + .connector_type = DDI_DP, + .aux_index = DDI_AUX4, + .hdp_index = DDI_HDP4, + } }; void mainboard_get_dxio_ddi_descriptors( -- To view, visit https://review.coreboot.org/c/coreboot/+/52180 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ica4e6511a5106a958567565b96d5888b8c829ff2 Gerrit-Change-Number: 52180 Gerrit-PatchSet: 1 Gerrit-Owner: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: timestamp: Add helper fucntions
by Furquan Shaikh (Code Review) 07 Apr '21

07 Apr '21

Attention is currently required from: Subrata Banik, Julius Werner, Angel Pons, Aaron Durbin. Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/51445 ) Change subject: timestamp: Add helper fucntions ...................................................................... Patch Set 3: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/51445/comment/7611e0fd_b817c333 PS3, Line 7: Add helper fucntions > Sure Furquan, let me start with then you can chime in ? Sounds good. I would recommend evaluating Julius' comment about switching to microseconds for x86 as well. It would help keep the API slightly simpler. Let me know if you want to discuss more or need any help. Thanks! -- To view, visit https://review.coreboot.org/c/coreboot/+/51445 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6b7065ed26e231fc898ae44bcc15cba6fb42b308 Gerrit-Change-Number: 51445 Gerrit-PatchSet: 3 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Comment-Date: Thu, 08 Apr 2021 05:35:10 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Furquan Shaikh <furquan(a)google.com> Comment-In-Reply-To: Subrata Banik <subrata.banik(a)intel.com> Comment-In-Reply-To: Julius Werner <jwerner(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: timestamp: Add helper fucntions
by Subrata Banik (Code Review) 07 Apr '21

07 Apr '21

Attention is currently required from: Furquan Shaikh, Julius Werner, Angel Pons, Aaron Durbin. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/51445 ) Change subject: timestamp: Add helper fucntions ...................................................................... Patch Set 3: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/51445/comment/9dcd40fc_c70a61d0 PS3, Line 7: Add helper fucntions > Okay, let's go with that. […] Sure Furquan, let me start with then you can chime in ? -- To view, visit https://review.coreboot.org/c/coreboot/+/51445 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6b7065ed26e231fc898ae44bcc15cba6fb42b308 Gerrit-Change-Number: 51445 Gerrit-PatchSet: 3 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Comment-Date: Thu, 08 Apr 2021 05:32:02 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Furquan Shaikh <furquan(a)google.com> Comment-In-Reply-To: Julius Werner <jwerner(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/mediatek: add new driver 'msdc' for eMMC
by Hung-Te Lin (Code Review) 07 Apr '21

07 Apr '21

Attention is currently required from: Angel Pons, Wenbin Mei, Yu-Ping Wu. Hung-Te Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/51966 ) Change subject: soc/mediatek: add new driver 'msdc' for eMMC ...................................................................... Patch Set 11: Code-Review+2 (1 comment) File src/soc/mediatek/common/include/soc/msdc.h: https://review.coreboot.org/c/coreboot/+/51966/comment/66c7614d_2a7e2c40 PS5, Line 18: #define MSDC_CFG 0x0 : #define MSDC_IOCON 0x04 : #define MSDC_PS 0x08 : #define MSDC_INT 0x0c : #define MSDC_INTEN 0x10 : #define MSDC_FIFOCS 0x14 : #define MSDC_TXDATA 0x18 : #define MSDC_RXDATA 0x1c : #define SDC_CFG 0x30 : #define SDC_CMD 0x34 : #define SDC_ARG 0x38 : #define SDC_STS 0x3c : #define SDC_RESP0 0x40 : #define SDC_RESP1 0x44 : #define SDC_RESP2 0x48 : #define SDC_RESP3 0x4c : #define SDC_BLK_NUM 0x50 : #define SDC_ADV_CFG0 0x64 : #define EMMC_IOCON 0x7c : #define SDC_ACMD_RESP 0x80 : #define DMA_SA_H4BIT 0x8c : #define MSDC_DMA_SA 0x90 : #define MSDC_DMA_CTRL 0x98 : #define MSDC_DMA_CFG 0x9c : #define MSDC_PATCH_BIT 0xb0 : #define MSDC_PATCH_BIT1 0xb4 : #define MSDC_PATCH_BIT2 0xb8 : #define MSDC_PAD_TUNE 0xec : #define MSDC_PAD_TUNE0 0xf0 : #define PAD_DS_TUNE 0x188 : #define PAD_CMD_TUNE 0x18c : #define EMMC51_CFG0 0x204 : #define EMMC50_CFG0 0x208 : #define EMMC50_CFG1 0x20c : #define EMMC50_CFG3 0x220 : #define SDC_FIFO_CFG 0x228 : > If we do that, we need to reserve some memory. I think the current way is better. No, a "struct *" do not need/allocate extra memory except a pointer (8 bytes). But anyway, feel free to keep your current implementation. -- To view, visit https://review.coreboot.org/c/coreboot/+/51966 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I54a7749ed167c00cd631a76af7c67c654c7bc725 Gerrit-Change-Number: 51966 Gerrit-PatchSet: 11 Gerrit-Owner: Wenbin Mei <wenbin.mei(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Xi Chen <xixi.chen(a)mediatek.com> Gerrit-Reviewer: Yidi Lin <yidi.lin(a)mediatek.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Wenbin Mei <wenbin.mei(a)mediatek.corp-partner.google.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Thu, 08 Apr 2021 04:37:03 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Hung-Te Lin <hungte(a)chromium.org> Comment-In-Reply-To: Wenbin Mei <wenbin.mei(a)mediatek.corp-partner.google.com> Gerrit-MessageType: comment

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coreboot-gerrit April 2021