coreboot-gerrit April 2021

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Change in coreboot[master]: mb/google/dedede/var/drawcia: Add low_power_probe config for camera d...
by Varshit B Pandya (Code Review) 08 Apr '21

08 Apr '21

Varshit B Pandya has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/52190 ) Change subject: mb/google/dedede/var/drawcia: Add low_power_probe config for camera devices ...................................................................... mb/google/dedede/var/drawcia: Add low_power_probe config for camera devices Add low_power_probe config to camera devices so that driver skips initial probe during kernel boot and hence prevents privacy LED blink. BUG=b:178060668 TEST=Build and boot to OS on Drawcia. Ensure no blink on provacy LED. Signed-off-by: Varshit Pandya <varshit.b.pandya(a)intel.com> Change-Id: I00dfe2ce0b57ff3eaa258204f49e79a280754dcf --- M src/mainboard/google/dedede/variants/drawcia/overridetree.cb 1 file changed, 13 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/90/52190/1 diff --git a/src/mainboard/google/dedede/variants/drawcia/overridetree.cb b/src/mainboard/google/dedede/variants/drawcia/overridetree.cb index d727ecc..7a97b86 100644 --- a/src/mainboard/google/dedede/variants/drawcia/overridetree.cb +++ b/src/mainboard/google/dedede/variants/drawcia/overridetree.cb @@ -248,6 +248,8 @@ register "remote_name" = ""IPU0"" register "has_power_resource" = "1" + register "low_power_probe" = "1" + #Controls register "clk_panel.clks[0].clknum" = "1" #IMGCLKOUT_1 register "clk_panel.clks[0].freq" = "1" #19.2 Mhz @@ -280,8 +282,17 @@ register "chip_name" = ""DW AF DAC"" register "device_type" = "INTEL_ACPI_CAMERA_VCM" - register "pr0" = ""\\_SB.PCI0.I2C3.CAM1.PRIC"" + register "has_power_resource" = "1" register "vcm_compat" = ""dongwoon,dw9714"" + register "low_power_probe" = "1" + + register "gpio_panel.gpio[0].gpio_num" = "GPP_D14" #power_enable_1p2 + #_ON + register "on_seq.ops_cnt" = "1" + register "on_seq.ops[0]" = "SEQ_OPS_GPIO_ENABLE(0, 0)" + #_OFF + register "off_seq.ops_cnt" = "1" + register "off_seq.ops[0]" = "SEQ_OPS_GPIO_DISABLE(0, 0)" device i2c 0C on end end @@ -296,6 +307,7 @@ register "nvm_readonly" = "1" register "nvm_width" = "0x08" register "nvm_compat" = ""atmel,24c08"" + register "low_power_probe" = "1" device i2c 50 on end end -- To view, visit https://review.coreboot.org/c/coreboot/+/52190 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I00dfe2ce0b57ff3eaa258204f49e79a280754dcf Gerrit-Change-Number: 52190 Gerrit-PatchSet: 1 Gerrit-Owner: Varshit B Pandya <varshit.b.pandya(a)intel.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: drivers/intel/mipi_camera: Adding support for low power camera probe
by Varshit B Pandya (Code Review) 08 Apr '21

08 Apr '21

Attention is currently required from: Sugnan Prabhu S. Hello Sugnan Prabhu S, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/52189 to review the following change. Change subject: drivers/intel/mipi_camera: Adding support for low power camera probe ...................................................................... drivers/intel/mipi_camera: Adding support for low power camera probe Adding a new configuration low_power_probe to avoid camera privacy LED blink during the boot. Change-Id: I27d5c66fb380ae6cd76d04ee82b7736407dac1b0 Signed-off-by: Pandya, Varshit B <varshit.b.pandya(a)intel.com> Signed-off-by: Sugnan Prabhu S <sugnan.prabhu.s(a)intel.com> --- M src/drivers/intel/mipi_camera/camera.c M src/drivers/intel/mipi_camera/chip.h 2 files changed, 13 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/89/52189/1 diff --git a/src/drivers/intel/mipi_camera/camera.c b/src/drivers/intel/mipi_camera/camera.c index 65eba16..ec79e39 100644 --- a/src/drivers/intel/mipi_camera/camera.c +++ b/src/drivers/intel/mipi_camera/camera.c @@ -433,6 +433,9 @@ acpi_dp_add_array(dsd, lens_focus); } + if (config->low_power_probe) + acpi_dp_add_integer(dsd, "i2c-allow-low-power-probe", 0x01); + acpi_dp_add_child(dsd, "port0", prt0); acpi_dp_write(dsd); @@ -480,6 +483,10 @@ acpi_dp_add_integer(dsd, "address-width", config->nvm_width); acpi_dp_add_string(dsd, "compatible", config->nvm_compat); + + if (config->low_power_probe) + acpi_dp_add_integer(dsd, "i2c-allow-low-power-probe", 0x01); + acpi_dp_write(dsd); } @@ -493,6 +500,10 @@ dsd = acpi_dp_new_table("_DSD"); acpi_dp_add_string(dsd, "compatible", config->vcm_compat); + + if (config->low_power_probe) + acpi_dp_add_integer(dsd, "i2c-allow-low-power-probe", 0x01); + acpi_dp_write(dsd); } diff --git a/src/drivers/intel/mipi_camera/chip.h b/src/drivers/intel/mipi_camera/chip.h index 28f8464..64942b6 100644 --- a/src/drivers/intel/mipi_camera/chip.h +++ b/src/drivers/intel/mipi_camera/chip.h @@ -247,6 +247,8 @@ const char *vcm_compat; /* Does the device have a power resource entries */ bool has_power_resource; + /* Perform low power probe */ + bool low_power_probe; }; #endif -- To view, visit https://review.coreboot.org/c/coreboot/+/52189 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I27d5c66fb380ae6cd76d04ee82b7736407dac1b0 Gerrit-Change-Number: 52189 Gerrit-PatchSet: 1 Gerrit-Owner: Varshit B Pandya <varshit.b.pandya(a)intel.com> Gerrit-Reviewer: Sugnan Prabhu S <sugnan.prabhu.s(a)intel.com> Gerrit-Attention: Sugnan Prabhu S <sugnan.prabhu.s(a)intel.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: util/genbuild_h: add COREBOOT_BUILD_EPOCH seconds since epoch
by Alexander Couzens (Code Review) 08 Apr '21

08 Apr '21

Attention is currently required from: Martin Roth. Alexander Couzens has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/51362 ) Change subject: util/genbuild_h: add COREBOOT_BUILD_EPOCH seconds since epoch ...................................................................... Patch Set 4: (1 comment) Patchset: PS3: > Not _too_ happy about adding an option for that here (which will encourage adding all kinds of other […] Maybe this approach is better. It gets ugly in https://review.coreboot.org/c/coreboot/+/51364 :) -- To view, visit https://review.coreboot.org/c/coreboot/+/51362 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iaa79d3e7df8101a1ba1b37a361d8992f7eab2d52 Gerrit-Change-Number: 51362 Gerrit-PatchSet: 4 Gerrit-Owner: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Comment-Date: Thu, 08 Apr 2021 12:38:35 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/intel/shadowmountain: Enable RTD3 for SD card
by Rizwan Qureshi (Code Review) 08 Apr '21

08 Apr '21

Attention is currently required from: Rizwan Qureshi. Hello build bot (Jenkins), Paul Menzel, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/52134 to look at the new patch set (#2). Change subject: mb/intel/shadowmountain: Enable RTD3 for SD card ...................................................................... mb/intel/shadowmountain: Enable RTD3 for SD card Enable the PCIe RTD3 driver for the PCIe attached SD card interface and specify the srcclk pin and reset GPIO. TEST=Tested on shadowmountain platform to ensure the system can enter the S0i3.2 substate and suspend/resume is stable Signed-off-by: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Change-Id: Ibeb99bea48d72b019cb2adcf38926c3ed39f7b84 --- M src/mainboard/intel/shadowmountain/variants/baseboard/devicetree.cb 1 file changed, 7 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/34/52134/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/52134 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibeb99bea48d72b019cb2adcf38926c3ed39f7b84 Gerrit-Change-Number: 52134 Gerrit-PatchSet: 2 Gerrit-Owner: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/alderlake: Add tcss code
by Deepti Deshatty (Code Review) 08 Apr '21

08 Apr '21

Deepti Deshatty has removed Deepti Deshatty from this change. ( https://review.coreboot.org/c/coreboot/+/52188 ) Change subject: soc/intel/alderlake: Add tcss code ...................................................................... Removed reviewer Deepti Deshatty. -- To view, visit https://review.coreboot.org/c/coreboot/+/52188 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6c11eae5946038363ac1f81cea4d2c4449bb90fd Gerrit-Change-Number: 52188 Gerrit-PatchSet: 2 Gerrit-Owner: Deepti Deshatty <deepti.deshatty(a)intel.com> Gerrit-MessageType: deleteReviewer

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Change in coreboot[master]: mb/facebook/fbg1701/Kconfig: Remove CACHE_MRC_SETTINGS
by Patrick Georgi (Code Review) 08 Apr '21

08 Apr '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/52152 ) Change subject: mb/facebook/fbg1701/Kconfig: Remove CACHE_MRC_SETTINGS ...................................................................... mb/facebook/fbg1701/Kconfig: Remove CACHE_MRC_SETTINGS The CACHE_MRC_SETTINGS option is already selected in SoC Kconfig. BUG = N/A TEST = Build and boot facebook FBG1701 Signed-off-by: Frans Hendriks <fhendriks(a)eltan.com> Change-Id: I1c7fd5ec36726724939660bf506a45a44848f8c4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52152 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/mainboard/facebook/fbg1701/Kconfig 1 file changed, 0 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Angel Pons: Looks good to me, approved diff --git a/src/mainboard/facebook/fbg1701/Kconfig b/src/mainboard/facebook/fbg1701/Kconfig index e01f979..1c47247 100644 --- a/src/mainboard/facebook/fbg1701/Kconfig +++ b/src/mainboard/facebook/fbg1701/Kconfig @@ -16,7 +16,6 @@ select SOC_INTEL_COMMON_BLOCK_HDA_VERB select PCIEXP_L1_SUB_STATE select HAVE_FSP_BIN - select CACHE_MRC_SETTINGS select DISABLE_HPET select INTEL_GMA_HAVE_VBT select HAVE_SPD_IN_CBFS -- To view, visit https://review.coreboot.org/c/coreboot/+/52152 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1c7fd5ec36726724939660bf506a45a44848f8c4 Gerrit-Change-Number: 52152 Gerrit-PatchSet: 3 Gerrit-Owner: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Wim Vervoorn <wvervoorn(a)eltan.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/google/zork/vilboz: Update the ACPI name of ALC1015 AMP
by Patrick Georgi (Code Review) 08 Apr '21

08 Apr '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/52127 ) Change subject: mb/google/zork/vilboz: Update the ACPI name of ALC1015 AMP ...................................................................... mb/google/zork/vilboz: Update the ACPI name of ALC1015 AMP Update the ACPI name from AMDP1015 to 1002105 based on b/177971830#180. AMDI1015 -> AMD platform with RT1015 10021015 -> AMD platform with RT1015p Reference: https://www.spinics.net/lists/alsa-devel/msg124694.html BUG=b:177971830 BRANCH=firmware-zork-13434.B TEST=emerge-zork coreboot chromeos-bootimage, then verify with ALC1015 AMP Signed-off-by: Frank Wu <frank_wu(a)compal.corp-partner.google.com> Change-Id: Id8f378ad6f3328d7db949ecdb609a2f16acd3884 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52127 Reviewed-by: Kangheui Won <khwon(a)chromium.org> Reviewed-by: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/google/zork/variants/vilboz/overridetree.cb 1 file changed, 1 insertion(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified EricR Lai: Looks good to me, approved Kangheui Won: Looks good to me, approved diff --git a/src/mainboard/google/zork/variants/vilboz/overridetree.cb b/src/mainboard/google/zork/variants/vilboz/overridetree.cb index 3f5bfc3..93fe607 100644 --- a/src/mainboard/google/zork/variants/vilboz/overridetree.cb +++ b/src/mainboard/google/zork/variants/vilboz/overridetree.cb @@ -172,7 +172,7 @@ end end chip drivers/amd/i2s_machine_dev - register "hid" = ""AMDP1015"" + register "hid" = ""10021015"" # DMIC select GPIO for ACP machine device # This GPIO is used to select DMIC0 or DMIC1 by the # kernel driver. It does not really have a polarity -- To view, visit https://review.coreboot.org/c/coreboot/+/52127 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id8f378ad6f3328d7db949ecdb609a2f16acd3884 Gerrit-Change-Number: 52127 Gerrit-PatchSet: 4 Gerrit-Owner: Frank Wu <frank_wu(a)compal.corp-partner.google.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Alan Lee <alan_lee(a)compal.corp-partner.google.com> Gerrit-CC: John Su <john_su(a)compal.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/mediatek: dsi: fine tune the delta time for EoTp
by Patrick Georgi (Code Review) 08 Apr '21

08 Apr '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/51432 ) Change subject: soc/mediatek: dsi: fine tune the delta time for EoTp ...................................................................... soc/mediatek: dsi: fine tune the delta time for EoTp We seperate the EoTp packet extra data. So need to reduce the delta. BUG=b:173603645 BRANCH=kukui TEST=Display is normal on Kukui Signed-off-by: Jitao Shi <jitao.shi(a)mediatek.com> Change-Id: I0666068cfb04b78eb706278814163f050da32b9c Reviewed-on: https://review.coreboot.org/c/coreboot/+/51432 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Hung-Te Lin <hungte(a)chromium.org> --- M src/soc/mediatek/common/dsi.c 1 file changed, 1 insertion(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Hung-Te Lin: Looks good to me, approved diff --git a/src/soc/mediatek/common/dsi.c b/src/soc/mediatek/common/dsi.c index 3f35443..5c969db 100644 --- a/src/soc/mediatek/common/dsi.c +++ b/src/soc/mediatek/common/dsi.c @@ -204,7 +204,7 @@ data_phy_cycles = phy_timing->lpx + phy_timing->da_hs_prepare + phy_timing->da_hs_zero + phy_timing->da_hs_exit + 3; - u32 delta = 12; + u32 delta = 10; if (mode_flags & MIPI_DSI_MODE_EOT_PACKET) delta += 2; -- To view, visit https://review.coreboot.org/c/coreboot/+/51432 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0666068cfb04b78eb706278814163f050da32b9c Gerrit-Change-Number: 51432 Gerrit-PatchSet: 6 Gerrit-Owner: jitao shi <jitao.shi(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Chen-Tsung Hsieh <chentsung(a)chromium.org> Gerrit-CC: Chen-Tsung Hsieh <chentsung(a)google.com> Gerrit-CC: Jitao Shi <jitao.shi(a)mediatek.corp-partner.google.com> Gerrit-CC: Shaoming Chen <shaoming.chen(a)mediatek.corp-partner.google.com> Gerrit-MessageType: merged

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Change in coreboot[master]: [TEST] sb/amd/hudson: Make SPI available in all stages
by Nico Huber (Code Review) 08 Apr '21

08 Apr '21

Nico Huber has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/52187 ) Change subject: [TEST] sb/amd/hudson: Make SPI available in all stages ...................................................................... [TEST] sb/amd/hudson: Make SPI available in all stages Change-Id: Ie1ac485923aaa50e8a0024c12755909c0cb83214 Signed-off-by: Nico Huber <nico.huber(a)secunet.com> --- M src/southbridge/amd/agesa/hudson/Makefile.inc M src/southbridge/amd/agesa/hudson/spi.c 2 files changed, 3 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/87/52187/1 diff --git a/src/southbridge/amd/agesa/hudson/Makefile.inc b/src/southbridge/amd/agesa/hudson/Makefile.inc index b8eb5b9..8da883e 100644 --- a/src/southbridge/amd/agesa/hudson/Makefile.inc +++ b/src/southbridge/amd/agesa/hudson/Makefile.inc @@ -24,7 +24,7 @@ ramstage-y += enable_usbdebug.c romstage-y += early_setup.c -ramstage-$(CONFIG_SPI_FLASH) += spi.c +all-$(CONFIG_SPI_FLASH) += spi.c ramstage-y += resume.c ramtop.c romstage-y += ramtop.c diff --git a/src/southbridge/amd/agesa/hudson/spi.c b/src/southbridge/amd/agesa/hudson/spi.c index b2f9ff2..e222ce7 100644 --- a/src/southbridge/amd/agesa/hudson/spi.c +++ b/src/southbridge/amd/agesa/hudson/spi.c @@ -66,10 +66,8 @@ void spi_init(void) { - struct device *dev; - - dev = pcidev_on_root(0x14, 3); - spibar = pci_read_config32(dev, 0xA0) & ~0x1F; + const pci_devfn_t dev = PCI_DEV(0, 0x14, 3); + spibar = pci_s_read_config32(dev, 0xA0) & ~0x1F; } static int spi_ctrlr_xfer(const struct spi_slave *slave, const void *dout, -- To view, visit https://review.coreboot.org/c/coreboot/+/52187 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie1ac485923aaa50e8a0024c12755909c0cb83214 Gerrit-Change-Number: 52187 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/mediatek: dsi: fine tune the delta time for EoTp
by Chen-Tsung Hsieh (Code Review) 08 Apr '21

08 Apr '21

Attention is currently required from: Chen-Tsung Hsieh, jitao shi, Shaoming Chen, Jitao Shi, Yu-Ping Wu. Chen-Tsung Hsieh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/51432 ) Change subject: soc/mediatek: dsi: fine tune the delta time for EoTp ...................................................................... Patch Set 5: (1 comment) File src/soc/mediatek/common/dsi.c: https://review.coreboot.org/c/coreboot/+/51432/comment/62c79846_8146baa1 PS2, Line 207: 10 > Ack According to https://patchwork.kernel.org/project/linux-mediatek/patch/20210201033603.12… > delta = dsi->mode_flags & MIPI_DSI_MODE_VIDEO_BURST ? 18 : 12; > + delta += dsi->mode_flags & MIPI_DSI_MODE_EOT_PACKET ? 2 : 0; If this is what we want, should we update coreboot as follow? ``` u32 delta = 12; if (!(mode_flags & MIPI_DSI_MODE_EOT_PACKET)) delta += 2; if (mode_flags & MIPI_DSI_MODE_VIDEO_BURST) delta += 6; ``` (MIPI_DSI_MODE_EOT_PACKET is a disable bit in kernel, but an enable bit in coreboot.) -- To view, visit https://review.coreboot.org/c/coreboot/+/51432 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0666068cfb04b78eb706278814163f050da32b9c Gerrit-Change-Number: 51432 Gerrit-PatchSet: 5 Gerrit-Owner: jitao shi <jitao.shi(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Chen-Tsung Hsieh <chentsung(a)chromium.org> Gerrit-CC: Chen-Tsung Hsieh <chentsung(a)google.com> Gerrit-CC: Jitao Shi <jitao.shi(a)mediatek.corp-partner.google.com> Gerrit-CC: Shaoming Chen <shaoming.chen(a)mediatek.corp-partner.google.com> Gerrit-Attention: Chen-Tsung Hsieh <chentsung(a)chromium.org> Gerrit-Attention: jitao shi <jitao.shi(a)mediatek.com> Gerrit-Attention: Shaoming Chen <shaoming.chen(a)mediatek.corp-partner.google.com> Gerrit-Attention: Jitao Shi <jitao.shi(a)mediatek.corp-partner.google.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Thu, 08 Apr 2021 10:31:41 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Hung-Te Lin <hungte(a)chromium.org> Comment-In-Reply-To: Chen-Tsung Hsieh <chentsung(a)google.com> Comment-In-Reply-To: Chen-Tsung Hsieh <chentsung(a)chromium.org> Comment-In-Reply-To: Shaoming Chen <shaoming.chen(a)mediatek.corp-partner.google.com> Comment-In-Reply-To: Jitao Shi <jitao.shi(a)mediatek.corp-partner.google.com> Gerrit-MessageType: comment

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coreboot-gerrit April 2021