coreboot-gerrit April 2021

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Change in coreboot[master]: intel/common/block/tcss: Add a weak funtion for mainboard_tcss_get_po...
by Rizwan Qureshi (Code Review) 08 Apr '21

08 Apr '21

Attention is currently required from: Tim Wawrzynczak, Deepti Deshatty, Patrick Rudolph. Rizwan Qureshi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52183 ) Change subject: intel/common/block/tcss: Add a weak funtion for mainboard_tcss_get_port_info() ...................................................................... Patch Set 3: (1 comment) Patchset: PS3: > It was intentional to not leave a weak function in place. […] I don't think this was mentioned in the patch that was used to move stuff to common location. This means the SoC and mainboard changes have to be in the same patch -- To view, visit https://review.coreboot.org/c/coreboot/+/52183 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6ccc799f28d45f5ffd0e9b8179ed973744af8113 Gerrit-Change-Number: 52183 Gerrit-PatchSet: 3 Gerrit-Owner: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Deepti Deshatty <deepti.deshatty(a)intel.corp-partner.google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Deepti Deshatty <deepti.deshatty(a)intel.corp-partner.google.com> Gerrit-Attention: Deepti Deshatty <deepti.deshatty(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Thu, 08 Apr 2021 14:36:48 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: tests: Add lib/dimm_info_util-test test case
by Jakub Czapiga (Code Review) 08 Apr '21

08 Apr '21

Jakub Czapiga has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/52192 ) Change subject: tests: Add lib/dimm_info_util-test test case ...................................................................... tests: Add lib/dimm_info_util-test test case Signed-off-by: Jakub Czapiga <jacz(a)semihalf.com> Change-Id: I536566ba883bbeb558587a8d71e3d86152fb5e14 --- M tests/lib/Makefile.inc A tests/lib/dimm_info_util-test.c 2 files changed, 117 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/92/52192/1 diff --git a/tests/lib/Makefile.inc b/tests/lib/Makefile.inc index cba4361..37e7455 100644 --- a/tests/lib/Makefile.inc +++ b/tests/lib/Makefile.inc @@ -24,6 +24,7 @@ tests-y += compute_ip_checksum-test tests-y += memrange-test tests-y += uuid-test +tests-y += dimm_info_util-test string-test-srcs += tests/lib/string-test.c string-test-srcs += src/lib/string.c @@ -116,3 +117,7 @@ uuid-test-srcs += tests/lib/uuid-test.c uuid-test-srcs += src/lib/hexstrtobin.c uuid-test-srcs += src/lib/uuid.c + +dimm_info_util-test-srcs += tests/lib/dimm_info_util-test.c +dimm_info_util-test-srcs += src/lib/dimm_info_util.c +dimm_info_util-test-srcs += tests/stubs/console.c diff --git a/tests/lib/dimm_info_util-test.c b/tests/lib/dimm_info_util-test.c new file mode 100644 index 0000000..a698fc5 --- /dev/null +++ b/tests/lib/dimm_info_util-test.c @@ -0,0 +1,112 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <dimm_info_util.h> +#include <spd.h> +#include <tests/test.h> + +static void test_smbios_bus_width_to_spd_width(void **state) +{ + /* Non-ECC variants */ + assert_int_equal(MEMORY_BUS_WIDTH_64, smbios_bus_width_to_spd_width(64, 64)); + assert_int_equal(MEMORY_BUS_WIDTH_32, smbios_bus_width_to_spd_width(32, 32)); + assert_int_equal(MEMORY_BUS_WIDTH_16, smbios_bus_width_to_spd_width(16, 16)); + assert_int_equal(MEMORY_BUS_WIDTH_8, smbios_bus_width_to_spd_width(8, 8)); + /* Incorrect data width. Fallback to 8-bit */ + assert_int_equal(MEMORY_BUS_WIDTH_8, smbios_bus_width_to_spd_width(15, 15)); + + /* ECC variants */ + assert_int_equal(MEMORY_BUS_WIDTH_64 | SPD_ECC_8BIT, + smbios_bus_width_to_spd_width(64 + 8, 64)); + assert_int_equal(MEMORY_BUS_WIDTH_32 | SPD_ECC_8BIT, + smbios_bus_width_to_spd_width(32 + 8, 32)); + assert_int_equal(MEMORY_BUS_WIDTH_16 | SPD_ECC_8BIT, + smbios_bus_width_to_spd_width(16 + 8, 16)); + assert_int_equal(MEMORY_BUS_WIDTH_8 | SPD_ECC_8BIT, + smbios_bus_width_to_spd_width(8 + 8, 8)); + /* Incorrect data width. Fallback to 8-bit */ + assert_int_equal(MEMORY_BUS_WIDTH_8 | SPD_ECC_8BIT, + smbios_bus_width_to_spd_width(15 + 8, 15)); +} + +static void test_smbios_memory_size_to_mib(void **state) +{ + uint32_t extended_size; + uint16_t memory_size; + + /* Unknown memory size */ + assert_int_equal(0, smbios_memory_size_to_mib(0xFFFF, 0)); + assert_int_equal(0, smbios_memory_size_to_mib(0xFFFF, 0xFFFF)); + assert_int_equal(0, smbios_memory_size_to_mib(0xFFFF, 87642)); + + /* 32GiB - 1MiB */ + extended_size = 0; + assert_int_equal(extended_size, smbios_memory_size_to_mib(0x7FFF, extended_size)); + extended_size = 0xFFFFFFFF; + assert_int_equal(extended_size, smbios_memory_size_to_mib(0x7FFF, extended_size)); + extended_size = 0xDEDE6666; + assert_int_equal(extended_size, smbios_memory_size_to_mib(0x7FFF, extended_size)); + + /* Memory size in KiB when MSB is flipped */ + memory_size = 0x0 & 0x8000; /* Zero bytes */ + assert_int_equal(0, smbios_memory_size_to_mib(memory_size, 0)); + assert_int_equal(0, smbios_memory_size_to_mib(memory_size, 0xFFFFFFFF)); + assert_int_equal(0, smbios_memory_size_to_mib(memory_size, 2345568)); + memory_size = (31 * KiB) | 0x8000; + assert_int_equal(31, smbios_memory_size_to_mib(memory_size, 0)); + assert_int_equal(31, smbios_memory_size_to_mib(memory_size, 0xFFFFFFFF)); + assert_int_equal(31, smbios_memory_size_to_mib(memory_size, 72594344)); + + /* Value in MiB Only when memory size is not 0xFFFF and 0x7FFF and MSB is not set */ + memory_size = 32766; /* value in MiB */ + assert_int_equal(memory_size, smbios_memory_size_to_mib(memory_size, 0)); + assert_int_equal(memory_size, smbios_memory_size_to_mib(memory_size, 0xFFFFFFFF)); + assert_int_equal(memory_size, smbios_memory_size_to_mib(memory_size, 694735)); +} + +static void test_smbios_form_factor_to_spd_mod_type(void **state) +{ + /* Form factors defined in coreboot */ + const LargestIntegralType udimm_allowed[] = { + SPD_UDIMM, SPD_MICRO_DIMM, SPD_MINI_UDIMM, + }; + assert_in_set(smbios_form_factor_to_spd_mod_type(MEMORY_FORMFACTOR_DIMM), + udimm_allowed, ARRAY_SIZE(udimm_allowed)); + + const LargestIntegralType rdimm_allowed[] = { SPD_RDIMM, SPD_MINI_RDIMM }; + assert_in_set(smbios_form_factor_to_spd_mod_type(MEMORY_FORMFACTOR_RIMM), + rdimm_allowed, ARRAY_SIZE(rdimm_allowed)); + + assert_int_equal(SPD_SODIMM, + smbios_form_factor_to_spd_mod_type(MEMORY_FORMFACTOR_SODIMM)); + + const smbios_memory_form_factor undefined_factors[] = { + MEMORY_FORMFACTOR_OTHER, + MEMORY_FORMFACTOR_UNKNOWN, + MEMORY_FORMFACTOR_SIMM, + MEMORY_FORMFACTOR_SIP, + MEMORY_FORMFACTOR_CHIP, + MEMORY_FORMFACTOR_DIP, + MEMORY_FORMFACTOR_ZIP, + MEMORY_FORMFACTOR_PROPRIETARY_CARD, + MEMORY_FORMFACTOR_TSOP, + MEMORY_FORMFACTOR_ROC, + MEMORY_FORMFACTOR_SRIMM, + MEMORY_FORMFACTOR_FBDIMM, + MEMORY_FORMFACTOR_DIE, + }; + for (int i = 0; i < ARRAY_SIZE(undefined_factors); ++i) { + assert_int_equal(SPD_UNDEFINED, + smbios_form_factor_to_spd_mod_type(undefined_factors[i])); + } +} + +int main(void) +{ + const struct CMUnitTest tests[] = { + cmocka_unit_test(test_smbios_bus_width_to_spd_width), + cmocka_unit_test(test_smbios_memory_size_to_mib), + cmocka_unit_test(test_smbios_form_factor_to_spd_mod_type), + }; + + return cmocka_run_group_tests(tests, NULL, NULL); +} -- To view, visit https://review.coreboot.org/c/coreboot/+/52192 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I536566ba883bbeb558587a8d71e3d86152fb5e14 Gerrit-Change-Number: 52192 Gerrit-PatchSet: 1 Gerrit-Owner: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: intel/common/block/tcss: Add a weak funtion for mainboard_tcss_get_po...
by Tim Wawrzynczak (Code Review) 08 Apr '21

08 Apr '21

Attention is currently required from: Rizwan Qureshi, Deepti Deshatty, Patrick Rudolph. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52183 ) Change subject: intel/common/block/tcss: Add a weak funtion for mainboard_tcss_get_port_info() ...................................................................... Patch Set 3: Code-Review-1 (1 comment) Patchset: PS3: It was intentional to not leave a weak function in place. I intended for the mainboard developer to add a `mainboard_tcss_get_port_info()` function in the same patch that they add SOC_INTEL_COMMON_BLOCK_TCSS -- To view, visit https://review.coreboot.org/c/coreboot/+/52183 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6ccc799f28d45f5ffd0e9b8179ed973744af8113 Gerrit-Change-Number: 52183 Gerrit-PatchSet: 3 Gerrit-Owner: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Deepti Deshatty <deepti.deshatty(a)intel.corp-partner.google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Attention: Deepti Deshatty <deepti.deshatty(a)intel.corp-partner.google.com> Gerrit-Attention: Deepti Deshatty <deepti.deshatty(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Thu, 08 Apr 2021 14:25:35 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/alderlake/acpi: Skip D3Cold for TBT
by Tim Wawrzynczak (Code Review) 08 Apr '21

08 Apr '21

Attention is currently required from: V Sowmya, Alex Levin, Sugnan Prabhu S, Rizwan Qureshi, Subramony Sesha (Anand), Ruben Rodriguez Buchillon, Aamir Bohra, Patrick Rudolph. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/51274 ) Change subject: soc/intel/alderlake/acpi: Skip D3Cold for TBT ...................................................................... Patch Set 3: (1 comment) File src/soc/intel/alderlake/acpi/tcss.asl: https://review.coreboot.org/c/coreboot/+/51274/comment/35b445cf_c12c54df PS3, Line 616: \_SB.PCI0.TDM1.IFWR() The IFWR Method doesn't seem to be necessary, you could just check `\_SB.PCI0.TDM1.INFR` -- To view, visit https://review.coreboot.org/c/coreboot/+/51274 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib9b9ceee4393aeba37fdcb4e05d1b279a6ff72d2 Gerrit-Change-Number: 51274 Gerrit-PatchSet: 3 Gerrit-Owner: Sugnan Prabhu S <sugnan.prabhu.s(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Alex Levin <levinale(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Ruben Rodriguez Buchillon <coconutruben(a)google.com> Gerrit-Reviewer: Subramony Sesha (Anand) <subramony.sesha(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Archana Patni <archana.patni(a)intel.com> Gerrit-CC: Furquan Shaikh <furquan(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-CC: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-CC: Sridhar Siricilla <sridhar.siricilla(a)intel.corp-partner.google.com> Gerrit-CC: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: V Sowmya <v.sowmya(a)intel.com> Gerrit-Attention: Alex Levin <levinale(a)google.com> Gerrit-Attention: Sugnan Prabhu S <sugnan.prabhu.s(a)intel.com> Gerrit-Attention: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Attention: Subramony Sesha (Anand) <subramony.sesha(a)intel.com> Gerrit-Attention: Ruben Rodriguez Buchillon <coconutruben(a)google.com> Gerrit-Attention: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Thu, 08 Apr 2021 14:23:35 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: payloads/tianocore: Fix compilation for UEFIPAYLOAD option
by Stefan Reinauer (Code Review) 08 Apr '21

08 Apr '21

Attention is currently required from: Martin Roth, Matt DeVillier. Stefan Reinauer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52191 ) Change subject: payloads/tianocore: Fix compilation for UEFIPAYLOAD option ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/52191 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I40077f1d370f0cb5627645b305b57e6c71e44095 Gerrit-Change-Number: 52191 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Comment-Date: Thu, 08 Apr 2021 14:15:56 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/intel/adlrvp: Update Mainboard part number and Vendor
by Sathya Prakash M R (Code Review) 08 Apr '21

08 Apr '21

Attention is currently required from: Anil Kumar K, Meera Ravindranath. Sathya Prakash M R has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/51408 ) Change subject: mb/intel/adlrvp: Update Mainboard part number and Vendor ...................................................................... Patch Set 7: Code-Review+1 (1 comment) Patchset: PS7: On the Mosys, i think we need to fix the platform name in mosys based on what is reported. As mentioned in earlier comments, having same platform name as UEFI is required for kernel driver DMI match -- To view, visit https://review.coreboot.org/c/coreboot/+/51408 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7cce423de624e7056e88b52a1443c554fd9123bc Gerrit-Change-Number: 51408 Gerrit-PatchSet: 7 Gerrit-Owner: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Sathya Prakash M R <sathya.prakash.m.r(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-CC: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Attention: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Comment-Date: Thu, 08 Apr 2021 14:13:25 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: payloads/tianocore: Fix compilation for UEFIPAYLOAD option
by Angel Pons (Code Review) 08 Apr '21

08 Apr '21

Attention is currently required from: Martin Roth, Matt DeVillier, Stefan Reinauer. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52191 ) Change subject: payloads/tianocore: Fix compilation for UEFIPAYLOAD option ...................................................................... Patch Set 1: (1 comment) File payloads/external/tianocore/Makefile: https://review.coreboot.org/c/coreboot/+/52191/comment/67b002a1_05f9c6cd PS1, Line 49: ARCH=-a IA32 -a X64 -p UefiPayloadPkg/UefiPayloadPkg.dsc > but that's arch dependent, and what does setting another variable really accomplish when it's only u […] Ack -- To view, visit https://review.coreboot.org/c/coreboot/+/52191 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I40077f1d370f0cb5627645b305b57e6c71e44095 Gerrit-Change-Number: 52191 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Attention: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Comment-Date: Thu, 08 Apr 2021 14:06:20 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Matt DeVillier <matt.devillier(a)gmail.com> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

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Change in coreboot[master]: payloads/tianocore: Fix compilation for UEFIPAYLOAD option
by Matt DeVillier (Code Review) 08 Apr '21

08 Apr '21

Attention is currently required from: Martin Roth, Stefan Reinauer, Angel Pons. Matt DeVillier has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52191 ) Change subject: payloads/tianocore: Fix compilation for UEFIPAYLOAD option ...................................................................... Patch Set 1: (1 comment) File payloads/external/tianocore/Makefile: https://review.coreboot.org/c/coreboot/+/52191/comment/767c0baf_756c9f36 PS1, Line 49: ARCH=-a IA32 -a X64 -p UefiPayloadPkg/UefiPayloadPkg.dsc > I'd add a `dsc_file` variable that gets set accordingly for CorebootPayloadPkg and UefiPayloadPkg but that's arch dependent, and what does setting another variable really accomplish when it's only used one place? -- To view, visit https://review.coreboot.org/c/coreboot/+/52191 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I40077f1d370f0cb5627645b305b57e6c71e44095 Gerrit-Change-Number: 52191 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Comment-Date: Thu, 08 Apr 2021 14:05:03 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

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Change in coreboot[master]: payloads/tianocore: Fix compilation for UEFIPAYLOAD option
by Angel Pons (Code Review) 08 Apr '21

08 Apr '21

Attention is currently required from: Martin Roth, Matt DeVillier, Stefan Reinauer. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52191 ) Change subject: payloads/tianocore: Fix compilation for UEFIPAYLOAD option ...................................................................... Patch Set 1: Code-Review+1 (1 comment) File payloads/external/tianocore/Makefile: https://review.coreboot.org/c/coreboot/+/52191/comment/21d53bf9_5ff8f272 PS1, Line 49: ARCH=-a IA32 -a X64 -p UefiPayloadPkg/UefiPayloadPkg.dsc I'd add a `dsc_file` variable that gets set accordingly for CorebootPayloadPkg and UefiPayloadPkg -- To view, visit https://review.coreboot.org/c/coreboot/+/52191 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I40077f1d370f0cb5627645b305b57e6c71e44095 Gerrit-Change-Number: 52191 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Attention: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Comment-Date: Thu, 08 Apr 2021 14:01:24 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: payloads/tianocore: Fix compilation for UEFIPAYLOAD option
by Matt DeVillier (Code Review) 08 Apr '21

08 Apr '21

Matt DeVillier has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/52191 ) Change subject: payloads/tianocore: Fix compilation for UEFIPAYLOAD option ...................................................................... payloads/tianocore: Fix compilation for UEFIPAYLOAD option Upstream edk2 dropped separate 32-bit support for UefiPayloadPkg, and removed the architecture suffix from the package dsc filename. Test: build/run qemu with CONFIG_TIANOCORE_UEFIPAYLOAD selected. Change-Id: I40077f1d370f0cb5627645b305b57e6c71e44095 Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> --- M payloads/external/tianocore/Makefile 1 file changed, 6 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/91/52191/1 diff --git a/payloads/external/tianocore/Makefile b/payloads/external/tianocore/Makefile index 198c17f..7cd34f1 100644 --- a/payloads/external/tianocore/Makefile +++ b/payloads/external/tianocore/Makefile @@ -39,10 +39,14 @@ TIMEOUT=-D PLATFORM_BOOT_TIMEOUT=$(CONFIG_TIANOCORE_BOOT_TIMEOUT) +ifeq ($(CONFIG_TIANOCORE_COREBOOTPAYLOAD),y) ifeq ($(CONFIG_TIANOCORE_TARGET_IA32), y) -ARCH=-a IA32 -p $(bootloader)/$(bootloader)Ia32.dsc +ARCH=-a IA32 -p CorebootPayloadPkg/CorebootPayloadPkgIa32.dsc else -ARCH=-a IA32 -a X64 -p $(bootloader)/$(bootloader)Ia32X64.dsc +ARCH=-a IA32 -a X64 -p CorebootPayloadPkg/CorebootPayloadPkgIa32X64.dsc +endif +else +ARCH=-a IA32 -a X64 -p UefiPayloadPkg/UefiPayloadPkg.dsc endif BUILD_STR=-q $(ARCH) -t COREBOOT -b $(BUILD_TYPE) $(TIMER) $(TIMEOUT) $(build_flavor) -- To view, visit https://review.coreboot.org/c/coreboot/+/52191 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I40077f1d370f0cb5627645b305b57e6c71e44095 Gerrit-Change-Number: 52191 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-MessageType: newchange

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coreboot-gerrit April 2021