coreboot-gerrit April 2021

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Change in coreboot[master]: tests: Add lib/dimm_info_util-test test case
by Paul Fagerburg (Code Review) 08 Apr '21

08 Apr '21

Attention is currently required from: Jakub Czapiga, Julius Werner, Jan Dabros. Paul Fagerburg has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52192 ) Change subject: tests: Add lib/dimm_info_util-test test case ...................................................................... Patch Set 1: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/52192 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I536566ba883bbeb558587a8d71e3d86152fb5e14 Gerrit-Change-Number: 52192 Gerrit-PatchSet: 1 Gerrit-Owner: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: Jan Dabros <jsd(a)semihalf.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Fagerburg <pfagerburg(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Jan Dabros <jsd(a)semihalf.com> Gerrit-Comment-Date: Thu, 08 Apr 2021 20:24:14 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/supermicro/x11-lga1151v2-series: Add support for X11SCH-F
by Angel Pons (Code Review) 08 Apr '21

08 Apr '21

Attention is currently required from: Felix Singer, Christian Walter, Angel Pons, Michael Niewöhner. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37441 ) Change subject: mb/supermicro/x11-lga1151v2-series: Add support for X11SCH-F ...................................................................... Patch Set 66: (5 comments) File src/mainboard/supermicro/x11-lga1151v2-series/devicetree.cb: https://review.coreboot.org/c/coreboot/+/37441/comment/d41238e8_03ceb5ff PS65, Line 16: device pci 14.2 on end > I've no idea of what this is Done File src/mainboard/supermicro/x11-lga1151v2-series/variants/x11sch-f/overridetree.cb: https://review.coreboot.org/c/coreboot/+/37441/comment/feaf9559_4a22d758 PS64, Line 6: > What is it necessary for? *poke* https://review.coreboot.org/c/coreboot/+/37441/comment/1933f33f_535e4284 PS64, Line 29: register "PcieClkSrcUsage[0]" = "0x80" : register "PcieClkSrcUsage[1]" = "0x80" : register "PcieClkSrcUsage[2]" = "0x80" : register "PcieClkSrcUsage[3]" = "0x80" : register "PcieClkSrcUsage[4]" = "0x80" : register "PcieClkSrcUsage[5]" = "0x80" : register "PcieClkSrcUsage[6]" = "0x80" : register "PcieClkSrcUsage[7]" = "0x80" : register "PcieClkSrcUsage[8]" = "0x80" : register "PcieClkSrcUsage[9]" = "0x80" : register "PcieClkSrcUsage[10]" = "0x80" : register "PcieClkSrcUsage[11]" = "0x80" : register "PcieClkSrcUsage[12]" = "0x80" : register "PcieClkSrcUsage[13]" = "0x80" : register "PcieClkSrcUsage[14]" = "0x80" : register "PcieClkSrcUsage[15]" = "0x80" : : register "PcieClkSrcClkReq[0]" = "0" : register "PcieClkSrcClkReq[1]" = "1" : register "PcieClkSrcClkReq[2]" = "2" : register "PcieClkSrcClkReq[3]" = "3" : register "PcieClkSrcClkReq[4]" = "4" : register "PcieClkSrcClkReq[5]" = "5" : register "PcieClkSrcClkReq[6]" = "6" : register "PcieClkSrcClkReq[7]" = "7" : register "PcieClkSrcClkReq[8]" = "8" : register "PcieClkSrcClkReq[9]" = "9" : register "PcieClkSrcClkReq[10]" = "10" : register "PcieClkSrcClkReq[11]" = "11" : register "PcieClkSrcClkReq[12]" = "12" : register "PcieClkSrcClkReq[13]" = "13" : register "PcieClkSrcClkReq[14]" = "14" : register "PcieClkSrcClkReq[15]" = "15" > Given the non-linear mapping between PCIe RPs and clksrc/clkreq pins, it is not trivial to determine […] Ack https://review.coreboot.org/c/coreboot/+/37441/comment/c9a2061e_b0cee6ba PS64, Line 121: device pci 1d.0 on end # PCIE x4 > add smbios info? Done, and this is actually another NVMe slot File src/mainboard/supermicro/x11-lga1151v2-series/variants/x11sch-f/overridetree.cb: https://review.coreboot.org/c/coreboot/+/37441/comment/b46f23e2_e1d5065a PS65, Line 29: register "PcieClkSrcUsage[0]" = "0x80" : register "PcieClkSrcUsage[1]" = "0x80" : register "PcieClkSrcUsage[2]" = "0x80" : register "PcieClkSrcUsage[3]" = "0x80" : register "PcieClkSrcUsage[4]" = "0x80" : register "PcieClkSrcUsage[5]" = "0x80" : register "PcieClkSrcUsage[6]" = "0x80" : register "PcieClkSrcUsage[7]" = "0x80" : register "PcieClkSrcUsage[8]" = "0x80" : register "PcieClkSrcUsage[9]" = "0x80" : register "PcieClkSrcUsage[10]" = "0x80" : register "PcieClkSrcUsage[11]" = "0x80" : register "PcieClkSrcUsage[12]" = "0x80" : register "PcieClkSrcUsage[13]" = "0x80" : register "PcieClkSrcUsage[14]" = "0x80" : register "PcieClkSrcUsage[15]" = "0x80" : : register "PcieClkSrcClkReq[0]" = "0" : register "PcieClkSrcClkReq[1]" = "1" : register "PcieClkSrcClkReq[2]" = "2" : register "PcieClkSrcClkReq[3]" = "3" : register "PcieClkSrcClkReq[4]" = "4" : register "PcieClkSrcClkReq[5]" = "5" : register "PcieClkSrcClkReq[6]" = "6" : register "PcieClkSrcClkReq[7]" = "7" : register "PcieClkSrcClkReq[8]" = "8" : register "PcieClkSrcClkReq[9]" = "9" : register "PcieClkSrcClkReq[10]" = "10" : register "PcieClkSrcClkReq[11]" = "11" : register "PcieClkSrcClkReq[12]" = "12" : register "PcieClkSrcClkReq[13]" = "13" : register "PcieClkSrcClkReq[14]" = "14" : register "PcieClkSrcClkReq[15]" = "15" : > Looks like the clksrc/clkreq mapping isn't linear. Since none of the ports use CLKREQ# right now, I'll drop that and keep the CLKSRCs free-running. -- To view, visit https://review.coreboot.org/c/coreboot/+/37441 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0ab1cb9462607b9af068bc2374508d99c60d0a30 Gerrit-Change-Number: 37441 Gerrit-PatchSet: 66 Gerrit-Owner: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Guido Beyer @ Prodrive Technologies <guido.beyer(a)prodrive-technologies.com> Gerrit-Reviewer: Justin van Son <justin.van.son(a)prodrive-technologies.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Stef van Os <stef.van.os(a)prodrive-technologies.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: wouter.eckhardt(a)prodrive-technologies.com Gerrit-CC: Jonas Löffelholz Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Attention: Felix Singer <felixsinger(a)posteo.net> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Comment-Date: Thu, 08 Apr 2021 20:23:34 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Felix Singer <felixsinger(a)posteo.net> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Comment-In-Reply-To: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/supermicro/x11-lga1151v2-series: Add support for X11SCH-F
by Angel Pons (Code Review) 08 Apr '21

08 Apr '21

Angel Pons has uploaded a new patch set (#67) to the change originally created by Christian Walter. ( https://review.coreboot.org/c/coreboot/+/37441 ) Change subject: mb/supermicro/x11-lga1151v2-series: Add support for X11SCH-F ...................................................................... mb/supermicro/x11-lga1151v2-series: Add support for X11SCH-F This is a µATX UP server mainboard with a LGA1151 socket and four DDR4 DIMM slots. Unlike existing boards, this one supports Coffee Lake CPUs instead of Skylake and Kaby Lake, thus it is not added as a variant. Tested with an Intel Xeon E-2276G CPU and 4x 16 GiB ECC DDR4 UDIMMs. Working: - All four DIMM slots - Aspeed AST2500 graphics output - Serial console - Super I/O devicetree config - SATA ports - USB ports - IPMI KCS - BMC iKVM (keyboard/mouse input not available before OS loads) - TianoCore from 9elements/edk2 - LinuxBoot - Booting Linux 5.5 and Windows 10 - No ACPI errors in Windows/Linux - TPM support (w/ patched IFD) - Patch IFD at 0x235=0x03 and 0x13E=0x84 Untested: - PCIe/M.2 ports and corresponding SMBIOS information Change-Id: I0ab1cb9462607b9af068bc2374508d99c60d0a30 Signed-off-by: Christian Walter <christian.walter(a)9elements.com> --- M Documentation/mainboard/index.md A Documentation/mainboard/supermicro/x11-lga1151v2-series/x11-lga1151v2-series.md A Documentation/mainboard/supermicro/x11-lga1151v2-series/x11sch-f/x11sch-f.md A Documentation/mainboard/supermicro/x11-lga1151v2-series/x11sch-f/x11sch-f_flash.jpg M MAINTAINERS A src/mainboard/supermicro/x11-lga1151v2-series/Kconfig A src/mainboard/supermicro/x11-lga1151v2-series/Kconfig.name A src/mainboard/supermicro/x11-lga1151v2-series/Makefile.inc A src/mainboard/supermicro/x11-lga1151v2-series/board_info.txt A src/mainboard/supermicro/x11-lga1151v2-series/bootblock.c A src/mainboard/supermicro/x11-lga1151v2-series/devicetree.cb A src/mainboard/supermicro/x11-lga1151v2-series/dsdt.asl A src/mainboard/supermicro/x11-lga1151v2-series/gpio.h A src/mainboard/supermicro/x11-lga1151v2-series/ramstage.c A src/mainboard/supermicro/x11-lga1151v2-series/romstage.c A src/mainboard/supermicro/x11-lga1151v2-series/variants/x11sch-f/board_info.txt A src/mainboard/supermicro/x11-lga1151v2-series/variants/x11sch-f/gpio.c A src/mainboard/supermicro/x11-lga1151v2-series/variants/x11sch-f/overridetree.cb 18 files changed, 793 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/41/37441/67 -- To view, visit https://review.coreboot.org/c/coreboot/+/37441 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0ab1cb9462607b9af068bc2374508d99c60d0a30 Gerrit-Change-Number: 37441 Gerrit-PatchSet: 67 Gerrit-Owner: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Guido Beyer @ Prodrive Technologies <guido.beyer(a)prodrive-technologies.com> Gerrit-Reviewer: Justin van Son <justin.van.son(a)prodrive-technologies.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Stef van Os <stef.van.os(a)prodrive-technologies.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: wouter.eckhardt(a)prodrive-technologies.com Gerrit-CC: Jonas Löffelholz Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: cpu/smm/ssm_stub: Add x86_64 support
by Patrick Rudolph (Code Review) 08 Apr '21

08 Apr '21

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37392 ) Change subject: cpu/smm/ssm_stub: Add x86_64 support ...................................................................... cpu/smm/ssm_stub: Add x86_64 support Enable long mode in SMM handler. x86_32 isn't affected from this change. * Enter long mode * Add 64bit entry to GDT * Use x86_64 SysV ABI calling conventions for C code entry * Change smm_module_params' cpu to size_t as 'push' is native integer Tested on Lenovo T410 with additional x86_64 patches. Change-Id: I26300492e4be62ddd5d80525022c758a019d63a1 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/cpu/x86/smm/smm_stub.S M src/include/cpu/x86/smm.h 2 files changed, 25 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/92/37392/1 diff --git a/src/cpu/x86/smm/smm_stub.S b/src/cpu/x86/smm/smm_stub.S index f0e55f9..3feee9b 100644 --- a/src/cpu/x86/smm/smm_stub.S +++ b/src/cpu/x86/smm/smm_stub.S @@ -90,6 +90,10 @@ /* gdt selector 0x10, flat data segment */ .word 0xffff, 0x0000 .byte 0x00, 0x93, 0xcf, 0x00 + + /* gdt selector 0x18, flat code segment (64-bit) */ + .word 0xffff, 0x0000 + .byte 0x00, 0x9b, 0xaf, 0x00 smm_relocate_gdt_end: .align 4 @@ -172,11 +176,30 @@ /* Align stack to 16 bytes. Another 32 bytes are pushed below. */ andl $0xfffffff0, %esp +#ifdef __x86_64__ + /* entry64.inc preserves ebx, esi, edi */ + mov %ecx, %edi +#include <cpu/x86/64bit/entry64.inc> + mov %edi, %ecx + +#endif + /* Call into the c-based SMM relocation function with the platform * parameters. Equivalent to: * struct arg = { c_handler_params, cpu_num, smm_runtime, canary }; * c_handler(&arg) */ +#ifdef __x86_64__ + push %rbx /* uintptr_t *canary */ + push $(smm_runtime) + push %rcx /* int cpu */ + push c_handler_arg /* void *arg */ + + mov %rsp, %rdi /* *arg */ + + movl c_handler, %eax + call *%rax +#else push $0x0 /* Padding */ push $0x0 /* Padding */ push $0x0 /* Padding */ @@ -187,7 +210,7 @@ push %esp /* smm_module_params *arg (allocated on stack). */ mov c_handler, %eax call *%eax - +#endif /* Retrieve fxsave location. */ mov -4(%ebp), %edi test %edi, %edi diff --git a/src/include/cpu/x86/smm.h b/src/include/cpu/x86/smm.h index cf107b1..0de08b6 100644 --- a/src/include/cpu/x86/smm.h +++ b/src/include/cpu/x86/smm.h @@ -75,7 +75,7 @@ struct smm_module_params { void *arg; - int cpu; + size_t cpu; const struct smm_runtime *runtime; /* A canary value that has been placed at the end of the stack. * If (uintptr_t)canary != *canary then a stack overflow has occurred. -- To view, visit https://review.coreboot.org/c/coreboot/+/37392 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I26300492e4be62ddd5d80525022c758a019d63a1 Gerrit-Change-Number: 37392 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: arch/x86: Reserve space for EC SMSC KBC1098/KBC1126
by Bill XIE (Code Review) 08 Apr '21

08 Apr '21

Attention is currently required from: Bill XIE, Julius Werner. Hello build bot (Jenkins), Julius Werner, Iru Cai (vimacs), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/51671 to look at the new patch set (#2). Change subject: arch/x86: Reserve space for EC SMSC KBC1098/KBC1126 ...................................................................... arch/x86: Reserve space for EC SMSC KBC1098/KBC1126 According to util/kbc1126/README.md, for these ECs to work, the address and size of their two firmware should be written to $s-0x100` (`$s` means the image size, done with kbc1126_ec_insert), which means that every existing section (especially those used to store code) should not overlap this address, otherwise the bootblock will get damaged when inserting firmwares of the EC. In this commit the reserved space could be adjusted with kconfig symbols ECFW_PTR_ADDR and ECFW_PTR_SIZE. Signed-off-by: Bill XIE <persmule(a)hardenedlinux.org> Change-Id: I4f0de0c4d7283e630242fbe84a46e0547783c49e --- M src/arch/x86/bootblock.ld M src/ec/hp/kbc1126/Kconfig M src/ec/hp/kbc1126/Makefile.inc A src/ec/hp/kbc1126/ecfw_ptr.c 4 files changed, 31 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/71/51671/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/51671 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4f0de0c4d7283e630242fbe84a46e0547783c49e Gerrit-Change-Number: 51671 Gerrit-PatchSet: 2 Gerrit-Owner: Bill XIE <persmule(a)hardenedlinux.org> Gerrit-Reviewer: Iru Cai (vimacs) <mytbk920423(a)gmail.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Bill XIE <persmule(a)hardenedlinux.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/amd/bilby: Enable postcode on port 0x80
by Felix Held (Code Review) 08 Apr '21

08 Apr '21

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/52016 ) Change subject: mb/amd/bilby: Enable postcode on port 0x80 ...................................................................... mb/amd/bilby: Enable postcode on port 0x80 selecting SOC_AMD_COMMON_BLOCK_USE_ESPI will disable the lpc decodes, so not selecting that keeps the lpc decodes. Change-Id: I03a8d4b804cee205b9e06b00e2e5a442452f8f86 Signed-off-by: Ritul Guru <ritul.bits(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52016 Reviewed-by: Felix Held <felix-coreboot(a)felixheld.de> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/amd/bilby/Kconfig 1 file changed, 0 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Felix Held: Looks good to me, approved diff --git a/src/mainboard/amd/bilby/Kconfig b/src/mainboard/amd/bilby/Kconfig index 3366705..9f125b7 100644 --- a/src/mainboard/amd/bilby/Kconfig +++ b/src/mainboard/amd/bilby/Kconfig @@ -4,7 +4,6 @@ config BOARD_SPECIFIC_OPTIONS def_bool y - select SOC_AMD_COMMON_BLOCK_USE_ESPI select SOC_AMD_PICASSO select BOARD_ROMSIZE_KB_16384 select AZALIA_PLUGIN_SUPPORT -- To view, visit https://review.coreboot.org/c/coreboot/+/52016 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I03a8d4b804cee205b9e06b00e2e5a442452f8f86 Gerrit-Change-Number: 52016 Gerrit-PatchSet: 6 Gerrit-Owner: ritul guru <ritul.bits(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Martin Roth <martinroth(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/amd/bilby: enable boot from NVMe SSD
by Felix Held (Code Review) 08 Apr '21

08 Apr '21

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/51674 ) Change subject: mb/amd/bilby: enable boot from NVMe SSD ...................................................................... mb/amd/bilby: enable boot from NVMe SSD These changes involve NVMe specific GPIO programming to enable pcie NVMe SSD boot. Add nvme dev,func in devicetree and also remove unused GPIOs programmed in Bilby. Change-Id: I4407f82122c04b13684d4176ba5cd5a9fe03f0db Signed-off-by: Ritul Guru <ritul.bits(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51674 Reviewed-by: Felix Held <felix-coreboot(a)felixheld.de> Reviewed-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/amd/bilby/devicetree.cb M src/mainboard/amd/bilby/early_gpio.c M src/mainboard/amd/bilby/gpio.c M src/mainboard/amd/bilby/port_descriptors.c 4 files changed, 48 insertions(+), 55 deletions(-) Approvals: build bot (Jenkins): Verified Felix Held: Looks good to me, approved Marshall Dawson: Looks good to me, approved ritul guru: Looks good to me, but someone else must approve diff --git a/src/mainboard/amd/bilby/devicetree.cb b/src/mainboard/amd/bilby/devicetree.cb index addb328..c07415e 100644 --- a/src/mainboard/amd/bilby/devicetree.cb +++ b/src/mainboard/amd/bilby/devicetree.cb @@ -130,10 +130,10 @@ register "gpp_clk_config[0]" = "GPP_CLK_REQ" register "gpp_clk_config[1]" = "GPP_CLK_REQ" register "gpp_clk_config[2]" = "GPP_CLK_REQ" - register "gpp_clk_config[3]" = "GPP_CLK_OFF" + register "gpp_clk_config[3]" = "GPP_CLK_REQ" register "gpp_clk_config[4]" = "GPP_CLK_REQ" - register "gpp_clk_config[5]" = "GPP_CLK_OFF" - register "gpp_clk_config[6]" = "GPP_CLK_OFF" + register "gpp_clk_config[5]" = "GPP_CLK_REQ" + register "gpp_clk_config[6]" = "GPP_CLK_REQ" device cpu_cluster 0 on device lapic 0 on end @@ -143,7 +143,9 @@ device pci 0.0 on end # Root Complex device pci 0.2 on end # IOMMU device pci 1.0 on end # Dummy Host Bridge - device pci 1.1 on end # Bridge to PCIe Ethernet chip + device pci 1.1 on end # GPP Bridge 0 + device pci 1.2 on end # GPP Bridge 1 + device pci 1.5 on end # NVMe device pci 8.0 on end # Dummy Host Bridge device pci 8.1 on # Bridge to Bus A device pci 0.0 on end # Internal GPU diff --git a/src/mainboard/amd/bilby/early_gpio.c b/src/mainboard/amd/bilby/early_gpio.c index b6ca995..0a9d266 100644 --- a/src/mainboard/amd/bilby/early_gpio.c +++ b/src/mainboard/amd/bilby/early_gpio.c @@ -1,11 +1,12 @@ /* SPDX-License-Identifier: GPL-2.0-only */ - #include <soc/gpio.h> #include "gpio.h" /* GPIO pins used by coreboot should be initialized in bootblock */ static const struct soc_amd_gpio gpio_set_stage_reset[] = { + /* assert PCIe reset */ + PAD_GPO(GPIO_6, HIGH), /* not LLB */ PAD_GPI(GPIO_12, PULL_UP), /* not USB_OC1_L */ @@ -14,14 +15,16 @@ PAD_GPI(GPIO_18, PULL_UP), /* SDIO eMMC power control */ PAD_NF(GPIO_22, EMMC_PWR_CTRL, PULL_NONE), - /* PCIe Reset 0 */ - PAD_NF(GPIO_26, PCIE_RST_L, PULL_NONE), - /* PCIe Reset 1 */ - PAD_NF(GPIO_27, PCIE_RST1_L, PULL_NONE), + /* PCIe Reset to DP0, DP1, J2105, TP, FP */ + PAD_GPO(GPIO_27, HIGH), /* eSPI CS# */ PAD_NF(GPIO_30, ESPI_CS_L, PULL_NONE), + /* GPP_10G_SELECT => High=10G, Low=x2 NVME (work with AGPIO89) */ + PAD_GPO(GPIO_42, LOW), /* FANOUT0 */ PAD_NF(GPIO_85, FANOUT0, PULL_NONE), + /* APU_COMBO_GPP_SW => High=SATA, Low=x2 NVME (work with EGPIO42) */ + PAD_GPO(GPIO_89, LOW), /* PC beep to codec */ PAD_NF(GPIO_91, SPKR, PULL_NONE), }; diff --git a/src/mainboard/amd/bilby/gpio.c b/src/mainboard/amd/bilby/gpio.c index 999672e..0d49816 100644 --- a/src/mainboard/amd/bilby/gpio.c +++ b/src/mainboard/amd/bilby/gpio.c @@ -9,8 +9,6 @@ * ramstage. */ static const struct soc_amd_gpio gpio_set_stage_ram[] = { - /* EC SCI# */ - PAD_SCI(GPIO_6, PULL_UP, EDGE_LOW), /* I2S SDIN */ PAD_NF(GPIO_7, ACP_I2S_SDIN, PULL_NONE), /* I2S LRCLK */ @@ -23,8 +21,6 @@ PAD_GPI(GPIO_31, PULL_UP), /* NFC IRQ */ PAD_INT(GPIO_69, PULL_UP, EDGE_LOW, STATUS), - /* NFC wake output# */ - PAD_GPO(GPIO_89, HIGH), }; void mainboard_program_gpios(void) diff --git a/src/mainboard/amd/bilby/port_descriptors.c b/src/mainboard/amd/bilby/port_descriptors.c index 8fc94f8..2801c73 100644 --- a/src/mainboard/amd/bilby/port_descriptors.c +++ b/src/mainboard/amd/bilby/port_descriptors.c @@ -3,51 +3,25 @@ #include <soc/platform_descriptors.h> #include <types.h> -static const fsp_dxio_descriptor pollock_dxio_descriptors[] = { - { /* NVME SSD */ +static const fsp_dxio_descriptor pco_dxio_descriptors[] = { + { /* MXM - Entry 0 */ .port_present = true, .engine_type = PCIE_ENGINE, - .start_logical_lane = 0, - .end_logical_lane = 0, - .device_number = 1, - .function_number = 3, - .link_aspm = ASPM_L1, - .link_aspm_L1_1 = true, - .link_aspm_L1_2 = true, - .turn_off_unused_lanes = true, - .clk_req = CLK_REQ0 - }, - { /* WWAN */ - .port_present = true, - .engine_type = PCIE_ENGINE, - .start_logical_lane = 1, - .end_logical_lane = 1, - .device_number = 1, - .function_number = 4, - .link_aspm = ASPM_L1, - .link_aspm_L1_1 = true, - .link_aspm_L1_2 = true, - .turn_off_unused_lanes = true, - .clk_req = CLK_REQ2 - }, - { /* LAN */ - .port_present = true, - .engine_type = PCIE_ENGINE, - .start_logical_lane = 4, - .end_logical_lane = 4, + .start_logical_lane = 15, + .end_logical_lane = 8, .device_number = 1, .function_number = 1, .link_aspm = ASPM_L1, .link_aspm_L1_1 = true, .link_aspm_L1_2 = true, .turn_off_unused_lanes = true, - .clk_req = CLK_REQ1 + .clk_req = CLK_REQ3 }, - { /* WLAN */ + { /* DEVICE_ID_DT - Entry 1 */ .port_present = true, .engine_type = PCIE_ENGINE, - .start_logical_lane = 5, - .end_logical_lane = 5, + .start_logical_lane = 4, + .end_logical_lane = 7, .device_number = 1, .function_number = 2, .link_aspm = ASPM_L1, @@ -55,12 +29,25 @@ .link_aspm_L1_2 = true, .turn_off_unused_lanes = true, .clk_req = CLK_REQ4 - } + }, + { /* PCIE M.2 x2 - Entry 2 */ + .port_present = true, + .engine_type = PCIE_ENGINE, + .start_logical_lane = 0, + .end_logical_lane = 3, + .device_number = 1, + .function_number = 5, + .link_aspm = ASPM_L1, + .link_aspm_L1_1 = true, + .link_aspm_L1_2 = true, + .turn_off_unused_lanes = true, + .clk_req = CLK_REQ2 + }, }; -fsp_ddi_descriptor pollock_ddi_descriptors[] = { - { /* DDI0 - eDP */ - .connector_type = EDP, +static const fsp_ddi_descriptor pco_ddi_descriptors[] = { + { /* DDI0 - DP */ + .connector_type = DP, .aux_index = AUX1, .hdp_index = HDP1 }, @@ -71,6 +58,11 @@ }, { /* DDI2 - DP */ .connector_type = DP, + .aux_index = AUX3, + .hdp_index = HDP3, + }, + { /* DDI3 - DP */ + .connector_type = DP, .aux_index = AUX4, .hdp_index = HDP4, } @@ -80,8 +72,8 @@ const fsp_dxio_descriptor **dxio_descs, size_t *dxio_num, const fsp_ddi_descriptor **ddi_descs, size_t *ddi_num) { - *dxio_descs = pollock_dxio_descriptors; - *dxio_num = ARRAY_SIZE(pollock_dxio_descriptors); - *ddi_descs = pollock_ddi_descriptors; - *ddi_num = ARRAY_SIZE(pollock_ddi_descriptors); + *dxio_descs = pco_dxio_descriptors; + *dxio_num = ARRAY_SIZE(pco_dxio_descriptors); + *ddi_descs = pco_ddi_descriptors; + *ddi_num = ARRAY_SIZE(pco_ddi_descriptors); } -- To view, visit https://review.coreboot.org/c/coreboot/+/51674 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4407f82122c04b13684d4176ba5cd5a9fe03f0db Gerrit-Change-Number: 51674 Gerrit-PatchSet: 11 Gerrit-Owner: ritul guru <ritul.bits(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: ritul guru <ritul.bits(a)gmail.com> Gerrit-CC: Martin Roth <martinroth(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/google/brya: Add FPMCU power control
by Furquan Shaikh (Code Review) 08 Apr '21

08 Apr '21

Attention is currently required from: Tim Wawrzynczak, EricR Lai. Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52185 ) Change subject: mb/google/brya: Add FPMCU power control ...................................................................... Patch Set 1: (1 comment) File src/mainboard/google/brya/variants/brya0/overridetree.cb: https://review.coreboot.org/c/coreboot/+/52185/comment/9894bcd1_3c1a6b13 PS1, Line 196: register "has_power_resource" = "1" > If we just need D0, _INI is good to use. […] Doing it in hardware makes sense to me. I can raise a bug to see if this is something that we can do in future builds. For now, I think we can start with something like: https://review.coreboot.org/c/coreboot/+/52181/comment/7357ab3f_150a962b/ -- To view, visit https://review.coreboot.org/c/coreboot/+/52185 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8a8fae80c3cc186e0a097ab2007abb656f382cbd Gerrit-Change-Number: 52185 Gerrit-PatchSet: 1 Gerrit-Owner: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Comment-Date: Thu, 08 Apr 2021 18:11:55 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Comment-In-Reply-To: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/intel/shadowmountain: Enable Bluetooth config in the devicetree
by Sridhar Siricilla (Code Review) 08 Apr '21

08 Apr '21

Attention is currently required from: V Sowmya, Rizwan Qureshi, Meera Ravindranath, Balaji Manigandan, Deepti Deshatty. Sridhar Siricilla has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52182 ) Change subject: mb/intel/shadowmountain: Enable Bluetooth config in the devicetree ...................................................................... Patch Set 5: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/52182/comment/f91dd76b_601286e1 PS4, Line 17: hange-Id: I1c257988af23d83830c8a980e52e9e741d51da41 > double change id? Ack -- To view, visit https://review.coreboot.org/c/coreboot/+/52182 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7a54d344ef1b0418bee56e7308977a61604b954a Gerrit-Change-Number: 52182 Gerrit-PatchSet: 5 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Deepti Deshatty <deepti.deshatty(a)intel.com> Gerrit-Reviewer: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: V Sowmya <v.sowmya(a)intel.com> Gerrit-Attention: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Attention: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Attention: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Attention: Deepti Deshatty <deepti.deshatty(a)intel.com> Gerrit-Comment-Date: Thu, 08 Apr 2021 18:07:25 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subrata.banik(a)intel.com> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/brya: Add FPMCU power control
by EricR Lai (Code Review) 08 Apr '21

08 Apr '21

Attention is currently required from: Tim Wawrzynczak. EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52185 ) Change subject: mb/google/brya: Add FPMCU power control ...................................................................... Patch Set 1: (1 comment) File src/mainboard/google/brya/variants/brya0/overridetree.cb: https://review.coreboot.org/c/coreboot/+/52185/comment/83048251_cb529119 PS1, Line 196: register "has_power_resource" = "1" > This won't work right now, b/c this will generate a power resource which will let the kernel put the […] If we just need D0, _INI is good to use. But I am think either EC control this or we can use HW to do this since it only need 3ms delay. Totally can do it by add the CAP. -- To view, visit https://review.coreboot.org/c/coreboot/+/52185 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8a8fae80c3cc186e0a097ab2007abb656f382cbd Gerrit-Change-Number: 52185 Gerrit-PatchSet: 1 Gerrit-Owner: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Comment-Date: Thu, 08 Apr 2021 18:07:14 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: comment

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coreboot-gerrit April 2021