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Change subject: soc/amd/{common,picasso}: Move generate_cpu_entries to common
......................................................................
Patch Set 1:
(1 comment)
Patchset:
PS1:
i'd move that to a separate c file, add some kconfig option (SOC_AMD_COMMON_BLOCK_ACPI_CPU_ZEN maybe?) to include this and only select that option in picasso and cezanne
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Change subject: ec/lenovo/h8/acpi: fix wrong calculation
......................................................................
Patch Set 4:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/52144/comment/1221b8c9_794a5379
PS3, Line 11: wrongly converted
> Done :)
I would say you need more coffee, but it's past midnight already. Then, you (and I as well) need more bed 😄
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Change subject: mb/google/mancomb: add DXIO and DDI descriptors
......................................................................
Patch Set 2:
(1 comment)
Patchset:
PS2:
i wonder if the missing pcie engine for lane 4 will result in running into the power management issue where the dummy descriptors were added as a workaround. maybe that's fixed when the prototype is ready, but it's probably something to keep in mind
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Change subject: ec/lenovo/h8/acpi: fix wrong calculation
......................................................................
ec/lenovo/h8/acpi: fix wrong calculation
The conversion to ASL 2.0 syntax in commit 81d55cf introduced a
regression triggering a BUG in Linux when reading the battery current.
Correct the wrongly-converted calculation.
Fixes: 81d55cf ("src/ec/lenovo/h8/acpi/battery.asl: Convert to ASL 2.0")
Tested-by: Andrew A. I. <aidron(a)yandex.ru>
Change-Id: I1cea8f56eb0a674005582c87cad89f10a02d0701
Signed-off-by: Michael Niewöhner <foss(a)mniewoehner.de>
---
M src/ec/lenovo/h8/acpi/battery.asl
1 file changed, 1 insertion(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/44/52144/4
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Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52144 )
Change subject: ec/lenovo/h8/acpi: fix wrong calculation
......................................................................
Patch Set 3:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/52144/comment/d83ef3e5_8507d3b8
PS3, Line 11: wrongly converted
> both is correct, so I leave it as-is :)
wait. you're right. I should have actually read what I wrote \o/
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Change subject: soc/intel/alderlake: revert renaming of CONFIG_MAX_PCIE_CLOCKS
......................................................................
Patch Set 3:
(1 comment)
File src/soc/intel/common/block/pcie/rtd3/rtd3.c:
https://review.coreboot.org/c/coreboot/+/52194/comment/4e868ba6_00c007b1
PS1, Line 203: CONFIG_MAX_PCIE_CLOCK_REQ
> Couple of things: […]
ugh...oversight...fixed
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Change subject: mb/intel/shadowmountain: Enable RTD3 for SD card
......................................................................
mb/intel/shadowmountain: Enable RTD3 for SD card
Enable the PCIe RTD3 driver for the PCIe attached SD card interface
and specify the srcclk pin and reset GPIO.
TEST=Tested on shadowmountain platform to ensure the system can enter the
S0i3.2 substate and suspend/resume is stable
Signed-off-by: Rizwan Qureshi <rizwan.qureshi(a)intel.com>
Change-Id: Ibeb99bea48d72b019cb2adcf38926c3ed39f7b84
---
M src/mainboard/intel/shadowmountain/variants/baseboard/devicetree.cb
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Change subject: soc/intel/alderlake: Enable PCIE RTD3 driver
......................................................................
soc/intel/alderlake: Enable PCIE RTD3 driver
Include the PCIE RTD3 driveri for Alder Lake SoC.
Signed-off-by: Rizwan Qureshi <rizwan.qureshi(a)intel.com>
Change-Id: I4732e4663feff503b249b76aaf70ec142a888963
---
M src/soc/intel/alderlake/Kconfig
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git pull ssh://review.coreboot.org:29418/coreboot refs/changes/95/52195/3
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Change subject: soc/intel/alderlake: revert renaming of CONFIG_MAX_PCIE_CLOCKS
......................................................................
soc/intel/alderlake: revert renaming of CONFIG_MAX_PCIE_CLOCKS
CONFIG_MAX_PCIE_CLOCKS was renamed to MAX_PCIE_CLOCK_SRC in alderlake. However, this config
is being used in common/block/pcie/rtd3 to validate clksrc range.
Signed-off-by: Rizwan Qureshi <rizwan.qureshi(a)intel.com>
Change-Id: I747c94331b68c4ec0b6b5a04149856a4bb384829
---
M src/soc/intel/alderlake/Kconfig
M src/soc/intel/alderlake/chip.h
M src/soc/intel/alderlake/romstage/fsp_params.c
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