coreboot-gerrit April 2021

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Change in coreboot[master]: soc/amd/cezanne: add downcore and SMT disable settings to deviectree
by Felix Held (Code Review) 08 Apr '21

08 Apr '21

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/52197 ) Change subject: soc/amd/cezanne: add downcore and SMT disable settings to deviectree ...................................................................... soc/amd/cezanne: add downcore and SMT disable settings to deviectree TEST=none Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: Id03454ed2be242bce9497560c089f75046ed7e32 --- M src/soc/amd/cezanne/chip.h M src/soc/amd/cezanne/fsp_m_params.c 2 files changed, 10 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/97/52197/1 diff --git a/src/soc/amd/cezanne/chip.h b/src/soc/amd/cezanne/chip.h index 76ecbfa..317dd53 100644 --- a/src/soc/amd/cezanne/chip.h +++ b/src/soc/amd/cezanne/chip.h @@ -11,6 +11,9 @@ struct soc_amd_common_config common_config; u8 i2c_scl_reset; struct dw_i2c_bus_config i2c[I2C_CTRLR_COUNT]; + + uint8_t downcore_mode; + uint8_t disable_smt; }; #endif /* CEZANNE_CHIP_H */ diff --git a/src/soc/amd/cezanne/fsp_m_params.c b/src/soc/amd/cezanne/fsp_m_params.c index f24b601..baf4ca8 100644 --- a/src/soc/amd/cezanne/fsp_m_params.c +++ b/src/soc/amd/cezanne/fsp_m_params.c @@ -4,10 +4,12 @@ #include <amdblocks/memmap.h> #include <assert.h> #include <console/uart.h> +#include <device/device.h> #include <fsp/api.h> #include <soc/platform_descriptors.h> #include <string.h> #include <types.h> +#include "chip.h" static void fill_dxio_descriptors(FSP_M_CONFIG *mcfg, const fsp_dxio_descriptor *descs, size_t num) @@ -51,6 +53,7 @@ void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version) { FSP_M_CONFIG *mcfg = &mupd->FspmConfig; + const struct soc_amd_cezanne_config *config = config_of_soc(); mupd->FspmArchUpd.NvsBufferPtr = (uintptr_t)soc_fill_apob_cache(); @@ -62,5 +65,9 @@ mcfg->serial_port_baudrate = get_uart_baudrate(); mcfg->serial_port_refclk = uart_platform_refclk(); + /* 0 is default */ + mcfg->ccx_down_core_mode = config->downcore_mode; + mcfg->ccx_disable_smt = config->disable_smt; + fsp_fill_pcie_ddi_descriptors(mcfg); } -- To view, visit https://review.coreboot.org/c/coreboot/+/52197 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id03454ed2be242bce9497560c089f75046ed7e32 Gerrit-Change-Number: 52197 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/dedede: Enable HECI
by Aseda Aboagye (Code Review) 08 Apr '21

08 Apr '21

Aseda Aboagye has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/52196 ) Change subject: mb/google/dedede: Enable HECI ...................................................................... mb/google/dedede: Enable HECI This commit enables HECI such that interface can be used from userspace on the dedede mainboards. BUG=b:184219504 TEST=Build and flash drawcia, verify that Intel Flash Programming Tool can communicate with the Converged Security Engine. Signed-off-by: Aseda Aboagye <aaboagye(a)google.com> Change-Id: I5b28c471d6554a5e14538073d48ef47da05936fc --- M src/mainboard/google/dedede/variants/baseboard/devicetree.cb 1 file changed, 3 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/96/52196/1 diff --git a/src/mainboard/google/dedede/variants/baseboard/devicetree.cb b/src/mainboard/google/dedede/variants/baseboard/devicetree.cb index bb76c9c..69dd89c 100644 --- a/src/mainboard/google/dedede/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/dedede/variants/baseboard/devicetree.cb @@ -189,6 +189,9 @@ # - PM_CFG.SLP_LAN_MIN_ASST_WDTH register "PchPmPwrCycDur" = "1" # 1s + # Enable HECI + register "HeciEnabled" = "1" + device domain 0 on device pci 00.0 on end # Host Bridge device pci 02.0 on end # Integrated Graphics Device -- To view, visit https://review.coreboot.org/c/coreboot/+/52196 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5b28c471d6554a5e14538073d48ef47da05936fc Gerrit-Change-Number: 52196 Gerrit-PatchSet: 1 Gerrit-Owner: Aseda Aboagye <aaboagye(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel: Remove SMM HECI disable related options
by Aseda Aboagye (Code Review) 08 Apr '21

08 Apr '21

Attention is currently required from: Furquan Shaikh, Aaron Durbin, Karthik Ramasubramanian. Hello build bot (Jenkins), Furquan Shaikh, Aaron Durbin, Patrick Rudolph, Karthik Ramasubramanian, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/52147 to look at the new patch set (#2). Change subject: soc/intel: Remove SMM HECI disable related options ...................................................................... soc/intel: Remove SMM HECI disable related options The following config options are being removed: - HECI_DISABLE_USING_SMM - SOC_INTEL_COMMON_BLOCK_HECI_DISABLE_IN_SMM Nearly all of the SoCs use both the config option and refer to the device tree to determine if HECI should be disabled. By removing these options we can rely solely on the devicetree configuration to disable HECI. BUG=b:184219504 TEST=With other changes to enable HECI for the dedede mainboard, build and flash drawcia, verify that Intel Flash Programming Tool can communicate with the Converged Security Engine. Signed-off-by: Aseda Aboagye <aaboagye(a)google.com> Change-Id: Iced84faaab8a0cca8400ccd3ec6e4cd525c30e92 --- M src/soc/intel/alderlake/Kconfig M src/soc/intel/alderlake/smihandler.c M src/soc/intel/cannonlake/fsp_params.c M src/soc/intel/cannonlake/smihandler.c M src/soc/intel/common/block/cse/Kconfig M src/soc/intel/common/block/cse/Makefile.inc M src/soc/intel/common/block/smm/Kconfig M src/soc/intel/icelake/Kconfig M src/soc/intel/icelake/smihandler.c M src/soc/intel/jasperlake/Kconfig M src/soc/intel/jasperlake/smihandler.c M src/soc/intel/tigerlake/Kconfig M src/soc/intel/tigerlake/smihandler.c 13 files changed, 6 insertions(+), 30 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/47/52147/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/52147 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iced84faaab8a0cca8400ccd3ec6e4cd525c30e92 Gerrit-Change-Number: 52147 Gerrit-PatchSet: 2 Gerrit-Owner: Aseda Aboagye <aaboagye(a)google.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: ec/lenovo/h8/acpi: fix wrong calculation
by Michael Niewöhner (Code Review) 08 Apr '21

08 Apr '21

Michael Niewöhner has submitted this change. ( https://review.coreboot.org/c/coreboot/+/52144 ) Change subject: ec/lenovo/h8/acpi: fix wrong calculation ...................................................................... ec/lenovo/h8/acpi: fix wrong calculation The conversion to ASL 2.0 syntax in commit 81d55cf introduced a regression triggering a BUG in Linux when reading the battery current. Correct the wrongly-converted calculation. Fixes: 81d55cf ("src/ec/lenovo/h8/acpi/battery.asl: Convert to ASL 2.0") Tested-by: Andrew A. I. <aidron(a)yandex.ru> Change-Id: I1cea8f56eb0a674005582c87cad89f10a02d0701 Signed-off-by: Michael Niewöhner <foss(a)mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52144 Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/ec/lenovo/h8/acpi/battery.asl 1 file changed, 1 insertion(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Angel Pons: Looks good to me, approved diff --git a/src/ec/lenovo/h8/acpi/battery.asl b/src/ec/lenovo/h8/acpi/battery.asl index d5e8c12..ae07540 100644 --- a/src/ec/lenovo/h8/acpi/battery.asl +++ b/src/ec/lenovo/h8/acpi/battery.asl @@ -115,7 +115,7 @@ { Local0 |= 1 // Negate present rate - Local2 -= 0x10000 + Local2 = 0x10000 - Local2 } Else // Full battery, force to 0 { -- To view, visit https://review.coreboot.org/c/coreboot/+/52144 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1cea8f56eb0a674005582c87cad89f10a02d0701 Gerrit-Change-Number: 52144 Gerrit-PatchSet: 5 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Evgeny Zinoviev <me(a)ch1p.io> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: merged

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Change in coreboot[master]: ec/lenovo/h8/acpi: fix wrong calculation
by Angel Pons (Code Review) 08 Apr '21

08 Apr '21

Attention is currently required from: Nico Huber, Paul Menzel, Arthur Heymans, Michael Niewöhner, Evgeny Zinoviev, Alexander Couzens, Patrick Rudolph, HAOUAS Elyes. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52144 ) Change subject: ec/lenovo/h8/acpi: fix wrong calculation ...................................................................... Patch Set 4: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/52144/comment/6b1dd79f_f87be106 PS3, Line 11: wrongly converted > The hyphen isn't needed. "wrongly" is clearly an adverb which makes […] Oh, true. Sorry for the noise. I need to sleep... -- To view, visit https://review.coreboot.org/c/coreboot/+/52144 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1cea8f56eb0a674005582c87cad89f10a02d0701 Gerrit-Change-Number: 52144 Gerrit-PatchSet: 4 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Evgeny Zinoviev <me(a)ch1p.io> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Attention: Evgeny Zinoviev <me(a)ch1p.io> Gerrit-Attention: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Comment-Date: Thu, 08 Apr 2021 22:37:55 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Comment-In-Reply-To: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-MessageType: comment

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Change in coreboot[master]: ec/lenovo/h8/acpi: fix wrong calculation
by Nico Huber (Code Review) 08 Apr '21

08 Apr '21

Attention is currently required from: Paul Menzel, Arthur Heymans, Michael Niewöhner, Evgeny Zinoviev, Alexander Couzens, Patrick Rudolph, HAOUAS Elyes. Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52144 ) Change subject: ec/lenovo/h8/acpi: fix wrong calculation ...................................................................... Patch Set 4: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/52144/comment/8e62898d_3a37b0fd PS3, Line 11: wrongly converted > I would say you need more coffee, but it's past midnight already. […] The hyphen isn't needed. "wrongly" is clearly an adverb which makes it unambiguously refer to `converted`. In such cases, you usually don't use a hyphen. -- To view, visit https://review.coreboot.org/c/coreboot/+/52144 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1cea8f56eb0a674005582c87cad89f10a02d0701 Gerrit-Change-Number: 52144 Gerrit-PatchSet: 4 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Evgeny Zinoviev <me(a)ch1p.io> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Attention: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Attention: Evgeny Zinoviev <me(a)ch1p.io> Gerrit-Attention: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Comment-Date: Thu, 08 Apr 2021 22:32:37 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Comment-In-Reply-To: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/supermicro/x11-lga1151v2-series: Add support for X11SCH-F
by Michael Niewöhner (Code Review) 08 Apr '21

08 Apr '21

Attention is currently required from: Felix Singer, Christian Walter, Angel Pons, Arthur Heymans. Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37441 ) Change subject: mb/supermicro/x11-lga1151v2-series: Add support for X11SCH-F ...................................................................... Patch Set 67: (1 comment) File Documentation/mainboard/supermicro/x11-lga1151v2-series/x11sch-f/x11sch-f.md: https://review.coreboot.org/c/coreboot/+/37441/comment/13c1b7a2_7a9ea76c PS67, Line 32: not working: BMC UI sensor readings - this is probably due to the missing "POST complete" gpio code. see x11ssm-f for example. we need to identify what pin is connected there -- To view, visit https://review.coreboot.org/c/coreboot/+/37441 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0ab1cb9462607b9af068bc2374508d99c60d0a30 Gerrit-Change-Number: 37441 Gerrit-PatchSet: 67 Gerrit-Owner: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Guido Beyer @ Prodrive Technologies <guido.beyer(a)prodrive-technologies.com> Gerrit-Reviewer: Justin van Son <justin.van.son(a)prodrive-technologies.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Stef van Os <stef.van.os(a)prodrive-technologies.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: wouter.eckhardt(a)prodrive-technologies.com Gerrit-CC: Jonas Löffelholz Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Attention: Felix Singer <felixsinger(a)posteo.net> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Thu, 08 Apr 2021 22:30:13 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/ocp/deltalake: enable SOL console via Kconfig
by Michael Niewöhner (Code Review) 08 Apr '21

08 Apr '21

Attention is currently required from: Marc Jones, Anjaneya "Reddy" Chagam, Jonathan Zhang, Johnny Lin, Tim Wawrzynczak, Morgan Jang. Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52091 ) Change subject: mb/ocp/deltalake: enable SOL console via Kconfig ...................................................................... Patch Set 2: (1 comment) Patchset: PS2: > I run make olddefconfig and I confirmed SOC_INTEL_COMMON_BLOCK_LPC_COMB_ENABLE is set to y. Could you retest, please? -- To view, visit https://review.coreboot.org/c/coreboot/+/52091 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ida0632c6d5a3c8a951bf84600e06e394a2bdf022 Gerrit-Change-Number: 52091 Gerrit-PatchSet: 2 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Anjaneya "Reddy" Chagam <anjaneya.chagam(a)intel.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: Morgan Jang <Morgan_Jang(a)wiwynn.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Attention: Anjaneya "Reddy" Chagam <anjaneya.chagam(a)intel.com> Gerrit-Attention: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)google.com> Gerrit-Attention: Morgan Jang <Morgan_Jang(a)wiwynn.com> Gerrit-Comment-Date: Thu, 08 Apr 2021 22:24:12 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Johnny Lin <Johnny_Lin(a)wiwynn.com> Comment-In-Reply-To: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/ocp/tiogapass: enable SOL console via Kconfig
by Michael Niewöhner (Code Review) 08 Apr '21

08 Apr '21

Attention is currently required from: Anjaneya "Reddy" Chagam, Jonathan Zhang, Johnny Lin, Morgan Jang. Hello build bot (Jenkins), Anjaneya "Reddy" Chagam, Jonathan Zhang, Johnny Lin, Morgan Jang, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/52092 to look at the new patch set (#3). Change subject: mb/ocp/tiogapass: enable SOL console via Kconfig ...................................................................... mb/ocp/tiogapass: enable SOL console via Kconfig Enable the SOL console via Kconfig and drop the now redundant mainboard code because common soc code now handles enabling all needed I/O ranges and also mirrors that to the DMI registers. Change-Id: Idaf854d5f0ed17cfa493937df7e9b51b55216c03 Signed-off-by: Michael Niewöhner <foss(a)mniewoehner.de> --- M src/mainboard/ocp/tiogapass/Kconfig M src/mainboard/ocp/tiogapass/bootblock.c 2 files changed, 3 insertions(+), 29 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/92/52092/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/52092 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idaf854d5f0ed17cfa493937df7e9b51b55216c03 Gerrit-Change-Number: 52092 Gerrit-PatchSet: 3 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Anjaneya "Reddy" Chagam <anjaneya.chagam(a)intel.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Morgan Jang <Morgan_Jang(a)wiwynn.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Anjaneya "Reddy" Chagam <anjaneya.chagam(a)intel.com> Gerrit-Attention: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Morgan Jang <Morgan_Jang(a)wiwynn.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/ocp/deltalake: enable SOL console via Kconfig
by Michael Niewöhner (Code Review) 08 Apr '21

08 Apr '21

Attention is currently required from: Marc Jones, Anjaneya "Reddy" Chagam, Jonathan Zhang, Michael Niewöhner, Tim Wawrzynczak, Morgan Jang. Hello Marc Jones, build bot (Jenkins), Anjaneya "Reddy" Chagam, Jonathan Zhang, Johnny Lin, Tim Wawrzynczak, Morgan Jang, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/52091 to look at the new patch set (#3). Change subject: mb/ocp/deltalake: enable SOL console via Kconfig ...................................................................... mb/ocp/deltalake: enable SOL console via Kconfig Enable the SOL console via Kconfig and drop the now redundant mainboard code because common soc code now handles enabling all needed I/O ranges and also mirrors that to the DMI registers. Change-Id: Ida0632c6d5a3c8a951bf84600e06e394a2bdf022 Signed-off-by: Michael Niewöhner <foss(a)mniewoehner.de> --- M src/mainboard/ocp/deltalake/Kconfig M src/mainboard/ocp/deltalake/bootblock.c 2 files changed, 3 insertions(+), 30 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/91/52091/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/52091 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ida0632c6d5a3c8a951bf84600e06e394a2bdf022 Gerrit-Change-Number: 52091 Gerrit-PatchSet: 3 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Anjaneya "Reddy" Chagam <anjaneya.chagam(a)intel.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: Morgan Jang <Morgan_Jang(a)wiwynn.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Attention: Anjaneya "Reddy" Chagam <anjaneya.chagam(a)intel.com> Gerrit-Attention: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Attention: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)google.com> Gerrit-Attention: Morgan Jang <Morgan_Jang(a)wiwynn.com> Gerrit-MessageType: newpatchset

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coreboot-gerrit April 2021