coreboot-gerrit April 2021

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: soc/intel: Remove SMM HECI disable related options
by Karthik Ramasubramanian (Code Review) 08 Apr '21

08 Apr '21

Attention is currently required from: Martin Roth, Furquan Shaikh, Aseda Aboagye, Aaron Durbin. Karthik Ramasubramanian has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52147 ) Change subject: soc/intel: Remove SMM HECI disable related options ...................................................................... Patch Set 3: (1 comment) File src/soc/intel/common/block/cse/Makefile.inc: https://review.coreboot.org/c/coreboot/+/52147/comment/944baa26_3fe29819 PS3, Line 5: y We may have to change it to $(CONFIG_SOC_INTEL_COMMON_BLOCK_CSE) -- To view, visit https://review.coreboot.org/c/coreboot/+/52147 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iced84faaab8a0cca8400ccd3ec6e4cd525c30e92 Gerrit-Change-Number: 52147 Gerrit-PatchSet: 3 Gerrit-Owner: Aseda Aboagye <aaboagye(a)google.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Aseda Aboagye <aaboagye(a)google.com> Gerrit-Attention: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Comment-Date: Thu, 08 Apr 2021 23:59:01 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/amd/cezanne: add downcore and SMT disable settings to deviectree
by Furquan Shaikh (Code Review) 08 Apr '21

08 Apr '21

Attention is currently required from: Jason Glenesk, Raul Rangel, Marshall Dawson, Felix Held. Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52197 ) Change subject: soc/amd/cezanne: add downcore and SMT disable settings to deviectree ...................................................................... Patch Set 1: (2 comments) File src/soc/amd/cezanne/chip.h: https://review.coreboot.org/c/coreboot/+/52197/comment/f02caa5b_d0caa2bb PS1, Line 15: downcore_mode Are there a set of allowed values? If so, can you please use enum? https://review.coreboot.org/c/coreboot/+/52197/comment/9de5ce8f_4e051ee5 PS1, Line 16: uint8_t bool? -- To view, visit https://review.coreboot.org/c/coreboot/+/52197 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id03454ed2be242bce9497560c089f75046ed7e32 Gerrit-Change-Number: 52197 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Thu, 08 Apr 2021 23:58:04 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/brya: Change GPP_E16 default to high
by Furquan Shaikh (Code Review) 08 Apr '21

08 Apr '21

Attention is currently required from: Alex Levin, Tim Wawrzynczak. Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52199 ) Change subject: mb/google/brya: Change GPP_E16 default to high ...................................................................... Patch Set 1: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/52199/comment/b16b2de2_c3367870 PS1, Line 15: No Signed-off-by line in commit message -- To view, visit https://review.coreboot.org/c/coreboot/+/52199 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4f9884d3b2fc8822dda1a6fe743c863aa6c696da Gerrit-Change-Number: 52199 Gerrit-PatchSet: 1 Gerrit-Owner: Alex Levin <levinale(a)google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Alex Levin <levinale(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Comment-Date: Thu, 08 Apr 2021 23:55:24 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/dedede/var/boten: Configure Acoustic noise mitigation UPDs
by Karthik Ramasubramanian (Code Review) 08 Apr '21

08 Apr '21

Attention is currently required from: Henry Sun, Stanley Wu, Paul Fagerburg. Karthik Ramasubramanian has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52135 ) Change subject: mb/google/dedede/var/boten: Configure Acoustic noise mitigation UPDs ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/52135 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I75851bd7c279feeab4ab94f4c82d55bf0e5ce316 Gerrit-Change-Number: 52135 Gerrit-PatchSet: 1 Gerrit-Owner: Stanley Wu <stanley1.wu(a)lcfc.corp-partner.google.com> Gerrit-Reviewer: Henry Sun <henrysun(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Paul Fagerburg <pfagerburg(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Allen Cheng <allen.cheng(a)lcfc.corp-partner.google.com> Gerrit-CC: Kevin Chang <kevin.chang(a)lcfc.corp-partner.google.com> Gerrit-CC: Melo Chuang <melo.chuang(a)lcfc.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-CC: Rasheed Hsueh <rasheed.hsueh(a)lcfc.corp-partner.google.com> Gerrit-CC: Sunshine Chao <sunshine.chao(a)lcfc.corp-partner.google.com> Gerrit-Attention: Henry Sun <henrysun(a)google.com> Gerrit-Attention: Stanley Wu <stanley1.wu(a)lcfc.corp-partner.google.com> Gerrit-Attention: Paul Fagerburg <pfagerburg(a)chromium.org> Gerrit-Comment-Date: Thu, 08 Apr 2021 23:31:53 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/brya: Change GPP_E16 default to high
by Alex Levin (Code Review) 08 Apr '21

08 Apr '21

Alex Levin has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/52199 ) Change subject: mb/google/brya: Change GPP_E16 default to high ...................................................................... mb/google/brya: Change GPP_E16 default to high To enable WWAN we want to release it from reset start. BUG=b:180166408 TEST=WWAN enumerates on brya Change-Id: I4f9884d3b2fc8822dda1a6fe743c863aa6c696da --- M src/mainboard/google/brya/variants/baseboard/gpio.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/99/52199/1 diff --git a/src/mainboard/google/brya/variants/baseboard/gpio.c b/src/mainboard/google/brya/variants/baseboard/gpio.c index dd33b49..4e8a303 100644 --- a/src/mainboard/google/brya/variants/baseboard/gpio.c +++ b/src/mainboard/google/brya/variants/baseboard/gpio.c @@ -191,7 +191,7 @@ /* E15 : RSVD_TP ==> PCH_WP_OD */ PAD_CFG_GPI_GPIO_DRIVER(GPP_E15, NONE, DEEP), /* E16 : RSVD_TP ==> WWAN_RST_L */ - PAD_CFG_GPO(GPP_E16, 0, DEEP), + PAD_CFG_GPO(GPP_E16, 1, DEEP), /* E17 : THC0_SPI1_INT# ==> WWAN_CONFIG3 */ PAD_CFG_GPI(GPP_E17, NONE, DEEP), /* E18 : DDP1_CTRLCLK ==> USB_C0_LSX_SOC_TX */ -- To view, visit https://review.coreboot.org/c/coreboot/+/52199 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4f9884d3b2fc8822dda1a6fe743c863aa6c696da Gerrit-Change-Number: 52199 Gerrit-PatchSet: 1 Gerrit-Owner: Alex Levin <levinale(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/supermicro/x11-lga1151v2-series: Add support for X11SCH-F
by Angel Pons (Code Review) 08 Apr '21

08 Apr '21

Attention is currently required from: Felix Singer, Arthur Heymans, Michael Niewöhner. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37441 ) Change subject: mb/supermicro/x11-lga1151v2-series: Add support for X11SCH-F ...................................................................... Patch Set 67: (17 comments) File Documentation/mainboard/supermicro/x11-lga1151v2-series/x11-lga1151v2-series.md: https://review.coreboot.org/c/coreboot/+/37441/comment/572cf950_0248ffcd PS67, Line 34: - Fix TODOs mentioned in code > are there any? guess that was copypasta from x11-lga1151 none explicit, but some stuff needs to be rechecked. Hmmm, but there's a FIXME on the CLKSRC stuff... File Documentation/mainboard/supermicro/x11-lga1151v2-series/x11sch-f/x11sch-f.md: https://review.coreboot.org/c/coreboot/+/37441/comment/1f177464_03278ff1 PS67, Line 32: > not working: BMC UI sensor readings - this is probably due to the missing "POST complete" gpio code. […] Ack File MAINTAINERS: https://review.coreboot.org/c/coreboot/+/37441/comment/03f91e38_23713f68 PS67, Line 438: s > missing trailing slash I'll add it for consistency. File src/mainboard/supermicro/x11-lga1151v2-series/Kconfig: https://review.coreboot.org/c/coreboot/+/37441/comment/c2b5400b_3e9d8954 PS67, Line 13: SUPERIO_ASPEED_COMMON_PRE_RAM > selected by SUPERIO_ASPEED_AST2400 Gone https://review.coreboot.org/c/coreboot/+/37441/comment/7c3f5348_cfe6b39a PS67, Line 15: > select NO_FADT_8042 Why? File src/mainboard/supermicro/x11-lga1151v2-series/devicetree.cb: https://review.coreboot.org/c/coreboot/+/37441/comment/3a8fb2d3_fce2eebe PS67, Line 12: # SPS doesn't support all commands issued by FSP > huh? heciretry is not a different command but just a for-loop for retry sending commands This was here already when I took over the port. I imagine it's to reduce boot delays when FSP tries to run commands that SPS does not support. https://review.coreboot.org/c/coreboot/+/37441/comment/2b72ff6c_d2b579f8 PS67, Line 38: > nit: tab *squints* oh! https://review.coreboot.org/c/coreboot/+/37441/comment/a8e63670_c3253fb3 PS67, Line 48: ataPortsEnable" = "{ \ : [0] = 1, \ : [1] = 1, \ : [2] = 1, \ : [3] = 1, \ : [4] = 1, \ : [5] = 1, \ : [6] = 1, \ : [7] = 1, \ : }" > no escaping needed Gone https://review.coreboot.org/c/coreboot/+/37441/comment/d6d446b0_b2694ce5 PS67, Line 92: device pci 1f.2 off end # PMC > is the pmc really disabled on vendor fw? Haven't checked myself. I re-enabled it and doesn't seem to have any side-effects. File src/mainboard/supermicro/x11-lga1151v2-series/ramstage.c: https://review.coreboot.org/c/coreboot/+/37441/comment/a167acb0_5e2bc76f PS67, Line 7: mainboard_silicon_init_params > this function should only be used for fsp params, as it's name says. better use mainboard ops. […] Ack File src/mainboard/supermicro/x11-lga1151v2-series/romstage.c: https://review.coreboot.org/c/coreboot/+/37441/comment/180c026e_7e5bccd2 PS67, Line 38: .ect = 0, > defaults to 0, doesn't it? Yes, but the comment above is anchored to this line File src/mainboard/supermicro/x11-lga1151v2-series/variants/x11sch-f/overridetree.cb: https://review.coreboot.org/c/coreboot/+/37441/comment/feaa150a_c63a79ed PS67, Line 22: USB 2.0/3.0 : : # USB OC0 : register "usb2_ports[0]" = "USB2_PORT_MID(OC0)" : register "usb2_ports[2]" = "USB2_PORT_MID(OC0)" : : # USB OC1 : register "usb2_ports[1]" = "USB2_PORT_MID(OC1)" : register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC1)" : : # USB OC2 : register "usb2_ports[3]" = "USB2_PORT_MID(OC2)" : register "usb2_ports[5]" = "USB2_PORT_MID(OC2)" : register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC2)" : register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC2)" : : # USB OC3 : register "usb2_ports[4]" = "USB2_PORT_MID(OC3)" : register "usb2_ports[6]" = "USB2_PORT_MID(OC3)" : : # USB OC4 : register "usb2_ports[7]" = "USB2_PORT_MID(OC4)" : register "usb2_ports[9]" = "USB2_PORT_MID(OC4)" : : # USB OC5 : register "usb2_ports[8]" = "USB2_PORT_MID(OC5)" : register "usb2_ports[10]" = "USB2_PORT_MID(OC5)" : register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC5)" : register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC5)" : : # USB KCS : register "usb2_ports[13]" = "USB2_PORT_MID(OC_SKIP)" : : # USB OC6/7 - not > xhci could be added below and this moved into it. not a must, though. feel free to just close. I'll leave it here next to the PCIe settings, since I have no means to verify this. https://review.coreboot.org/c/coreboot/+/37441/comment/a1caf1c7_2e66da06 PS67, Line 58: On to avoid coalescing? > what for? Was there already when I took over the port. I guess vendor firmware enabled this RP to avoid coalescing, or CB:36651 hadn't landed yet. Will have to check if it can be disabled. https://review.coreboot.org/c/coreboot/+/37441/comment/1b7179f5_5b8e4681 PS67, Line 75: On to avoid coalescing? > what for? Ack https://review.coreboot.org/c/coreboot/+/37441/comment/a6f56ad0_a2f380b3 PS67, Line 84: 5 4 https://review.coreboot.org/c/coreboot/+/37441/comment/c022869f_317a66a1 PS67, Line 87: smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" : "M.2-P_1" "SlotDataBusWidth4X" : > iirc multiline for smbios_slot_desc doesn't work, does it? BUILD_TIMELESS=1 says it makes no difference. If multiline didn't work, why wouldn't SCONFIG complain about it? However, dmidecode data bus width looks wrong: Handle 0x0014, DMI type 9, 19 bytes System Slot Information Designation: M.2-P_1 Type: x4 M.2 Socket 3 Current Usage: Available Length: Other Characteristics: Unknown Bus Address: 0000:00:1c.4 Data Bus Width: 1 Peer Devices: 0 Handle 0x0015, DMI type 9, 19 bytes System Slot Information Designation: M.2-P_2 Type: x4 M.2 Socket 3 Current Usage: Available Length: Other Characteristics: Unknown Bus Address: 0000:00:1d.0 Data Bus Width: 1 Peer Devices: 0 I can't test properly because there are no devices plugged in. https://review.coreboot.org/c/coreboot/+/37441/comment/8196bd5d_3d7d7adf PS67, Line 94: smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" : "M.2-P_2" "SlotDataBusWidth4X" : > iirc multiline for smbios_slot_desc doesn't work, does it? Ack -- To view, visit https://review.coreboot.org/c/coreboot/+/37441 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0ab1cb9462607b9af068bc2374508d99c60d0a30 Gerrit-Change-Number: 37441 Gerrit-PatchSet: 67 Gerrit-Owner: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Guido Beyer @ Prodrive Technologies <guido.beyer(a)prodrive-technologies.com> Gerrit-Reviewer: Justin van Son <justin.van.son(a)prodrive-technologies.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Stef van Os <stef.van.os(a)prodrive-technologies.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: wouter.eckhardt(a)prodrive-technologies.com Gerrit-CC: Jonas Löffelholz Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Attention: Felix Singer <felixsinger(a)posteo.net> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Comment-Date: Thu, 08 Apr 2021 22:52:53 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/supermicro/x11-lga1151v2-series: Add support for X11SCH-F
by Angel Pons (Code Review) 08 Apr '21

08 Apr '21

Attention is currently required from: Felix Singer, Christian Walter, Angel Pons, Arthur Heymans. Angel Pons has uploaded a new patch set (#68) to the change originally created by Christian Walter. ( https://review.coreboot.org/c/coreboot/+/37441 ) Change subject: mb/supermicro/x11-lga1151v2-series: Add support for X11SCH-F ...................................................................... mb/supermicro/x11-lga1151v2-series: Add support for X11SCH-F This is a µATX UP server mainboard with a LGA1151 socket and four DDR4 DIMM slots. Unlike existing boards, this one supports Coffee Lake CPUs instead of Skylake and Kaby Lake, thus it is not added as a variant. Tested with an Intel Xeon E-2276G CPU and 4x 16 GiB ECC DDR4 UDIMMs. Working: - All four DIMM slots - Aspeed AST2500 graphics output - Serial console - Super I/O devicetree config - SATA ports - USB ports - IPMI KCS - BMC iKVM (keyboard/mouse input not available before OS loads) - TianoCore from 9elements/edk2 - LinuxBoot - Booting Linux 5.5 and Windows 10 - No ACPI errors in Windows/Linux - TPM support (w/ patched IFD) - Patch IFD at 0x235=0x03 and 0x13E=0x84 Untested: - PCIe/M.2 ports and corresponding SMBIOS information Change-Id: I0ab1cb9462607b9af068bc2374508d99c60d0a30 Signed-off-by: Christian Walter <christian.walter(a)9elements.com> --- M Documentation/mainboard/index.md A Documentation/mainboard/supermicro/x11-lga1151v2-series/x11-lga1151v2-series.md A Documentation/mainboard/supermicro/x11-lga1151v2-series/x11sch-f/x11sch-f.md A Documentation/mainboard/supermicro/x11-lga1151v2-series/x11sch-f/x11sch-f_flash.jpg M MAINTAINERS A src/mainboard/supermicro/x11-lga1151v2-series/Kconfig A src/mainboard/supermicro/x11-lga1151v2-series/Kconfig.name A src/mainboard/supermicro/x11-lga1151v2-series/Makefile.inc A src/mainboard/supermicro/x11-lga1151v2-series/board_info.txt A src/mainboard/supermicro/x11-lga1151v2-series/bootblock.c A src/mainboard/supermicro/x11-lga1151v2-series/devicetree.cb A src/mainboard/supermicro/x11-lga1151v2-series/dsdt.asl A src/mainboard/supermicro/x11-lga1151v2-series/gpio.h A src/mainboard/supermicro/x11-lga1151v2-series/mainboard.c A src/mainboard/supermicro/x11-lga1151v2-series/romstage.c A src/mainboard/supermicro/x11-lga1151v2-series/variants/x11sch-f/board_info.txt A src/mainboard/supermicro/x11-lga1151v2-series/variants/x11sch-f/gpio.c A src/mainboard/supermicro/x11-lga1151v2-series/variants/x11sch-f/overridetree.cb 18 files changed, 792 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/41/37441/68 -- To view, visit https://review.coreboot.org/c/coreboot/+/37441 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0ab1cb9462607b9af068bc2374508d99c60d0a30 Gerrit-Change-Number: 37441 Gerrit-PatchSet: 68 Gerrit-Owner: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Guido Beyer @ Prodrive Technologies <guido.beyer(a)prodrive-technologies.com> Gerrit-Reviewer: Justin van Son <justin.van.son(a)prodrive-technologies.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Stef van Os <stef.van.os(a)prodrive-technologies.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: wouter.eckhardt(a)prodrive-technologies.com Gerrit-CC: Jonas Löffelholz Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Attention: Felix Singer <felixsinger(a)posteo.net> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel: Remove SMM HECI disable related options
by Aseda Aboagye (Code Review) 08 Apr '21

08 Apr '21

Attention is currently required from: Martin Roth, Furquan Shaikh, Aaron Durbin, Karthik Ramasubramanian. Hello build bot (Jenkins), Patrick Georgi, Martin Roth, Furquan Shaikh, Aaron Durbin, Patrick Rudolph, Karthik Ramasubramanian, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/52147 to look at the new patch set (#3). Change subject: soc/intel: Remove SMM HECI disable related options ...................................................................... soc/intel: Remove SMM HECI disable related options The following config options are being removed: - HECI_DISABLE_USING_SMM - SOC_INTEL_COMMON_BLOCK_HECI_DISABLE_IN_SMM Nearly all of the SoCs use both the config option and refer to the device tree to determine if HECI should be disabled. By removing these options we can rely solely on the devicetree configuration to disable HECI. BUG=b:184219504 TEST=With other changes to enable HECI for the dedede mainboard, build and flash drawcia, verify that Intel Flash Programming Tool can communicate with the Converged Security Engine. Signed-off-by: Aseda Aboagye <aaboagye(a)google.com> Change-Id: Iced84faaab8a0cca8400ccd3ec6e4cd525c30e92 --- M src/soc/intel/alderlake/Kconfig M src/soc/intel/alderlake/smihandler.c M src/soc/intel/cannonlake/fsp_params.c M src/soc/intel/cannonlake/smihandler.c M src/soc/intel/common/block/cse/Kconfig M src/soc/intel/common/block/cse/Makefile.inc M src/soc/intel/common/block/smm/Kconfig M src/soc/intel/elkhartlake/smihandler.c M src/soc/intel/icelake/Kconfig M src/soc/intel/icelake/smihandler.c M src/soc/intel/jasperlake/Kconfig M src/soc/intel/jasperlake/smihandler.c M src/soc/intel/tigerlake/Kconfig M src/soc/intel/tigerlake/smihandler.c 14 files changed, 7 insertions(+), 31 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/47/52147/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/52147 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iced84faaab8a0cca8400ccd3ec6e4cd525c30e92 Gerrit-Change-Number: 52147 Gerrit-PatchSet: 3 Gerrit-Owner: Aseda Aboagye <aaboagye(a)google.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel: Remove SMM HECI disable related options
by Aseda Aboagye (Code Review) 08 Apr '21

08 Apr '21

Attention is currently required from: Martin Roth, Furquan Shaikh, Aaron Durbin, Karthik Ramasubramanian. Aseda Aboagye has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52147 ) Change subject: soc/intel: Remove SMM HECI disable related options ...................................................................... Patch Set 2: (1 comment) File src/soc/intel/cannonlake/smihandler.c: https://review.coreboot.org/c/coreboot/+/52147/comment/4fe93a31_fd6ed612 PS2, Line 22: const struct device *dev = pcidev_path_on_root(PCH_DEVFN_CSE); : if (!is_dev_enabled(dev)) CNL doesn't consult the devicetree here. Is this check sufficient? -- To view, visit https://review.coreboot.org/c/coreboot/+/52147 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iced84faaab8a0cca8400ccd3ec6e4cd525c30e92 Gerrit-Change-Number: 52147 Gerrit-PatchSet: 2 Gerrit-Owner: Aseda Aboagye <aaboagye(a)google.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Thu, 08 Apr 2021 22:48:52 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/amd/cezanne: add STT settings to deviectree
by Felix Held (Code Review) 08 Apr '21

08 Apr '21

Attention is currently required from: Jason Glenesk, Raul Rangel, Marshall Dawson. Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/52198 ) Change subject: soc/amd/cezanne: add STT settings to deviectree ...................................................................... soc/amd/cezanne: add STT settings to deviectree Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: Ifbcc85cc10d59f1418bbf0ed4a0dc7549d589a26 --- M src/soc/amd/cezanne/chip.h M src/soc/amd/cezanne/fsp_m_params.c 2 files changed, 43 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/98/52198/1 diff --git a/src/soc/amd/cezanne/chip.h b/src/soc/amd/cezanne/chip.h index 317dd53..91fabac 100644 --- a/src/soc/amd/cezanne/chip.h +++ b/src/soc/amd/cezanne/chip.h @@ -14,6 +14,27 @@ uint8_t downcore_mode; uint8_t disable_smt; + + uint8_t stt_control; + uint8_t stt_pcb_sensor_count; + uint16_t stt_min_limit; + uint16_t stt_m1; + uint16_t stt_m2; + uint16_t stt_m3; + uint16_t stt_m4; + uint16_t stt_m5; + uint16_t stt_m6; + uint16_t stt_c_apu; + uint16_t stt_c_gpu; + uint16_t stt_c_hs2; + uint16_t stt_alpha_apu; + uint16_t stt_alpha_gpu; + uint16_t stt_alpha_hs2; + uint16_t stt_skin_temp_apu; + uint16_t stt_skin_temp_gpu; + uint16_t stt_skin_temp_hs2; + uint16_t stt_error_coeff; + uint16_t stt_error_rate_coefficient; }; #endif /* CEZANNE_CHIP_H */ diff --git a/src/soc/amd/cezanne/fsp_m_params.c b/src/soc/amd/cezanne/fsp_m_params.c index baf4ca8..cb9e97f 100644 --- a/src/soc/amd/cezanne/fsp_m_params.c +++ b/src/soc/amd/cezanne/fsp_m_params.c @@ -69,5 +69,27 @@ mcfg->ccx_down_core_mode = config->downcore_mode; mcfg->ccx_disable_smt = config->disable_smt; + /* when stt_control isn't 1, FSP will ignore the other stt values */ + mcfg->stt_control = config->stt_control; + mcfg->stt_pcb_sensor_count = config->stt_pcb_sensor_count; + mcfg->stt_min_limit = config->stt_min_limit; + mcfg->stt_m1 = config->stt_m1; + mcfg->stt_m2 = config->stt_m2; + mcfg->stt_m3 = config->stt_m3; + mcfg->stt_m4 = config->stt_m4; + mcfg->stt_m5 = config->stt_m5; + mcfg->stt_m6 = config->stt_m6; + mcfg->stt_c_apu = config->stt_c_apu; + mcfg->stt_c_gpu = config->stt_c_gpu; + mcfg->stt_c_hs2 = config->stt_c_hs2; + mcfg->stt_alpha_apu = config->stt_alpha_apu; + mcfg->stt_alpha_gpu = config->stt_alpha_gpu; + mcfg->stt_alpha_hs2 = config->stt_alpha_hs2; + mcfg->stt_skin_temp_apu = config->stt_skin_temp_apu; + mcfg->stt_skin_temp_gpu = config->stt_skin_temp_gpu; + mcfg->stt_skin_temp_hs2 = config->stt_skin_temp_hs2; + mcfg->stt_error_coeff = config->stt_error_coeff; + mcfg->stt_error_rate_coefficient = config->stt_error_rate_coefficient; + fsp_fill_pcie_ddi_descriptors(mcfg); } -- To view, visit https://review.coreboot.org/c/coreboot/+/52198 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifbcc85cc10d59f1418bbf0ed4a0dc7549d589a26 Gerrit-Change-Number: 52198 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-MessageType: newchange

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coreboot-gerrit April 2021