coreboot-gerrit April 2021

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Change in coreboot[master]: mb/google/guybrush/var/guybrush: Add FPMCU configration
by Ivy Jian (Code Review) 08 Apr '21

08 Apr '21

Attention is currently required from: Furquan Shaikh, Bhanu Prakash Maiya, EricR Lai. Ivy Jian has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52181 ) Change subject: mb/google/guybrush/var/guybrush: Add FPMCU configration ...................................................................... Patch Set 9: (1 comment) File src/mainboard/google/guybrush/variants/guybrush/overridetree.cb: https://review.coreboot.org/c/coreboot/+/52181/comment/92df2074_9e3828bc PS9, Line 113: register "has_power_resource" = "1" > > I tried configure GPIO_32 to high and GPIO_11 to low in "early_gpio_table" then de-assert reset in […] Are the signals GPIO_11(reset) and GPIO_32(enable) driven low at reset? => GPIO_11 is default PU from PPR, GPIO_32 shows n/a. GPIO_11 should not be driven low in early_gpio_table. Else it will break the case of S3 resume. => FP seems not working if not configuring GPIO_11(reset) to low in early_gpio_table -- To view, visit https://review.coreboot.org/c/coreboot/+/52181 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7c56b0db193be6804d07c2f333445c2a1dbf9f59 Gerrit-Change-Number: 52181 Gerrit-PatchSet: 9 Gerrit-Owner: Ivy Jian <ivy_jian(a)compal.corp-partner.google.com> Gerrit-Reviewer: Bhanu Prakash Maiya <bhanumaiya(a)google.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Mathew King <mathewk(a)chromium.org> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Bhanu Prakash Maiya <bhanumaiya(a)google.com> Gerrit-Attention: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Comment-Date: Fri, 09 Apr 2021 05:02:37 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Furquan Shaikh <furquan(a)google.com> Comment-In-Reply-To: Ivy Jian <ivy_jian(a)compal.corp-partner.google.com> Comment-In-Reply-To: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: [Test] Enable -Wcast-function-type
by Jacob Garber (Code Review) 08 Apr '21

08 Apr '21

Jacob Garber has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/52203 ) Change subject: [Test] Enable -Wcast-function-type ...................................................................... [Test] Enable -Wcast-function-type Signed-off-by: Jacob Garber <jgarber1(a)ualberta.ca> Change-Id: I3e872fe00e483ed8c7db64918650a7ceac9aacbe --- M Makefile.inc 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/52203/1 diff --git a/Makefile.inc b/Makefile.inc index a372efa..ddd820f 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -428,7 +428,7 @@ CFLAGS_common += -nostdlib -Wall -Wundef -Wstrict-prototypes -Wmissing-prototypes CFLAGS_common += -Wwrite-strings -Wredundant-decls -Wno-trigraphs -Wimplicit-fallthrough CFLAGS_common += -Wshadow -Wdate-time -Wtype-limits -Wvla -CFLAGS_common += -Wdangling-else +CFLAGS_common += -Wdangling-else -Wcast-function-type CFLAGS_common += -fno-common -ffreestanding -fno-builtin -fomit-frame-pointer CFLAGS_common += -fstrict-aliasing -ffunction-sections -fdata-sections -fno-pie ifeq ($(CONFIG_COMPILER_GCC),y) -- To view, visit https://review.coreboot.org/c/coreboot/+/52203 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3e872fe00e483ed8c7db64918650a7ceac9aacbe Gerrit-Change-Number: 52203 Gerrit-PatchSet: 1 Gerrit-Owner: Jacob Garber <jgarber1(a)ualberta.ca> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/guybrush/var/guybrush: Add FPMCU configration
by Furquan Shaikh (Code Review) 08 Apr '21

08 Apr '21

Attention is currently required from: Bhanu Prakash Maiya, Ivy Jian, EricR Lai. Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52181 ) Change subject: mb/google/guybrush/var/guybrush: Add FPMCU configration ...................................................................... Patch Set 9: (1 comment) File src/mainboard/google/guybrush/variants/guybrush/overridetree.cb: https://review.coreboot.org/c/coreboot/+/52181/comment/7d70a187_478c4f86 PS9, Line 113: register "has_power_resource" = "1" > I tried configure GPIO_32 to high and GPIO_11 to low in "early_gpio_table" then de-assert reset in "base_gpio_table" GPIO_11 should not be driven low in early_gpio_table. Else it will break the case of S3 resume. > But I checked the PPR, both GPIO_11 and GPIO_32 are S5 Domain, does that mean the signals won't retain state in S3 or S0i3? If both are S5 domain, then it means that they will retain state in S3 and S0i3. -- To view, visit https://review.coreboot.org/c/coreboot/+/52181 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7c56b0db193be6804d07c2f333445c2a1dbf9f59 Gerrit-Change-Number: 52181 Gerrit-PatchSet: 9 Gerrit-Owner: Ivy Jian <ivy_jian(a)compal.corp-partner.google.com> Gerrit-Reviewer: Bhanu Prakash Maiya <bhanumaiya(a)google.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Mathew King <mathewk(a)chromium.org> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Bhanu Prakash Maiya <bhanumaiya(a)google.com> Gerrit-Attention: Ivy Jian <ivy_jian(a)compal.corp-partner.google.com> Gerrit-Attention: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Comment-Date: Fri, 09 Apr 2021 04:15:17 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Furquan Shaikh <furquan(a)google.com> Comment-In-Reply-To: Ivy Jian <ivy_jian(a)compal.corp-partner.google.com> Comment-In-Reply-To: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/guybrush/var/guybrush: Add FPMCU configration
by Ivy Jian (Code Review) 08 Apr '21

08 Apr '21

Attention is currently required from: Furquan Shaikh, Bhanu Prakash Maiya, EricR Lai. Ivy Jian has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52181 ) Change subject: mb/google/guybrush/var/guybrush: Add FPMCU configration ...................................................................... Patch Set 9: (1 comment) File src/mainboard/google/guybrush/variants/guybrush/overridetree.cb: https://review.coreboot.org/c/coreboot/+/52181/comment/bb39fa01_e9e42780 PS9, Line 113: register "has_power_resource" = "1" > I am thinking we can connect these pins to EC next time :p We don't care about the driver and CPU... I tried configure GPIO_32 to high and GPIO_11 to low in "early_gpio_table" then de-assert reset in "base_gpio_table", it is working in serial fw, I will try it in no-serial fw when get it working. But I checked the PPR, both GPIO_11 and GPIO_32 are S5 Domain, does that mean the signals won't retain state in S3 or S0i3? -- To view, visit https://review.coreboot.org/c/coreboot/+/52181 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7c56b0db193be6804d07c2f333445c2a1dbf9f59 Gerrit-Change-Number: 52181 Gerrit-PatchSet: 9 Gerrit-Owner: Ivy Jian <ivy_jian(a)compal.corp-partner.google.com> Gerrit-Reviewer: Bhanu Prakash Maiya <bhanumaiya(a)google.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Mathew King <mathewk(a)chromium.org> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Bhanu Prakash Maiya <bhanumaiya(a)google.com> Gerrit-Attention: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Comment-Date: Fri, 09 Apr 2021 04:02:54 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Furquan Shaikh <furquan(a)google.com> Comment-In-Reply-To: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/amd/cezanne: Add GRXS and GTXS method
by EricR Lai (Code Review) 08 Apr '21

08 Apr '21

Attention is currently required from: Jason Glenesk, Raul Rangel, Furquan Shaikh, Martin Roth, Marshall Dawson, Mathew King, Felix Held. Hello Jason Glenesk, Raul Rangel, Furquan Shaikh, Patrick Georgi, Martin Roth, Marshall Dawson, Mathew King, Felix Held, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/52202 to look at the new patch set (#2). Change subject: soc/amd/cezanne: Add GRXS and GTXS method ...................................................................... soc/amd/cezanne: Add GRXS and GTXS method Add GRXS and GTXS support. Move the gpio method into common place. Signed-off-by: Eric Lai <ericr_lai(a)compal.corp-partner.google.com> Change-Id: I8ba377179d6976cf26ed0dc521d8e4eff051dc85 --- M src/soc/amd/cezanne/Kconfig M src/soc/amd/common/block/acpi/Kconfig M src/soc/amd/common/block/acpi/Makefile.inc A src/soc/amd/common/block/acpi/gpio.c M src/soc/amd/picasso/Kconfig M src/soc/amd/picasso/acpi.c 6 files changed, 58 insertions(+), 47 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/02/52202/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/52202 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8ba377179d6976cf26ed0dc521d8e4eff051dc85 Gerrit-Change-Number: 52202 Gerrit-PatchSet: 2 Gerrit-Owner: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Mathew King <mathewk(a)chromium.org> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Mathew King <mathewk(a)chromium.org> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/amd/cezanne: Add GRXS and GTXS method
by EricR Lai (Code Review) 08 Apr '21

08 Apr '21

Attention is currently required from: Jason Glenesk, Raul Rangel, Furquan Shaikh, Martin Roth, Marshall Dawson, Mathew King, Felix Held. EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52202 ) Change subject: soc/amd/cezanne: Add GRXS and GTXS method ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: If you want add stoneyridge support this, I can upload the patch that I did before on picasso. -- To view, visit https://review.coreboot.org/c/coreboot/+/52202 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8ba377179d6976cf26ed0dc521d8e4eff051dc85 Gerrit-Change-Number: 52202 Gerrit-PatchSet: 1 Gerrit-Owner: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Mathew King <mathewk(a)chromium.org> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Mathew King <mathewk(a)chromium.org> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Fri, 09 Apr 2021 03:53:46 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/amd/cezanne: Add GRXS and GTXS method
by EricR Lai (Code Review) 08 Apr '21

08 Apr '21

EricR Lai has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/52202 ) Change subject: soc/amd/cezanne: Add GRXS and GTXS method ...................................................................... soc/amd/cezanne: Add GRXS and GTXS method Add GRXS and GTXS support. Move the gpio method into common place. Signed-off-by: Eric Lai <ericr_lai(a)compal.corp-partner.google.com> Change-Id: I8ba377179d6976cf26ed0dc521d8e4eff051dc85 --- M src/soc/amd/cezanne/Kconfig M src/soc/amd/common/block/acpi/Kconfig M src/soc/amd/common/block/acpi/Makefile.inc A src/soc/amd/common/block/acpi/gpio.c M src/soc/amd/picasso/Kconfig M src/soc/amd/picasso/acpi.c 6 files changed, 56 insertions(+), 47 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/02/52202/1 diff --git a/src/soc/amd/cezanne/Kconfig b/src/soc/amd/cezanne/Kconfig index d682892..59dc4ec 100644 --- a/src/soc/amd/cezanne/Kconfig +++ b/src/soc/amd/cezanne/Kconfig @@ -37,6 +37,7 @@ select SOC_AMD_COMMON select SOC_AMD_COMMON_BLOCK_ACPI select SOC_AMD_COMMON_BLOCK_ACPIMMIO + select SOC_AMD_COMMON_BLOCK_ACPI_GPIO select SOC_AMD_COMMON_BLOCK_AOAC select SOC_AMD_COMMON_BLOCK_APOB select SOC_AMD_COMMON_BLOCK_BANKED_GPIOS diff --git a/src/soc/amd/common/block/acpi/Kconfig b/src/soc/amd/common/block/acpi/Kconfig index 024b378..716610e 100644 --- a/src/soc/amd/common/block/acpi/Kconfig +++ b/src/soc/amd/common/block/acpi/Kconfig @@ -4,3 +4,6 @@ select ACPI_AMD_HARDWARE_SLEEP_VALUES help Select this option to use the AcpiMmio ACPI registers. + +config SOC_AMD_COMMON_BLOCK_ACPI_GPIO + bool diff --git a/src/soc/amd/common/block/acpi/Makefile.inc b/src/soc/amd/common/block/acpi/Makefile.inc index 3f5d47a..1bec9e5 100644 --- a/src/soc/amd/common/block/acpi/Makefile.inc +++ b/src/soc/amd/common/block/acpi/Makefile.inc @@ -9,5 +9,6 @@ ramstage-y += pm_state.c ramstage-y += tables.c +ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_ACPI_GPIO) += gpio.c endif # CONFIG_SOC_AMD_COMMON_BLOCK_ACPI diff --git a/src/soc/amd/common/block/acpi/gpio.c b/src/soc/amd/common/block/acpi/gpio.c new file mode 100644 index 0000000..783680f --- /dev/null +++ b/src/soc/amd/common/block/acpi/gpio.c @@ -0,0 +1,50 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <acpi/acpigen.h> + +static int acpigen_soc_gpio_op(const char *op, unsigned int gpio_num) +{ + if (gpio_num >= SOC_GPIO_TOTAL_PINS) { + printk(BIOS_WARNING, "Warning: Pin %d should be smaller than" + " %d\n", gpio_num, SOC_GPIO_TOTAL_PINS); + return -1; + } + /* op (gpio_num) */ + acpigen_emit_namestring(op); + acpigen_write_integer(gpio_num); + return 0; +} + +static int acpigen_soc_get_gpio_state(const char *op, unsigned int gpio_num) +{ + if (gpio_num >= SOC_GPIO_TOTAL_PINS) { + printk(BIOS_WARNING, "Warning: Pin %d should be smaller than" + " %d\n", gpio_num, SOC_GPIO_TOTAL_PINS); + return -1; + } + /* Store (op (gpio_num), Local0) */ + acpigen_write_store(); + acpigen_soc_gpio_op(op, gpio_num); + acpigen_emit_byte(LOCAL0_OP); + return 0; +} + +int acpigen_soc_read_rx_gpio(unsigned int gpio_num) +{ + return acpigen_soc_get_gpio_state("\\_SB.GRXS", gpio_num); +} + +int acpigen_soc_get_tx_gpio(unsigned int gpio_num) +{ + return acpigen_soc_get_gpio_state("\\_SB.GTXS", gpio_num); +} + +int acpigen_soc_set_tx_gpio(unsigned int gpio_num) +{ + return acpigen_soc_gpio_op("\\_SB.STXS", gpio_num); +} + +int acpigen_soc_clear_tx_gpio(unsigned int gpio_num) +{ + return acpigen_soc_gpio_op("\\_SB.CTXS", gpio_num); +} diff --git a/src/soc/amd/picasso/Kconfig b/src/soc/amd/picasso/Kconfig index b6ab784..765ed60 100644 --- a/src/soc/amd/picasso/Kconfig +++ b/src/soc/amd/picasso/Kconfig @@ -27,6 +27,7 @@ select SOC_AMD_COMMON select SOC_AMD_COMMON_BLOCK_ACPI select SOC_AMD_COMMON_BLOCK_ACPIMMIO + select SOC_AMD_COMMON_BLOCK_ACPI_GPIO select SOC_AMD_COMMON_BLOCK_AOAC select SOC_AMD_COMMON_BLOCK_APOB select SOC_AMD_COMMON_BLOCK_BANKED_GPIOS diff --git a/src/soc/amd/picasso/acpi.c b/src/soc/amd/picasso/acpi.c index 7315b92..b879571 100644 --- a/src/soc/amd/picasso/acpi.c +++ b/src/soc/amd/picasso/acpi.c @@ -364,50 +364,3 @@ acpigen_write_name_integer("PCNT", logical_cores); acpigen_pop_len(); } - -static int acpigen_soc_gpio_op(const char *op, unsigned int gpio_num) -{ - if (gpio_num >= SOC_GPIO_TOTAL_PINS) { - printk(BIOS_WARNING, "Warning: Pin %d should be smaller than" - " %d\n", gpio_num, SOC_GPIO_TOTAL_PINS); - return -1; - } - /* op (gpio_num) */ - acpigen_emit_namestring(op); - acpigen_write_integer(gpio_num); - return 0; -} - -static int acpigen_soc_get_gpio_state(const char *op, unsigned int gpio_num) -{ - if (gpio_num >= SOC_GPIO_TOTAL_PINS) { - printk(BIOS_WARNING, "Warning: Pin %d should be smaller than" - " %d\n", gpio_num, SOC_GPIO_TOTAL_PINS); - return -1; - } - /* Store (op (gpio_num), Local0) */ - acpigen_write_store(); - acpigen_soc_gpio_op(op, gpio_num); - acpigen_emit_byte(LOCAL0_OP); - return 0; -} - -int acpigen_soc_read_rx_gpio(unsigned int gpio_num) -{ - return acpigen_soc_get_gpio_state("\\_SB.GRXS", gpio_num); -} - -int acpigen_soc_get_tx_gpio(unsigned int gpio_num) -{ - return acpigen_soc_get_gpio_state("\\_SB.GTXS", gpio_num); -} - -int acpigen_soc_set_tx_gpio(unsigned int gpio_num) -{ - return acpigen_soc_gpio_op("\\_SB.STXS", gpio_num); -} - -int acpigen_soc_clear_tx_gpio(unsigned int gpio_num) -{ - return acpigen_soc_gpio_op("\\_SB.CTXS", gpio_num); -} -- To view, visit https://review.coreboot.org/c/coreboot/+/52202 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8ba377179d6976cf26ed0dc521d8e4eff051dc85 Gerrit-Change-Number: 52202 Gerrit-PatchSet: 1 Gerrit-Owner: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/amd/cezanne: Add GRXS and GTXS method
by Ivy Jian (Code Review) 08 Apr '21

08 Apr '21

Ivy Jian has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/52184 ) Change subject: soc/amd/cezanne: Add GRXS and GTXS method ...................................................................... Abandoned As comment, this should be moved to common code. -- To view, visit https://review.coreboot.org/c/coreboot/+/52184 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2e3512562f92de230cf2e6967ec90527fb3d62ee Gerrit-Change-Number: 52184 Gerrit-PatchSet: 1 Gerrit-Owner: Ivy Jian <ivy_jian(a)compal.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Mathew King <mathewk(a)chromium.org> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-MessageType: abandon

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Change in coreboot[master]: soc/amd/cezanne: Add GRXS and GTXS method
by EricR Lai (Code Review) 08 Apr '21

08 Apr '21

Attention is currently required from: Jason Glenesk, Raul Rangel, Martin Roth, Marshall Dawson, Mathew King, Ivy Jian, Felix Held. EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52184 ) Change subject: soc/amd/cezanne: Add GRXS and GTXS method ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: > had a look and i'll probably do the moving to common code as a follow-up patch, since stoneyridge is […] We can add Kconfig CONFIG_SOC_AMD_COMMON_BLOCK_ACPI_GPIO in makefile :p -- To view, visit https://review.coreboot.org/c/coreboot/+/52184 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2e3512562f92de230cf2e6967ec90527fb3d62ee Gerrit-Change-Number: 52184 Gerrit-PatchSet: 1 Gerrit-Owner: Ivy Jian <ivy_jian(a)compal.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Mathew King <mathewk(a)chromium.org> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Mathew King <mathewk(a)chromium.org> Gerrit-Attention: Ivy Jian <ivy_jian(a)compal.corp-partner.google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Fri, 09 Apr 2021 03:28:51 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Mathew King <mathewk(a)chromium.org> Comment-In-Reply-To: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/mancomb: add DXIO and DDI descriptors
by EricR Lai (Code Review) 08 Apr '21

08 Apr '21

Attention is currently required from: Raul Rangel, Martin Roth, Mathew King, Felix Held. EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52180 ) Change subject: mb/google/mancomb: add DXIO and DDI descriptors ...................................................................... Patch Set 2: (1 comment) Patchset: PS2: > i wonder if the missing pcie engine for lane 4 will result in running into the power management issu […] I copied from guybrush. If you can fix the issue, I will keep follow up. I will sync all CL merged on guybrush :p Are we good with this? -- To view, visit https://review.coreboot.org/c/coreboot/+/52180 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ica4e6511a5106a958567565b96d5888b8c829ff2 Gerrit-Change-Number: 52180 Gerrit-PatchSet: 2 Gerrit-Owner: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Mathew King <mathewk(a)chromium.org> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Mathew King <mathewk(a)chromium.org> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Fri, 09 Apr 2021 03:27:16 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: comment

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coreboot-gerrit April 2021