coreboot-gerrit April 2021

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Change in coreboot[master]: *x86: Support x2apic mode
by Ravishankar Sarawadi (Code Review) 09 Apr '21

09 Apr '21

Attention is currently required from: Nico Huber, Furquan Shaikh, Jamie Ryu, Wonkyu Kim, Paul Menzel, Angel Pons, Subrata Banik, Kyösti Mälkki, Raj Astekar, Aaron Durbin, Patrick Rudolph. Ravishankar Sarawadi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/51723 ) Change subject: *x86: Support x2apic mode ...................................................................... Patch Set 9: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/51723 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0bb729b0521fb9dc38b7981014755daeaf9ca817 Gerrit-Change-Number: 51723 Gerrit-PatchSet: 9 Gerrit-Owner: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Lance Zhao Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Raj Astekar <raj.astekar(a)intel.com> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Attention: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Attention: Raj Astekar <raj.astekar(a)intel.com> Gerrit-Attention: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Fri, 09 Apr 2021 06:07:33 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: Makefile: export LANG LC_ALL TZ without using COREBOOT_EXPORTS
by Patrick Georgi (Code Review) 09 Apr '21

09 Apr '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/51363 ) Change subject: Makefile: export LANG LC_ALL TZ without using COREBOOT_EXPORTS ...................................................................... Makefile: export LANG LC_ALL TZ without using COREBOOT_EXPORTS LANG LC_ALL TZ are required for reproducible builds. Those environment should be always used for all builds in coreboot and for payloads. By using COREBOOT_EXPORTS those would be removed in payload builds. Change-Id: Iea965abbce23bf6ec408ef587da0a4c4ebc65a27 Signed-off-by: Alexander Couzens <lynxis(a)fe80.eu> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51363 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi(a)google.com> --- M Makefile 1 file changed, 3 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Patrick Georgi: Looks good to me, approved diff --git a/Makefile b/Makefile index d942ee3..e307e1d 100644 --- a/Makefile +++ b/Makefile @@ -24,7 +24,9 @@ LANG:=C LC_ALL:=C TZ:=UTC0 -COREBOOT_EXPORTS += LANG LC_ALL TZ +# don't use COREBOOT_EXPORTS to ensure build steps outside the coreboot build system +# are reproducible +export LANG LC_ALL TZ DOTCONFIG ?= $(top)/.config KCONFIG_CONFIG = $(DOTCONFIG) -- To view, visit https://review.coreboot.org/c/coreboot/+/51363 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iea965abbce23bf6ec408ef587da0a4c4ebc65a27 Gerrit-Change-Number: 51363 Gerrit-PatchSet: 6 Gerrit-Owner: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/google/asurada: early-init eMMC
by Patrick Georgi (Code Review) 09 Apr '21

09 Apr '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/51973 ) Change subject: mb/google/asurada: early-init eMMC ...................................................................... mb/google/asurada: early-init eMMC Some eMMCs need 80+ms for CMD1 to complete. And the payload may need to access eMMC in the very early stage (for example, Depthcharge needs it 20ms after started) so we have to start initialization in coreboot. On Hayato Chromebook this can save ~100ms in total. BUG=b:177389446 TEST=emerge-asurada coreboot BRANCH=asurada Signed-off-by: Wenbin Mei <wenbin.mei(a)mediatek.com> Change-Id: I2f58d203e969dc1a13a479d7dc63b1b162a9ae3f Reviewed-on: https://review.coreboot.org/c/coreboot/+/51973 Reviewed-by: Hung-Te Lin <hungte(a)chromium.org> Reviewed-by: Yu-Ping Wu <yupingso(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/google/asurada/mainboard.c 1 file changed, 6 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Hung-Te Lin: Looks good to me, approved Yu-Ping Wu: Looks good to me, but someone else must approve diff --git a/src/mainboard/google/asurada/mainboard.c b/src/mainboard/google/asurada/mainboard.c index 16325c8..86e8d5f 100644 --- a/src/mainboard/google/asurada/mainboard.c +++ b/src/mainboard/google/asurada/mainboard.c @@ -16,6 +16,7 @@ #include <soc/gpio.h> #include <soc/gpio_common.h> #include <soc/i2c.h> +#include <soc/msdc.h> #include <soc/mtcmos.h> #include <soc/regulator.h> #include <soc/spm.h> @@ -25,6 +26,9 @@ #include <arm-trusted-firmware/include/export/plat/mediatek/common/plat_params_exp.h> +#define MSDC0_BASE 0x11f60000 +#define MSDC0_TOP_BASE 0x11f50000 + #define MSDC0_DRV_MASK 0x3fffffff #define MSDC1_DRV_MASK 0x3ffff000 #define MSDC0_DRV_VALUE 0x24924924 @@ -154,6 +158,8 @@ /* set eMMC cmd/dat/clk/ds/rstb pins driving to 10mA */ clrsetbits32(gpio_base, MSDC0_DRV_MASK, MSDC0_DRV_VALUE); + + mtk_emmc_early_init((void *)MSDC0_BASE, (void *)MSDC0_TOP_BASE); } static void configure_sdcard(void) -- To view, visit https://review.coreboot.org/c/coreboot/+/51973 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2f58d203e969dc1a13a479d7dc63b1b162a9ae3f Gerrit-Change-Number: 51973 Gerrit-PatchSet: 9 Gerrit-Owner: Wenbin Mei <wenbin.mei(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/google/asurada: select mmc storage config
by Patrick Georgi (Code Review) 09 Apr '21

09 Apr '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/52014 ) Change subject: mb/google/asurada: select mmc storage config ...................................................................... mb/google/asurada: select mmc storage config Select mmc storage config for asurada. Build MTK host mmc driver. BUG=b:177389446 TEST=emerge-asurada coreboot BRANCH=asurada Signed-off-by: Wenbin Mei <wenbin.mei(a)mediatek.com> Change-Id: Iac656d57c2b834d1ce393fd991275b897e597b4b Reviewed-on: https://review.coreboot.org/c/coreboot/+/52014 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Hung-Te Lin <hungte(a)chromium.org> Reviewed-by: Yu-Ping Wu <yupingso(a)google.com> --- M src/mainboard/google/asurada/Kconfig M src/soc/mediatek/mt8192/Makefile.inc 2 files changed, 3 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Hung-Te Lin: Looks good to me, approved Yu-Ping Wu: Looks good to me, approved diff --git a/src/mainboard/google/asurada/Kconfig b/src/mainboard/google/asurada/Kconfig index bdd1176..8951008 100644 --- a/src/mainboard/google/asurada/Kconfig +++ b/src/mainboard/google/asurada/Kconfig @@ -29,6 +29,8 @@ select MAINBOARD_FORCE_NATIVE_VGA_INIT select HAVE_LINEAR_FRAMEBUFFER select DRIVER_ANALOGIX_ANX7625 + select COMMONLIB_STORAGE + select COMMONLIB_STORAGE_MMC config MAINBOARD_DIR string diff --git a/src/soc/mediatek/mt8192/Makefile.inc b/src/soc/mediatek/mt8192/Makefile.inc index f88ca11..40bfe2d9 100644 --- a/src/soc/mediatek/mt8192/Makefile.inc +++ b/src/soc/mediatek/mt8192/Makefile.inc @@ -52,6 +52,7 @@ ramstage-y += ../common/mcu.c ramstage-y += mcupm.c ramstage-y += ../common/mmu_operations.c mmu_operations.c +ramstage-$(CONFIG_COMMONLIB_STORAGE_MMC) += ../common/msdc.c ramstage-y += ../common/mtcmos.c mtcmos.c ramstage-y += pmif.c ramstage-y += ../common/rtc.c rtc.c -- To view, visit https://review.coreboot.org/c/coreboot/+/52014 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iac656d57c2b834d1ce393fd991275b897e597b4b Gerrit-Change-Number: 52014 Gerrit-PatchSet: 9 Gerrit-Owner: Wenbin Mei <wenbin.mei(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Xi Chen <xixi.chen(a)mediatek.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/mediatek: add new driver 'msdc' for eMMC
by Patrick Georgi (Code Review) 09 Apr '21

09 Apr '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/51966 ) Change subject: soc/mediatek: add new driver 'msdc' for eMMC ...................................................................... soc/mediatek: add new driver 'msdc' for eMMC Add MTK host mmc driver support. MTK host controller supports eMMC5.1 spec. BUG=b:177389446 TEST=emerge-asurada coreboot BRANCH=asurada Signed-off-by: Wenbin Mei <wenbin.mei(a)mediatek.com> Change-Id: I54a7749ed167c00cd631a76af7c67c654c7bc725 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51966 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Hung-Te Lin <hungte(a)chromium.org> Reviewed-by: Yu-Ping Wu <yupingso(a)google.com> --- M src/commonlib/include/commonlib/sd_mmc_ctrlr.h A src/soc/mediatek/common/include/soc/msdc.h A src/soc/mediatek/common/msdc.c 3 files changed, 665 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Hung-Te Lin: Looks good to me, approved Yu-Ping Wu: Looks good to me, approved diff --git a/src/commonlib/include/commonlib/sd_mmc_ctrlr.h b/src/commonlib/include/commonlib/sd_mmc_ctrlr.h index 1b1dd51..6ac2740 100644 --- a/src/commonlib/include/commonlib/sd_mmc_ctrlr.h +++ b/src/commonlib/include/commonlib/sd_mmc_ctrlr.h @@ -13,6 +13,14 @@ #define CARD_TIMEOUT -19 #define CARD_IN_PROGRESS -20 /* operation is in progress */ +/* MMC status in CBMEM_ID_MMC_STATUS */ +enum { + MMC_STATUS_NEED_RESET = 0, + MMC_STATUS_CMD1_READY_OR_IN_PROGRESS, + MMC_STATUS_CMD1_READY, + MMC_STATUS_CMD1_IN_PROGRESS, +}; + struct mmc_command { uint16_t cmdidx; diff --git a/src/soc/mediatek/common/include/soc/msdc.h b/src/soc/mediatek/common/include/soc/msdc.h new file mode 100644 index 0000000..6208b72 --- /dev/null +++ b/src/soc/mediatek/common/include/soc/msdc.h @@ -0,0 +1,169 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef __MSDC_H_ +#define __MSDC_H_ + +#include <commonlib/sd_mmc_ctrlr.h> + +/*------------------------------*/ +/* Register Offset */ +/*------------------------------*/ +#define MSDC_CFG 0x0 +#define MSDC_IOCON 0x04 +#define MSDC_PS 0x08 +#define MSDC_INT 0x0c +#define MSDC_INTEN 0x10 +#define MSDC_FIFOCS 0x14 +#define MSDC_TXDATA 0x18 +#define MSDC_RXDATA 0x1c +#define SDC_CFG 0x30 +#define SDC_CMD 0x34 +#define SDC_ARG 0x38 +#define SDC_STS 0x3c +#define SDC_RESP0 0x40 +#define SDC_RESP1 0x44 +#define SDC_RESP2 0x48 +#define SDC_RESP3 0x4c +#define SDC_BLK_NUM 0x50 +#define SDC_ADV_CFG0 0x64 +#define EMMC_IOCON 0x7c +#define SDC_ACMD_RESP 0x80 +#define DMA_SA_H4BIT 0x8c +#define MSDC_DMA_SA 0x90 +#define MSDC_DMA_CTRL 0x98 +#define MSDC_DMA_CFG 0x9c +#define MSDC_PATCH_BIT 0xb0 +#define MSDC_PATCH_BIT1 0xb4 +#define MSDC_PATCH_BIT2 0xb8 +#define MSDC_PAD_TUNE 0xec +#define MSDC_PAD_TUNE0 0xf0 +#define PAD_DS_TUNE 0x188 +#define PAD_CMD_TUNE 0x18c +#define EMMC51_CFG0 0x204 +#define EMMC50_CFG0 0x208 +#define EMMC50_CFG1 0x20c +#define EMMC50_CFG3 0x220 +#define SDC_FIFO_CFG 0x228 + +/*-------------------------------*/ +/* Top Pad Register Offset */ +/*-------------------------------*/ +#define EMMC_TOP_CONTROL 0x00 +#define EMMC_TOP_CMD 0x04 +#define EMMC50_PAD_DS_TUNE 0x0c + +/*--------------------------------------------------------------------------*/ +/* Register Mask */ +/*--------------------------------------------------------------------------*/ + +/* MSDC_CFG mask */ +#define MSDC_CFG_MODE (0x1 << 0) /* RW */ +#define MSDC_CFG_CKPDN (0x1 << 1) /* RW */ +#define MSDC_CFG_RST (0x1 << 2) /* RW */ +#define MSDC_CFG_PIO (0x1 << 3) /* RW */ +#define MSDC_CFG_CKSTB (0x1 << 7) /* R */ + +/* MSDC_IOCON mask */ +#define MSDC_IOCON_DDLSEL (0x1 << 3) /* RW */ + +/* MSDC_INT mask */ +#define MSDC_INT_CMDRDY (0x1 << 8) /* W1C */ +#define MSDC_INT_CMDTMO (0x1 << 9) /* W1C */ +#define MSDC_INT_RSPCRCERR (0x1 << 10) /* W1C */ + +/* MSDC_FIFOCS mask */ +#define MSDC_FIFOCS_RXCNT (0xff << 0) /* R */ +#define MSDC_FIFOCS_TXCNT (0xff << 16) /* R */ +#define MSDC_FIFOCS_CLR (0x1 << 31) /* RW */ + +/* SDC_CFG mask */ +#define SDC_CFG_BUSWIDTH (0x3 << 16) /* RW */ +#define SDC_CFG_SDIO (0x1 << 19) /* RW */ +#define SDC_CFG_SDIOIDE (0x1 << 20) /* RW */ +#define SDC_CFG_DTOC (0xff << 24) /* RW */ + +/* SDC_CMD */ +#define SDC_CMD_CMD_S 0 +#define SDC_CMD_CMD_M (0x3f << SDC_CMD_CMD_S) +#define SDC_CMD_RSPTYP_S 7 +#define SDC_CMD_RSPTYP_M (0x7 << SDC_CMD_RSPTYP_S) +#define SDC_CMD_DTYPE_S 11 +#define SDC_CMD_DTYPE_M (0x3 << SDC_CMD_DTYPE_S) +#define SDC_CMD_WR (1 << 13) +#define SDC_CMD_STOP (1 << 14) +#define SDC_CMD_BLK_LEN_S 16 +#define SDC_CMD_BLK_LEN_M (0xfff << SDC_CMD_BLK_LEN_S) + +/* SDC_STS mask */ +#define SDC_STS_SDCBUSY (0x1 << 0) /* RW */ +#define SDC_STS_CMDBUSY (0x1 << 1) /* RW */ + +/* SDC_ADV_CFG0 mask */ +#define SDC_DAT1_IRQ_TRIGGER (0x1 << 19) /* RW */ +#define SDC_RX_ENHANCE_EN (0x1 << 20) /* RW */ + +/* MSDC_PATCH_BIT mask */ +#define MSDC_CKGEN_MSDC_DLY_SEL (0x1f << 10) + +/* PATCH_BIT1 mask */ +#define MSDC_PATCH_BIT1_STOP_DLY (0xf << 8) /* RW */ + +/* PATCH_BIT2 mask */ +#define MSDC_PATCH_BIT2_CFGRESP (0x1 << 15) /* RW */ +#define MSDC_PATCH_BIT2_CFGCRCSTS (0x1 << 28) /* RW */ +#define MSDC_PB2_RESPWAIT (0x3 << 2) /* RW */ + +/* PAD_TUNE mask */ +#define MSDC_PAD_TUNE_RD_SEL (0x1 << 13) /* RW */ +#define MSDC_PAD_TUNE_CMD_SEL (0x1 << 21) /* RW */ + +/* EMMC50_CFG mask */ +#define EMMC50_CFG_CFCSTS_SEL (0x1 << 4) /* RW */ + +/* SDC_FIFO mask */ +#define SDC_FIFO_CFG_WRVALIDSEL (0x1 << 24) /* RW */ +#define SDC_FIFO_CFG_RDVALIDSEL (0x1 << 25) /* RW */ + +/* EMMC_TOP_CONTROL mask */ +#define PAD_DAT_RD_RXDLY_SEL (0x1 << 13) /* RW */ +#define DATA_K_VALUE_SEL (0x1 << 14) /* RW */ +#define SDC_RX_ENH_EN (0x1 << 15) /* TW */ + +/* EMMC_TOP_CMD mask */ +#define PAD_CMD_RD_RXDLY_SEL (0x1 << 11) /* RW */ + +#define CMD_TIMEOUT_MS (5 * 100) /* 500ms */ +#define MSDC_TIMEOUT_US (1000 * 1000) /* 1s */ + +/* SDC_CFG_BUSWIDTH */ +#define MSDC_BUS_1BITS 0x0 +#define MSDC_BUS_4BITS 0x1 +#define MSDC_BUS_8BITS 0x2 + +#define MSDC_SUCCESS 0x0 +#define MSDC_NOT_READY 0x1 + +#define EIO 5 /* I/O error */ +#define ETIMEDOUT 110 /* I/O timed out */ + +#define CMD_INTS_MASK \ + (MSDC_INT_CMDRDY | MSDC_INT_RSPCRCERR | MSDC_INT_CMDTMO) + +struct msdc_ctrlr { + struct sd_mmc_ctrlr sd_mmc_ctrlr; + void *base; /* IO address */ + void *top_base; /* Top IO address */ + + uint32_t clock; /* Current clock frequency */ + uint32_t src_hz; /* Source clock frequency */ + + bool initialized; +}; + +#define msdc_debug(format...) printk(BIOS_DEBUG, format) +#define msdc_trace(format...) printk(BIOS_DEBUG, format) +#define msdc_error(format...) printk(BIOS_ERR, "ERROR: " format) + +int mtk_emmc_early_init(void *base, void *top_base); + +#endif // MTK_MMC_H_ diff --git a/src/soc/mediatek/common/msdc.c b/src/soc/mediatek/common/msdc.c new file mode 100644 index 0000000..a5a8a6b --- /dev/null +++ b/src/soc/mediatek/common/msdc.c @@ -0,0 +1,488 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * MTK MSDC Host Controller interface specific code + */ +#include <assert.h> +#include <cbmem.h> +#include <commonlib/bsd/helpers.h> +#include <commonlib/storage/sd_mmc.h> +#include <delay.h> +#include <device/mmio.h> +#include <lib.h> +#include <soc/msdc.h> +#include <string.h> +#include <timer.h> + +static inline void msdc_set_field(void *reg, u32 field, u32 val) +{ + clrsetbits32(reg, field, val << __ffs(field)); +} + +/* + * Periodically poll an address until a condition is met or a timeout occurs + * @addr: Address to poll + * @mask: mask condition + * @timeout: Timeout in us, 0 means never timeout + * + * Returns 0 on success and -MSDC_NOT_READY upon a timeout. + */ +static int msdc_poll_timeout(void *addr, u32 mask) +{ + struct stopwatch timer; + stopwatch_init_usecs_expire(&timer, MSDC_TIMEOUT_US); + u32 reg; + + do { + reg = read32(addr); + if (stopwatch_expired(&timer)) + return -MSDC_NOT_READY; + udelay(1); + } while (reg & mask); + + return MSDC_SUCCESS; +} + +/* + * Wait for a bit mask in a given register. To avoid endless loops, a + * time-out is implemented here. + */ +static int msdc_wait_done(void *addr, u32 mask, u32 *status) +{ + struct stopwatch timer; + stopwatch_init_usecs_expire(&timer, CMD_TIMEOUT_MS); + u32 reg; + + do { + reg = read32(addr); + if (stopwatch_expired(&timer)) { + if (status) + *status = reg; + return -MSDC_NOT_READY; + } + udelay(1); + } while (!(reg & mask)); + + if (status) + *status = reg; + + return MSDC_SUCCESS; +} + +static void msdc_reset_hw(struct msdc_ctrlr *host) +{ + u32 val; + + setbits32(host->base + MSDC_CFG, MSDC_CFG_RST); + if (msdc_poll_timeout(host->base + MSDC_CFG, MSDC_CFG_RST) != MSDC_SUCCESS) + msdc_error("Softwave reset timeout!\n"); + + setbits32(host->base + MSDC_FIFOCS, MSDC_FIFOCS_CLR); + if (msdc_poll_timeout(host->base + MSDC_FIFOCS, MSDC_FIFOCS_CLR) != MSDC_SUCCESS) + msdc_error("Clear FIFO timeout!\n"); + + val = read32(host->base + MSDC_INT); + write32(host->base + MSDC_INT, val); +} + +static void msdc_init_hw(struct msdc_ctrlr *host) +{ + /* Configure to MMC/SD mode */ + setbits32(host->base + MSDC_CFG, MSDC_CFG_MODE); + + /* Reset */ + msdc_reset_hw(host); + + /* Set PIO mode */ + setbits32(host->base + MSDC_CFG, MSDC_CFG_PIO); + + write32(host->top_base + EMMC_TOP_CONTROL, 0); + write32(host->top_base + EMMC_TOP_CMD, 0); + + write32(host->base + MSDC_IOCON, 0); + clrbits32(host->base + MSDC_IOCON, MSDC_IOCON_DDLSEL); + write32(host->base + MSDC_PATCH_BIT, 0x403c0046); + msdc_set_field(host->base + MSDC_PATCH_BIT, MSDC_CKGEN_MSDC_DLY_SEL, 1); + write32(host->base + MSDC_PATCH_BIT1, 0xffff4089); + setbits32(host->base + EMMC50_CFG0, EMMC50_CFG_CFCSTS_SEL); + + msdc_set_field(host->base + MSDC_PATCH_BIT1, + MSDC_PATCH_BIT1_STOP_DLY, 3); + clrbits32(host->base + SDC_FIFO_CFG, SDC_FIFO_CFG_WRVALIDSEL); + clrbits32(host->base + SDC_FIFO_CFG, SDC_FIFO_CFG_RDVALIDSEL); + + clrbits32(host->base + MSDC_PATCH_BIT1, (1 << 7)); + + msdc_set_field(host->base + MSDC_PATCH_BIT2, MSDC_PB2_RESPWAIT, 3); + if (host->top_base) + setbits32(host->top_base + EMMC_TOP_CONTROL, SDC_RX_ENH_EN); + else + setbits32(host->base + SDC_ADV_CFG0, SDC_RX_ENHANCE_EN); + /* Use async fifo, then no need to tune internal delay */ + clrbits32(host->base + MSDC_PATCH_BIT2, MSDC_PATCH_BIT2_CFGRESP); + setbits32(host->base + MSDC_PATCH_BIT2, MSDC_PATCH_BIT2_CFGCRCSTS); + + if (host->top_base) { + setbits32(host->top_base + EMMC_TOP_CONTROL, + PAD_DAT_RD_RXDLY_SEL); + clrbits32(host->top_base + EMMC_TOP_CONTROL, DATA_K_VALUE_SEL); + setbits32(host->top_base + EMMC_TOP_CMD, PAD_CMD_RD_RXDLY_SEL); + } else { + setbits32(host->base + MSDC_PAD_TUNE, + MSDC_PAD_TUNE_RD_SEL | MSDC_PAD_TUNE_CMD_SEL); + } + + /* Configure to enable SDIO mode. Otherwise, sdio cmd5 will fail. */ + setbits32(host->base + SDC_CFG, SDC_CFG_SDIO); + + /* Config SDIO device detect interrupt function */ + clrbits32(host->base + SDC_CFG, SDC_CFG_SDIOIDE); + setbits32(host->base + SDC_ADV_CFG0, SDC_DAT1_IRQ_TRIGGER); + + /* Configure to default data timeout */ + msdc_set_field(host->base + SDC_CFG, SDC_CFG_DTOC, 3); + + msdc_debug("init hardware done!\n"); +} + +static void msdc_fifo_clr(struct msdc_ctrlr *host) +{ + setbits32(host->base + MSDC_FIFOCS, MSDC_FIFOCS_CLR); + + if (msdc_poll_timeout(host->base + MSDC_FIFOCS, MSDC_FIFOCS_CLR) != MSDC_SUCCESS) + msdc_error("Clear FIFO timeout!\n"); +} + +static u32 msdc_cmd_find_resp(struct msdc_ctrlr *host, struct mmc_command *cmd) +{ + switch (cmd->resp_type) { + case CARD_RSP_R1: + return 0x1; + case CARD_RSP_R1b: + return 0x7; + case CARD_RSP_R2: + return 0x2; + case CARD_RSP_R3: + return 0x3; + case CARD_RSP_NONE: + default: + return 0x0; + } +} + +static bool msdc_cmd_is_ready(struct msdc_ctrlr *host) +{ + int ret; + + ret = msdc_poll_timeout(host->base + SDC_STS, SDC_STS_CMDBUSY); + if (ret != MSDC_SUCCESS) { + msdc_error("CMD bus busy detected, SDC_STS: %#x\n", + read32(host->base + SDC_STS)); + msdc_reset_hw(host); + return false; + } + + ret = msdc_poll_timeout(host->base + SDC_STS, SDC_STS_SDCBUSY); + if (ret != MSDC_SUCCESS) { + msdc_error("SD controller busy detected, SDC_STS: %#x\n", + read32(host->base + SDC_STS)); + msdc_reset_hw(host); + return false; + } + + return true; +} + +static u32 msdc_cmd_prepare_raw_cmd(struct msdc_ctrlr *host, + struct mmc_command *cmd, + struct mmc_data *data) +{ + u32 opcode = cmd->cmdidx; + u32 resp_type = msdc_cmd_find_resp(host, cmd); + u32 blocksize = 0; + u32 dtype = 0; + u32 rawcmd = 0; + + switch (opcode) { + case MMC_CMD_WRITE_MULTIPLE_BLOCK: + case MMC_CMD_READ_MULTIPLE_BLOCK: + dtype = 2; + break; + case MMC_CMD_WRITE_SINGLE_BLOCK: + case MMC_CMD_READ_SINGLE_BLOCK: + case MMC_CMD_AUTO_TUNING_SEQUENCE: + dtype = 1; + break; + case MMC_CMD_SEND_STATUS: + if (data) + dtype = 1; + } + + if (data) { + if (data->flags == DATA_FLAG_READ) + rawcmd |= SDC_CMD_WR; + + if (data->blocks > 1) + dtype = 2; + + blocksize = data->blocksize; + } + + rawcmd |= (opcode << SDC_CMD_CMD_S) & SDC_CMD_CMD_M; + rawcmd |= (resp_type << SDC_CMD_RSPTYP_S) & SDC_CMD_RSPTYP_M; + rawcmd |= (blocksize << SDC_CMD_BLK_LEN_S) & SDC_CMD_BLK_LEN_M; + rawcmd |= (dtype << SDC_CMD_DTYPE_S) & SDC_CMD_DTYPE_M; + + if (opcode == MMC_CMD_STOP_TRANSMISSION) + rawcmd |= SDC_CMD_STOP; + + return rawcmd; +} + +static int msdc_cmd_done(struct msdc_ctrlr *host, int events, + struct mmc_command *cmd) +{ + u32 *rsp = cmd->response; + int ret = 0; + + if (cmd->resp_type & CARD_RSP_PRESENT) { + if (cmd->resp_type & CARD_RSP_136) { + rsp[0] = read32(host->base + SDC_RESP3); + rsp[1] = read32(host->base + SDC_RESP2); + rsp[2] = read32(host->base + SDC_RESP1); + rsp[3] = read32(host->base + SDC_RESP0); + } else { + rsp[0] = read32(host->base + SDC_RESP0); + } + } + + if (!(events & MSDC_INT_CMDRDY)) { + if (cmd->cmdidx != MMC_CMD_AUTO_TUNING_SEQUENCE) { + /* + * should not clear fifo/interrupt as the tune data + * may have already come. + */ + msdc_reset_hw(host); + } + if (events & MSDC_INT_CMDTMO) + ret = -ETIMEDOUT; + else + ret = -EIO; + } + + return ret; +} + +static int msdc_start_command(struct msdc_ctrlr *host, struct mmc_command *cmd, + struct mmc_data *data) +{ + u32 rawcmd, status; + u32 blocks = 0; + int ret; + + if (!msdc_cmd_is_ready(host)) + return -EIO; + + if (read32(host->base + MSDC_FIFOCS) & + (MSDC_FIFOCS_TXCNT | MSDC_FIFOCS_RXCNT)) { + msdc_error("TX/RX FIFO non-empty before start of IO. Reset\n"); + msdc_reset_hw(host); + } + + msdc_fifo_clr(host); + + rawcmd = msdc_cmd_prepare_raw_cmd(host, cmd, data); + + if (data) + blocks = data->blocks; + + write32(host->base + MSDC_INT, CMD_INTS_MASK); + write32(host->base + SDC_BLK_NUM, blocks); + write32(host->base + SDC_ARG, cmd->cmdarg); + write32(host->base + SDC_CMD, rawcmd); + + ret = msdc_wait_done(host->base + MSDC_INT, CMD_INTS_MASK, &status); + if (ret != MSDC_SUCCESS) + status = MSDC_INT_CMDTMO; + + return msdc_cmd_done(host, status, cmd); +} + +static int msdc_send_command(struct sd_mmc_ctrlr *ctrlr, + struct mmc_command *cmd, struct mmc_data *data) +{ + struct msdc_ctrlr *host; + + host = container_of(ctrlr, struct msdc_ctrlr, sd_mmc_ctrlr); + + return msdc_start_command(host, cmd, data); +} + +static void msdc_set_clock(struct msdc_ctrlr *host, u32 clock) +{ + u32 mode, mode_shift; + u32 div, div_mask; + const u32 div_width = 12; + u32 sclk; + u32 hclk = host->src_hz; + struct sd_mmc_ctrlr *ctrlr = &host->sd_mmc_ctrlr; + + if (clock >= hclk) { + mode = 0x1; /* no divisor */ + div = 0; + sclk = hclk; + } else { + mode = 0x0; /* use divisor */ + if (clock >= (hclk / 2)) { + div = 0; /* mean div = 1/2 */ + sclk = hclk / 2; /* sclk = clk / 2 */ + } else { + div = DIV_ROUND_UP(hclk, clock * 4); + sclk = (hclk >> 2) / div; + } + } + + div_mask = (1 << div_width) - 1; + mode_shift = 8 + div_width; + assert(div <= div_mask); + + clrsetbits_le32(host->base + MSDC_CFG, (0x3 << mode_shift) | (div_mask << 8), + (mode << mode_shift) | (div << 8)); + if (msdc_wait_done(host->base + MSDC_CFG, MSDC_CFG_CKSTB, NULL) != MSDC_SUCCESS) + msdc_error("Failed while wait clock stable!\n"); + + ctrlr->bus_hz = sclk; + msdc_debug("sclk: %d\n", sclk); +} + +static void msdc_set_buswidth(struct msdc_ctrlr *host, u32 width) +{ + u32 val = read32(host->base + SDC_CFG); + + val &= ~SDC_CFG_BUSWIDTH; + + switch (width) { + default: + case 1: + val |= (MSDC_BUS_1BITS << 16); + break; + case 4: + val |= (MSDC_BUS_4BITS << 16); + break; + case 8: + val |= (MSDC_BUS_8BITS << 16); + break; + } + + write32(host->base + SDC_CFG, val); + msdc_trace("Bus Width = %d\n", width); +} + +static void msdc_set_ios(struct sd_mmc_ctrlr *ctrlr) +{ + struct msdc_ctrlr *host; + + host = container_of(ctrlr, struct msdc_ctrlr, sd_mmc_ctrlr); + + /* Set the clock frequency */ + if (ctrlr->bus_hz != ctrlr->request_hz) + msdc_set_clock(host, ctrlr->request_hz); + + msdc_set_buswidth(host, ctrlr->bus_width); + +} + +static void msdc_update_pointers(struct msdc_ctrlr *host) +{ + struct sd_mmc_ctrlr *ctrlr = &host->sd_mmc_ctrlr; + + /* Update the routine pointers */ + ctrlr->send_cmd = &msdc_send_command; + ctrlr->set_ios = &msdc_set_ios; + + ctrlr->f_min = 400 * 1000; + ctrlr->f_max = 52 * 1000 * 1000; + ctrlr->bus_width = 1; + ctrlr->caps |= DRVR_CAP_HS | DRVR_CAP_HC; + ctrlr->voltages = 0x40ff8080; +} + +static void add_msdc(struct msdc_ctrlr *host) +{ + struct sd_mmc_ctrlr *ctrlr = &host->sd_mmc_ctrlr; + + msdc_update_pointers(host); + + /* Initialize the MTK MSDC controller */ + msdc_init_hw(host); + + /* Display the results */ + msdc_trace("%#010x: ctrlr->caps\n", ctrlr->caps); + msdc_trace("%d.%03d MHz: ctrlr->f_max\n", + ctrlr->f_max / 1000000, + (ctrlr->f_max / 1000) % 1000); + msdc_trace("%d.%03d MHz: ctrlr->f_min\n", + ctrlr->f_min / 1000000, + (ctrlr->f_min / 1000) % 1000); + msdc_trace("%#010x: ctrlr->voltages\n", ctrlr->voltages); +} + +static void msdc_controller_init(struct msdc_ctrlr *host, void *base, void *top_base) +{ + memset(host, 0, sizeof(*host)); + host->base = base; + host->top_base = top_base; + host->src_hz = 50 * 1000 * 1000; + + add_msdc(host); +} + +static void set_early_mmc_wake_status(int32_t status) +{ + int32_t *ms_cbmem; + + ms_cbmem = cbmem_add(CBMEM_ID_MMC_STATUS, sizeof(status)); + + if (ms_cbmem == NULL) { + printk(BIOS_ERR, + "%s: Failed to add early mmc wake status to cbmem!\n", + __func__); + return; + } + + printk(BIOS_DEBUG, "Early init status = %d\n", status); + *ms_cbmem = status; +} + +int mtk_emmc_early_init(void *base, void *top_base) +{ + struct storage_media media = { 0 }; + int err; + struct msdc_ctrlr msdc_host; + struct sd_mmc_ctrlr *mmc_ctrlr = &msdc_host.sd_mmc_ctrlr; + + /* Init mtk mmc ctrlr */ + msdc_controller_init(&msdc_host, base, top_base); + + media.ctrlr = mmc_ctrlr; + SET_CLOCK(mmc_ctrlr, 400 * 1000); + SET_BUS_WIDTH(mmc_ctrlr, 1); + + /* Reset emmc, send CMD0 */ + if (sd_mmc_go_idle(&media)) + goto out_err; + + /* Send CMD1 */ + err = mmc_send_op_cond(&media); + if (err == 0) + set_early_mmc_wake_status(MMC_STATUS_CMD1_READY); + else if (err == CARD_IN_PROGRESS) + set_early_mmc_wake_status(MMC_STATUS_CMD1_IN_PROGRESS); + else + goto out_err; + + return 0; + +out_err: + set_early_mmc_wake_status(MMC_STATUS_NEED_RESET); + return -1; +} -- To view, visit https://review.coreboot.org/c/coreboot/+/51966 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I54a7749ed167c00cd631a76af7c67c654c7bc725 Gerrit-Change-Number: 51966 Gerrit-PatchSet: 12 Gerrit-Owner: Wenbin Mei <wenbin.mei(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Xi Chen <xixi.chen(a)mediatek.com> Gerrit-Reviewer: Yidi Lin <yidi.lin(a)mediatek.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/google/zork: make SSFC optional in FW_CONFIG
by Kangheui Won (Code Review) 08 Apr '21

08 Apr '21

Kangheui Won has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/52206 ) Change subject: mb/google/zork: make SSFC optional in FW_CONFIG ...................................................................... mb/google/zork: make SSFC optional in FW_CONFIG We expanded FW_CONFIG to 64-bit after many devices are out of the factory. Thus some devices miss SSFC in CBI and that makes whole fw_config to unusable. Making SSFC optional for all zork platforms will keep those device to use their fw_config. BUG=b:184809649 TEST=boot Jelboz, check touchpad is fixed (was broken due to invalidated fw_config) BRANCH=zork Signed-off-by: Kangheui Won <khwon(a)chromium.org> Change-Id: Id713e108550049e0ca1750b0be47dbb63e7687eb --- M src/mainboard/google/zork/Kconfig 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/06/52206/1 diff --git a/src/mainboard/google/zork/Kconfig b/src/mainboard/google/zork/Kconfig index aff1898..c5c174c 100644 --- a/src/mainboard/google/zork/Kconfig +++ b/src/mainboard/google/zork/Kconfig @@ -26,6 +26,7 @@ select EC_GOOGLE_CHROMEEC_BOARDID select EC_GOOGLE_CHROMEEC_ESPI select EC_GOOGLE_CHROMEEC_INCLUDE_SSFC_IN_FW_CONFIG + select EC_GOOGLE_CHROMEEC_SSFC_OPTIONAL_IN_FW_CONFIG select EC_GOOGLE_CHROMEEC_I2C_TUNNEL select EC_GOOGLE_CHROMEEC_SKUID select ELOG -- To view, visit https://review.coreboot.org/c/coreboot/+/52206 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id713e108550049e0ca1750b0be47dbb63e7687eb Gerrit-Change-Number: 52206 Gerrit-PatchSet: 1 Gerrit-Owner: Kangheui Won <khwon(a)chromium.org> Gerrit-MessageType: newchange

1 0

Change in coreboot[master]: chromeec: introduce SSFC_OPTIONAL_IN_FW_CONFIG
by Kangheui Won (Code Review) 08 Apr '21

08 Apr '21

Kangheui Won has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/52205 ) Change subject: chromeec: introduce SSFC_OPTIONAL_IN_FW_CONFIG ...................................................................... chromeec: introduce SSFC_OPTIONAL_IN_FW_CONFIG When EC_GOOGLE_CHROMEEC_INCLUDE_SSFC_IN_FW_CONFIG is enabled and SSFC is not set, all fw_config is invalidated. But for some platform this may not be necessary, we can treat missing SSFC as zero and use other 32 bits of firmware config. Add Kconfig option 'EC_GOOGLE_CHROMEEC_SSFC_OPTIONAL_IN_FW_CONFIG' to make this possible. BUG=b:184809649 TEST=build BRANCH=zork Signed-off-by: Kangheui Won <khwon(a)chromium.org> Change-Id: I21c7b0d449a694d28ad7b3f14b035e3a5830030a --- M src/ec/google/chromeec/Kconfig M src/ec/google/chromeec/ec.c 2 files changed, 10 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/05/52205/1 diff --git a/src/ec/google/chromeec/Kconfig b/src/ec/google/chromeec/Kconfig index 4bb0d65..d3a9faf 100644 --- a/src/ec/google/chromeec/Kconfig +++ b/src/ec/google/chromeec/Kconfig @@ -204,4 +204,11 @@ Fetch Second Source Factory Cache from CBI EEPROM and add it in the most significant 32 bits of firmware configuration. +config EC_GOOGLE_CHROMEEC_SSFC_OPTIONAL_IN_FW_CONFIG + depends on EC_GOOGLE_CHROMEEC_INCLUDE_SSFC_IN_FW_CONFIG + bool + help + While adding Second Source Factory Cache to firmware configuration, ignore it if it + is not set properly instead of falling into UNDEFINED_FW_CONFIG. + source "src/ec/google/chromeec/*/Kconfig" diff --git a/src/ec/google/chromeec/ec.c b/src/ec/google/chromeec/ec.c index affe66e..f0d2d94 100644 --- a/src/ec/google/chromeec/ec.c +++ b/src/ec/google/chromeec/ec.c @@ -854,10 +854,11 @@ * 32 bits. */ if (CONFIG(EC_GOOGLE_CHROMEEC_INCLUDE_SSFC_IN_FW_CONFIG)) { - uint32_t ssfc; + uint32_t ssfc = 0; if (google_chromeec_cbi_get_ssfc(&ssfc)) - return -1; + if (!CONFIG(EC_GOOGLE_CHROMEEC_SSFC_OPTIONAL_IN_FW_CONFIG)) + return -1; *fw_config |= (uint64_t)ssfc << 32; } -- To view, visit https://review.coreboot.org/c/coreboot/+/52205 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I21c7b0d449a694d28ad7b3f14b035e3a5830030a Gerrit-Change-Number: 52205 Gerrit-PatchSet: 1 Gerrit-Owner: Kangheui Won <khwon(a)chromium.org> Gerrit-MessageType: newchange

1 0

Change in coreboot[master]: mb/google/dedede/var/kracko: Add LTE modem support
by Tony Huang (Code Review) 08 Apr '21

08 Apr '21

Tony Huang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/52204 ) Change subject: mb/google/dedede/var/kracko: Add LTE modem support ...................................................................... mb/google/dedede/var/kracko: Add LTE modem support Add LTE modem to devicetree Configure GPIO control for LTE modem BUG=b:178092096 TEST=Built image and verified with command modem status Change-Id: Id8f483e1132a08500fbe950711cc84197ce40b12 Signed-off-by: Tony Huang <tony-huang(a)quanta.corp-partner.google.com> --- A src/mainboard/google/dedede/variants/kracko/Makefile.inc A src/mainboard/google/dedede/variants/kracko/gpio.c M src/mainboard/google/dedede/variants/kracko/overridetree.cb A src/mainboard/google/dedede/variants/kracko/variant.c 4 files changed, 68 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/04/52204/1 diff --git a/src/mainboard/google/dedede/variants/kracko/Makefile.inc b/src/mainboard/google/dedede/variants/kracko/Makefile.inc new file mode 100644 index 0000000..fd60a18 --- /dev/null +++ b/src/mainboard/google/dedede/variants/kracko/Makefile.inc @@ -0,0 +1,5 @@ +## SPDX-License-Identifier: GPL-2.0-or-later + +ramstage-y += gpio.c + +smm-y += variant.c diff --git a/src/mainboard/google/dedede/variants/kracko/gpio.c b/src/mainboard/google/dedede/variants/kracko/gpio.c new file mode 100644 index 0000000..ca89730 --- /dev/null +++ b/src/mainboard/google/dedede/variants/kracko/gpio.c @@ -0,0 +1,25 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <baseboard/gpio.h> +#include <baseboard/variants.h> + +/* Pad configuration in ramstage*/ +static const struct pad_config gpio_table[] = { + /* A10 : WWAN_EN */ + PAD_CFG_GPO(GPP_A10, 1, PWROK), + + /* B7 : PCIE_CLKREQ2_N ==> WWAN_SAR_DETECT_ODL*/ + PAD_CFG_GPO(GPP_B7, 1, DEEP), + + /* D0 : WWAN_HOST_WAKE ==> WWAN_WDISABLE_L */ + PAD_CFG_GPO(GPP_D0, 1, DEEP), + + /* H17 : WWAN_RST_L */ + PAD_CFG_GPO(GPP_H17, 0, PLTRST), +}; + +const struct pad_config *variant_override_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(gpio_table); + return gpio_table; +} diff --git a/src/mainboard/google/dedede/variants/kracko/overridetree.cb b/src/mainboard/google/dedede/variants/kracko/overridetree.cb index 99517bd..66fb274 100644 --- a/src/mainboard/google/dedede/variants/kracko/overridetree.cb +++ b/src/mainboard/google/dedede/variants/kracko/overridetree.cb @@ -55,6 +55,16 @@ chip drivers/usb/acpi device usb 0.0 on chip drivers/usb/acpi + register "desc" = ""LTE"" + register "type" = "UPC_TYPE_INTERNAL" + register "has_power_resource" = "1" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_H17)" + register "reset_off_delay_ms" = "20" + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_A10)" + register "enable_delay_ms" = "20" + device usb 2.3 on end + end + chip drivers/usb/acpi register "desc" = ""UFCamera"" register "type" = "UPC_TYPE_INTERNAL" device usb 2.5 on end @@ -64,6 +74,11 @@ register "type" = "UPC_TYPE_INTERNAL" device usb 2.6 on end end + chip drivers/usb/acpi + register "desc" = ""LTE"" + register "type" = "UPC_TYPE_INTERNAL" + device usb 3.3 on end + end end end end # USB xHCI diff --git a/src/mainboard/google/dedede/variants/kracko/variant.c b/src/mainboard/google/dedede/variants/kracko/variant.c new file mode 100644 index 0000000..22caa06 --- /dev/null +++ b/src/mainboard/google/dedede/variants/kracko/variant.c @@ -0,0 +1,23 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <acpi/acpi.h> +#include <baseboard/variants.h> +#include <delay.h> +#include <gpio.h> + +static void power_off_lte_module(void) +{ + gpio_output(GPP_H17, 0); + mdelay(20); + gpio_output(GPP_A10, 0); +} + +void variant_smi_sleep(u8 slp_typ) +{ + /* + * Once the FW_CONFIG is provisioned, power off LTE module only under + * the situation where it is stuffed. + */ + if (slp_typ == ACPI_S5) + power_off_lte_module(); +} -- To view, visit https://review.coreboot.org/c/coreboot/+/52204 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id8f483e1132a08500fbe950711cc84197ce40b12 Gerrit-Change-Number: 52204 Gerrit-PatchSet: 1 Gerrit-Owner: Tony Huang <tony-huang(a)quanta.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/guybrush/var/guybrush: Add FPMCU configration
by Furquan Shaikh (Code Review) 08 Apr '21

08 Apr '21

Attention is currently required from: Bhanu Prakash Maiya, Ivy Jian, EricR Lai. Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52181 ) Change subject: mb/google/guybrush/var/guybrush: Add FPMCU configration ...................................................................... Patch Set 9: (1 comment) File src/mainboard/google/guybrush/variants/guybrush/overridetree.cb: https://review.coreboot.org/c/coreboot/+/52181/comment/105636e2_3cb68a27 PS9, Line 113: register "has_power_resource" = "1" For GPIO_11, we will have to ensure that there is an external PD so that the default state is driven low at reset. GPIO_32 should have an external PD as well. Can you please probe the signals from reset to see what they look like? > => FP seems not working if not configuring GPIO_11(reset) to low in early_gpio_table I think we should get the signals probed both with and withou GPIO_11 driven low in early_gpio_table. Driving GPIO_11 low in early_gpio_table will cause FPMCU to not work after S3 resume. -- To view, visit https://review.coreboot.org/c/coreboot/+/52181 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7c56b0db193be6804d07c2f333445c2a1dbf9f59 Gerrit-Change-Number: 52181 Gerrit-PatchSet: 9 Gerrit-Owner: Ivy Jian <ivy_jian(a)compal.corp-partner.google.com> Gerrit-Reviewer: Bhanu Prakash Maiya <bhanumaiya(a)google.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Mathew King <mathewk(a)chromium.org> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Bhanu Prakash Maiya <bhanumaiya(a)google.com> Gerrit-Attention: Ivy Jian <ivy_jian(a)compal.corp-partner.google.com> Gerrit-Attention: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Comment-Date: Fri, 09 Apr 2021 05:14:59 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Furquan Shaikh <furquan(a)google.com> Comment-In-Reply-To: Ivy Jian <ivy_jian(a)compal.corp-partner.google.com> Comment-In-Reply-To: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: [WIP] mb/google/volteer: Update flashmap descriptor to add RW_UCODE_S...
by Jamie Ryu (Code Review) 08 Apr '21

08 Apr '21

Jamie Ryu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46622 ) Change subject: [WIP] mb/google/volteer: Update flashmap descriptor to add RW_UCODE_STAGED ...................................................................... [WIP] mb/google/volteer: Update flashmap descriptor to add RW_UCODE_STAGED This adds RW_UCODE_STAGED to flashmap descriptor to enable microcode update. BUG=b:149547271 TEST=Build and boot volteer2 to OS Signed-off-by: Jamie Ryu <jamie.m.ryu(a)intel.com> Change-Id: I0af7469cc2767cdf5933e65f81686f9edbfa830d --- M src/mainboard/google/volteer/chromeos.fmd 1 file changed, 8 insertions(+), 7 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/22/46622/1 diff --git a/src/mainboard/google/volteer/chromeos.fmd b/src/mainboard/google/volteer/chromeos.fmd index 07a5464..dc0aa9d 100644 --- a/src/mainboard/google/volteer/chromeos.fmd +++ b/src/mainboard/google/volteer/chromeos.fmd @@ -8,17 +8,17 @@ # of BIOS regions start at 16MiB boundary. Since this is a 32MiB # SPI flash only the top 16MiB actually gets memory mapped. RW_LEGACY(CBFS)@0x0 0xb00000 - RW_SECTION_A@0xb00000 0x5e0000 { + RW_SECTION_A@0xb00000 0x5c0000 { VBLOCK_A@0x0 0x10000 - FW_MAIN_A(CBFS)@0x10000 0x5cffc0 - RW_FWID_A@0x5dffc0 0x40 + FW_MAIN_A(CBFS)@0x10000 0x5affc0 + RW_FWID_A@0x5bffc0 0x40 } - RW_SECTION_B@0x10e0000 0x5e0000 { + RW_SECTION_B@0x10c0000 0x5c0000 { VBLOCK_B@0x0 0x10000 - FW_MAIN_B(CBFS)@0x10000 0x5cffc0 - RW_FWID_B@0x5dffc0 0x40 + FW_MAIN_B(CBFS)@0x10000 0x5affc0 + RW_FWID_B@0x5bffc0 0x40 } - RW_MISC@0x16c0000 0x40000 { + RW_MISC@0x1680000 0x80000 { UNIFIED_MRC_CACHE(PRESERVE)@0x0 0x30000 { RECOVERY_MRC_CACHE@0x0 0x10000 RW_MRC_CACHE@0x10000 0x20000 @@ -30,6 +30,7 @@ } RW_VPD(PRESERVE)@0x38000 0x2000 RW_NVRAM(PRESERVE)@0x3a000 0x6000 + RW_UCODE_STAGED@0x40000 0x40000 } # Make WP_RO region align with SPI vendor # memory protected range specification. -- To view, visit https://review.coreboot.org/c/coreboot/+/46622 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0af7469cc2767cdf5933e65f81686f9edbfa830d Gerrit-Change-Number: 46622 Gerrit-PatchSet: 1 Gerrit-Owner: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-MessageType: newchange

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