coreboot-gerrit April 2021

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Change in coreboot[master]: mb/google/mancomb: Add Codec configration
by Patrick Georgi (Code Review) 09 Apr '21

09 Apr '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/52179 ) Change subject: mb/google/mancomb: Add Codec configration ...................................................................... mb/google/mancomb: Add Codec configration Enable I2C2 in devicetree and fill ACPI information for Codec. BUG=b:182211161 TEST=builds Signed-off-by: Eric Lai <ericr_lai(a)compal.corp-partner.google.com> Change-Id: Ib75ef99cbca8b2f38268705704e7616b456f19d9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52179 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Mathew King <mathewk(a)chromium.org> --- M src/mainboard/google/mancomb/variants/mancomb/overridetree.cb 1 file changed, 14 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Mathew King: Looks good to me, approved diff --git a/src/mainboard/google/mancomb/variants/mancomb/overridetree.cb b/src/mainboard/google/mancomb/variants/mancomb/overridetree.cb index 59fe790..891b4eb 100644 --- a/src/mainboard/google/mancomb/variants/mancomb/overridetree.cb +++ b/src/mainboard/google/mancomb/variants/mancomb/overridetree.cb @@ -22,4 +22,18 @@ .early_init = true, }" + device ref i2c_2 on + chip drivers/i2c/generic + register "hid" = ""10EC5682"" + register "name" = ""RT58"" + register "desc" = ""Realtek RT5682"" + register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPIO_90)" + register "property_count" = "1" + register "property_list[0].type" = "ACPI_DP_TYPE_INTEGER" + register "property_list[0].name" = ""realtek,jd-src"" + register "property_list[0].integer" = "1" + device i2c 1a on end + end + end # I2C2 + end # chip soc/amd/cezanne -- To view, visit https://review.coreboot.org/c/coreboot/+/52179 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib75ef99cbca8b2f38268705704e7616b456f19d9 Gerrit-Change-Number: 52179 Gerrit-PatchSet: 2 Gerrit-Owner: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Mathew King <mathewk(a)chromium.org> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/google/mancomb: Add Bluetooth configuration
by Patrick Georgi (Code Review) 09 Apr '21

09 Apr '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/52178 ) Change subject: mb/google/mancomb: Add Bluetooth configuration ...................................................................... mb/google/mancomb: Add Bluetooth configuration Configure the BT disable GPIO to logic low in order to enable Bluetooth. BUG=b:182211161 TEST=builds Signed-off-by: Eric Lai <ericr_lai(a)compal.corp-partner.google.com> Change-Id: I7661dea682cbe0ae5e169d87e794ed6ed3c83b5e Reviewed-on: https://review.coreboot.org/c/coreboot/+/52178 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Mathew King <mathewk(a)chromium.org> --- M src/mainboard/google/mancomb/variants/baseboard/gpio.c 1 file changed, 1 insertion(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Mathew King: Looks good to me, approved diff --git a/src/mainboard/google/mancomb/variants/baseboard/gpio.c b/src/mainboard/google/mancomb/variants/baseboard/gpio.c index 1e39853..f647bec 100644 --- a/src/mainboard/google/mancomb/variants/baseboard/gpio.c +++ b/src/mainboard/google/mancomb/variants/baseboard/gpio.c @@ -142,7 +142,7 @@ /* CLK_REQ3_L */ PAD_NF(GPIO_131, CLK_REQ3_L, PULL_NONE), /* BT_DISABLE */ - PAD_GPO(GPIO_132, HIGH), + PAD_GPO(GPIO_132, LOW), /* EGPIO140 */ PAD_NC(GPIO_140), /* UART0_RXD */ -- To view, visit https://review.coreboot.org/c/coreboot/+/52178 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7661dea682cbe0ae5e169d87e794ed6ed3c83b5e Gerrit-Change-Number: 52178 Gerrit-PatchSet: 2 Gerrit-Owner: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Mathew King <mathewk(a)chromium.org> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/google/mancomb: Update GPIO configuration
by Patrick Georgi (Code Review) 09 Apr '21

09 Apr '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/52177 ) Change subject: mb/google/mancomb: Update GPIO configuration ...................................................................... mb/google/mancomb: Update GPIO configuration BUG=b:182211161 TEST=builds Signed-off-by: Eric Lai <ericr_lai(a)compal.corp-partner.google.com> Change-Id: Ie3917c10ecf37c914dbadce5949b8f4f772abd5c Reviewed-on: https://review.coreboot.org/c/coreboot/+/52177 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Mathew King <mathewk(a)chromium.org> --- M src/mainboard/google/mancomb/variants/baseboard/gpio.c 1 file changed, 11 insertions(+), 3 deletions(-) Approvals: build bot (Jenkins): Verified Mathew King: Looks good to me, approved diff --git a/src/mainboard/google/mancomb/variants/baseboard/gpio.c b/src/mainboard/google/mancomb/variants/baseboard/gpio.c index cd86f9c..1e39853 100644 --- a/src/mainboard/google/mancomb/variants/baseboard/gpio.c +++ b/src/mainboard/google/mancomb/variants/baseboard/gpio.c @@ -53,8 +53,8 @@ /* HUB_RST_L */ PAD_GPO(GPIO_24, LOW), /* GPIO_25: Not available */ - /* PCIE_RST0_L */ - PAD_NF(GPIO_26, PCIE_RST_L, PULL_NONE), + /* TODO: change back to PCIE_RST_L when we figure out why PCIE_RST doesn't go high. */ + PAD_GPO(GPIO_26, HIGH), /* PCIE_RST1_L */ PAD_NF(GPIO_27, PCIE_RST1_L, PULL_NONE), /* GPIO_28: Not available */ @@ -93,7 +93,7 @@ PAD_GPI(GPIO_84, PULL_NONE), /* AGPIO85 */ PAD_NC(GPIO_85), - /* SPI_CLK2 */ + /* ESPI_SOC_CLK */ PAD_NF(GPIO_86, SPI_CLK, PULL_NONE), /* AGPIO87 */ PAD_NC(GPIO_87), @@ -116,6 +116,8 @@ PAD_NF(GPIO_106, EMMC_SPI2_WP_L_ESPI2_D2, PULL_NONE), /* ESPI1_DATA3 */ PAD_NF(GPIO_107, SPI2_HOLD_L_ESPI2_D3, PULL_NONE), + /* ESPI_ALERT_L */ + PAD_NF(GPIO_108, ESPI_ALERT_D1, PULL_NONE), /* EGPIO109 */ PAD_NC(GPIO_109), /* GPIO_110 - GPIO_112: Not available */ @@ -169,6 +171,12 @@ PAD_NF(GPIO_19, I2C3_SCL, PULL_NONE), /* I2C3_SDA */ PAD_NF(GPIO_20, I2C3_SDA, PULL_NONE), + /* PCIE_RST0_L */ + PAD_GPO(GPIO_26, HIGH), + /* ESPI_CS_L */ + PAD_NF(GPIO_30, ESPI_CS_L, PULL_NONE), + /* ESPI_SOC_CLK */ + PAD_NF(GPIO_86, SPI_CLK, PULL_NONE), /* ESPI1_DATA0 */ PAD_NF(GPIO_104, SPI2_DO_ESPI2_D0, PULL_NONE), /* ESPI1_DATA1 */ -- To view, visit https://review.coreboot.org/c/coreboot/+/52177 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie3917c10ecf37c914dbadce5949b8f4f772abd5c Gerrit-Change-Number: 52177 Gerrit-PatchSet: 2 Gerrit-Owner: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Mathew King <mathewk(a)chromium.org> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/google/mancomb: Enable AP <-> H1 communication
by Patrick Georgi (Code Review) 09 Apr '21

09 Apr '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/52175 ) Change subject: mb/google/mancomb: Enable AP <-> H1 communication ...................................................................... mb/google/mancomb: Enable AP <-> H1 communication BUG=b:182211161 TEST=builds Signed-off-by: Eric Lai <ericr_lai(a)compal.corp-partner.google.com> Change-Id: I29be8572bc7bb366347eabe553be49775dec46a8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52175 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Mathew King <mathewk(a)chromium.org> --- M src/mainboard/google/mancomb/Kconfig M src/mainboard/google/mancomb/variants/baseboard/devicetree.cb M src/mainboard/google/mancomb/variants/baseboard/gpio.c 3 files changed, 24 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Mathew King: Looks good to me, approved diff --git a/src/mainboard/google/mancomb/Kconfig b/src/mainboard/google/mancomb/Kconfig index 85a50b3..5851e5c 100644 --- a/src/mainboard/google/mancomb/Kconfig +++ b/src/mainboard/google/mancomb/Kconfig @@ -20,6 +20,8 @@ select ELOG_GSMI select HAVE_ACPI_RESUME select MAINBOARD_HAS_CHROMEOS + select MAINBOARD_HAS_I2C_TPM_CR50 + select MAINBOARD_HAS_TPM2 select SOC_AMD_CEZANNE select SOC_AMD_COMMON_BLOCK_USE_ESPI @@ -49,6 +51,14 @@ help TODO: might need to be adapted for better placement of files in cbfs +config DRIVER_TPM_I2C_BUS + hex + default 0x03 + +config DRIVER_TPM_I2C_ADDR + hex + default 0x50 + config VARIANT_DIR string default "mancomb" if BOARD_GOOGLE_MANCOMB diff --git a/src/mainboard/google/mancomb/variants/baseboard/devicetree.cb b/src/mainboard/google/mancomb/variants/baseboard/devicetree.cb index 533e2b4..0a604a3 100644 --- a/src/mainboard/google/mancomb/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/mancomb/variants/baseboard/devicetree.cb @@ -121,5 +121,13 @@ device pnp 0c09.0 on end end end + device ref i2c_3 on + chip drivers/i2c/tpm + register "hid" = ""GOOG0005"" + register "desc" = ""Cr50 TPM"" + register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_LOW(GPIO_3)" + device i2c 50 on end + end + end end # domain end # chip soc/amd/cezanne diff --git a/src/mainboard/google/mancomb/variants/baseboard/gpio.c b/src/mainboard/google/mancomb/variants/baseboard/gpio.c index bcca693c..cd86f9c 100644 --- a/src/mainboard/google/mancomb/variants/baseboard/gpio.c +++ b/src/mainboard/google/mancomb/variants/baseboard/gpio.c @@ -163,6 +163,12 @@ /* Early GPIO configuration */ static const struct soc_amd_gpio early_gpio_table[] = { + /* GSC_SOC_INT_L */ + PAD_INT(GPIO_3, PULL_NONE, EDGE_LOW, STATUS_DELIVERY), + /* I2C3_SCL */ + PAD_NF(GPIO_19, I2C3_SCL, PULL_NONE), + /* I2C3_SDA */ + PAD_NF(GPIO_20, I2C3_SDA, PULL_NONE), /* ESPI1_DATA0 */ PAD_NF(GPIO_104, SPI2_DO_ESPI2_D0, PULL_NONE), /* ESPI1_DATA1 */ -- To view, visit https://review.coreboot.org/c/coreboot/+/52175 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I29be8572bc7bb366347eabe553be49775dec46a8 Gerrit-Change-Number: 52175 Gerrit-PatchSet: 2 Gerrit-Owner: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Mathew King <mathewk(a)chromium.org> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/google/mancomb: Add initial I2C configuration
by Patrick Georgi (Code Review) 09 Apr '21

09 Apr '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/52174 ) Change subject: mb/google/mancomb: Add initial I2C configuration ...................................................................... mb/google/mancomb: Add initial I2C configuration BUG=b:182211161 TEST=builds Signed-off-by: Eric Lai <ericr_lai(a)compal.corp-partner.google.com> Change-Id: I483c2e77eedcb434709b67bf9b3fbca636499508 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52174 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Mathew King <mathewk(a)chromium.org> --- M src/mainboard/google/mancomb/Kconfig M src/mainboard/google/mancomb/variants/baseboard/devicetree.cb M src/mainboard/google/mancomb/variants/mancomb/overridetree.cb 3 files changed, 26 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Mathew King: Looks good to me, approved diff --git a/src/mainboard/google/mancomb/Kconfig b/src/mainboard/google/mancomb/Kconfig index b681a1e..85a50b3 100644 --- a/src/mainboard/google/mancomb/Kconfig +++ b/src/mainboard/google/mancomb/Kconfig @@ -10,6 +10,8 @@ select AMD_SOC_CONSOLE_UART select BOARD_ROMSIZE_KB_16384 select DISABLE_SPI_FLASH_ROM_SHARING + select DRIVERS_I2C_GENERIC + select DRIVERS_I2C_HID select EC_GOOGLE_CHROMEEC select EC_GOOGLE_CHROMEEC_BOARDID select EC_GOOGLE_CHROMEEC_ESPI diff --git a/src/mainboard/google/mancomb/variants/baseboard/devicetree.cb b/src/mainboard/google/mancomb/variants/baseboard/devicetree.cb index b368574..533e2b4 100644 --- a/src/mainboard/google/mancomb/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/mancomb/variants/baseboard/devicetree.cb @@ -38,6 +38,9 @@ .vw_irq_polarity = ESPI_VW_IRQ_LEVEL_HIGH(1) | ESPI_VW_IRQ_LEVEL_HIGH(12), }" + register "i2c_scl_reset" = "GPIO_I2C0_SCL | GPIO_I2C1_SCL | + GPIO_I2C2_SCL | GPIO_I2C3_SCL" + device domain 0 on device ref gpp_bridge_0 on end # WLAN device ref gpp_bridge_1 on end # SD diff --git a/src/mainboard/google/mancomb/variants/mancomb/overridetree.cb b/src/mainboard/google/mancomb/variants/mancomb/overridetree.cb index eae9425..59fe790 100644 --- a/src/mainboard/google/mancomb/variants/mancomb/overridetree.cb +++ b/src/mainboard/google/mancomb/variants/mancomb/overridetree.cb @@ -1,4 +1,25 @@ chip soc/amd/cezanne device domain 0 on end # domain + + # I2C Config + #+-------------------+---------------------------+ + #| Field | Value | + #+-------------------+---------------------------+ + #| I2C0 | memory SPD bus | + #| I2C2 | Codec | + #| I2C3 | H1/D2 TPM | + #+-------------------+---------------------------+ + register "i2c[0]" = "{ + .speed = I2C_SPEED_FAST, + .early_init = true, + }" + register "i2c[2]" = "{ + .speed = I2C_SPEED_FAST, + }" + register "i2c[3]" = "{ + .speed = I2C_SPEED_FAST, + .early_init = true, + }" + end # chip soc/amd/cezanne -- To view, visit https://review.coreboot.org/c/coreboot/+/52174 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I483c2e77eedcb434709b67bf9b3fbca636499508 Gerrit-Change-Number: 52174 Gerrit-PatchSet: 2 Gerrit-Owner: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Mathew King <mathewk(a)chromium.org> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/google/dedede/var/boten: Configure Acoustic noise mitigation UPDs
by Patrick Georgi (Code Review) 09 Apr '21

09 Apr '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/52135 ) Change subject: mb/google/dedede/var/boten: Configure Acoustic noise mitigation UPDs ...................................................................... mb/google/dedede/var/boten: Configure Acoustic noise mitigation UPDs Enable Acoustic noise mitigation for boten and set slew rate to 1/8 which is calibrated value for the board. BUG=b:180668001 BRANCH=dedede TEST=build firmware to UPD and Acoustic noise test Change-Id: I75851bd7c279feeab4ab94f4c82d55bf0e5ce316 Signed-off-by: Stanley Wu <stanley1.wu(a)lcfc.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52135 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub(a)google.com> --- M src/mainboard/google/dedede/variants/boten/overridetree.cb 1 file changed, 6 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Karthik Ramasubramanian: Looks good to me, approved diff --git a/src/mainboard/google/dedede/variants/boten/overridetree.cb b/src/mainboard/google/dedede/variants/boten/overridetree.cb index 34044ff..f914b82 100644 --- a/src/mainboard/google/dedede/variants/boten/overridetree.cb +++ b/src/mainboard/google/dedede/variants/boten/overridetree.cb @@ -74,6 +74,12 @@ [PchSerialIoIndexI2C5] = PchSerialIoPci, }" + # Enable Acoustic noise mitigation and set slew rate to 1/8 + # Rest of the parameters are 0 by default. + register "AcousticNoiseMitigation" = "1" + register "SlowSlewRate" = "SlewRateFastBy8" + register "FastPkgCRampDisable" = "1" + device domain 0 on device pci 04.0 on chip drivers/intel/dptf -- To view, visit https://review.coreboot.org/c/coreboot/+/52135 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I75851bd7c279feeab4ab94f4c82d55bf0e5ce316 Gerrit-Change-Number: 52135 Gerrit-PatchSet: 2 Gerrit-Owner: Stanley Wu <stanley1.wu(a)lcfc.corp-partner.google.com> Gerrit-Reviewer: Henry Sun <henrysun(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Fagerburg <pfagerburg(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Allen Cheng <allen.cheng(a)lcfc.corp-partner.google.com> Gerrit-CC: Kevin Chang <kevin.chang(a)lcfc.corp-partner.google.com> Gerrit-CC: Melo Chuang <melo.chuang(a)lcfc.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-CC: Rasheed Hsueh <rasheed.hsueh(a)lcfc.corp-partner.google.com> Gerrit-CC: Sunshine Chao <sunshine.chao(a)lcfc.corp-partner.google.com> Gerrit-MessageType: merged

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Change in coreboot[master]: drivers/tpm/Kconfig: Rename TPM_INIT to TPM_INIT_RAMSTAGE
by Patrick Georgi (Code Review) 09 Apr '21

09 Apr '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/52133 ) Change subject: drivers/tpm/Kconfig: Rename TPM_INIT to TPM_INIT_RAMSTAGE ...................................................................... drivers/tpm/Kconfig: Rename TPM_INIT to TPM_INIT_RAMSTAGE Rename the Kconfig parameter to more accurately reflect what it does. TPM can be initialised in a different stage too, for instance with VBOOT it is done in verstage. Change-Id: Ic0126b356e8430c04c7c9fd46d4e20022a648738 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52133 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Frans Hendriks <fhendriks(a)eltan.com> --- M src/drivers/tpm/Kconfig M src/drivers/tpm/Makefile.inc M src/mainboard/facebook/fbg1701/Kconfig 3 files changed, 3 insertions(+), 3 deletions(-) Approvals: build bot (Jenkins): Verified Frans Hendriks: Looks good to me, approved diff --git a/src/drivers/tpm/Kconfig b/src/drivers/tpm/Kconfig index d8a1e10..128f9bf 100644 --- a/src/drivers/tpm/Kconfig +++ b/src/drivers/tpm/Kconfig @@ -1,4 +1,4 @@ -config TPM_INIT +config TPM_INIT_RAMSTAGE bool default y if TPM1 || TPM2 depends on !VBOOT && !VENDORCODE_ELTAN_VBOOT && !VENDORCODE_ELTAN_MBOOT diff --git a/src/drivers/tpm/Makefile.inc b/src/drivers/tpm/Makefile.inc index af6e5a21..9833eb4 100644 --- a/src/drivers/tpm/Makefile.inc +++ b/src/drivers/tpm/Makefile.inc @@ -1,4 +1,4 @@ -ramstage-$(CONFIG_TPM_INIT) += tpm.c +ramstage-$(CONFIG_TPM_INIT_RAMSTAGE) += tpm.c ifeq ($(CONFIG_TPM_PPI),y) ramstage-$(CONFIG_HAVE_ACPI_TABLES) += ppi.c diff --git a/src/mainboard/facebook/fbg1701/Kconfig b/src/mainboard/facebook/fbg1701/Kconfig index 1c47247..40cf8d9 100644 --- a/src/mainboard/facebook/fbg1701/Kconfig +++ b/src/mainboard/facebook/fbg1701/Kconfig @@ -87,7 +87,7 @@ bool default y -config TPM_INIT +config TPM_INIT_RAMSTAGE bool "TPM Setup in RAMSTAGE" default n -- To view, visit https://review.coreboot.org/c/coreboot/+/52133 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic0126b356e8430c04c7c9fd46d4e20022a648738 Gerrit-Change-Number: 52133 Gerrit-PatchSet: 3 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Wim Vervoorn <wvervoorn(a)eltan.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: include/assert.h: Use mock_assert() for ENV_TEST targets
by Patrick Georgi (Code Review) 09 Apr '21

09 Apr '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/51804 ) Change subject: include/assert.h: Use mock_assert() for ENV_TEST targets ...................................................................... include/assert.h: Use mock_assert() for ENV_TEST targets Some tests have to be able to catch assertion errors. Adding CMocka mock_assert() enables that. Additionally fix test_imd_create_tiered_empty(), test_full_stack() and test_incorrectly_initialized_stack() by adding missing expect_assert_failure(). Signed-off-by: Jakub Czapiga <jacz(a)semihalf.com> Change-Id: I5e8dd1b198ee6fab61e2be3f92baf1178f79bf18 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51804 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Paul Fagerburg <pfagerburg(a)chromium.org> --- M src/include/assert.h M tests/lib/imd-test.c M tests/lib/stack-test.c 3 files changed, 20 insertions(+), 5 deletions(-) Approvals: build bot (Jenkins): Verified Paul Fagerburg: Looks good to me, approved diff --git a/src/include/assert.h b/src/include/assert.h index 944c677..829e732 100644 --- a/src/include/assert.h +++ b/src/include/assert.h @@ -29,12 +29,24 @@ #define __build_time_assert(x) 0 #endif +/* CMocka function redefinition. */ +void mock_assert(const int result, const char *const expression, + const char *const file, const int line); + +#if ENV_TEST +#define MOCK_ASSERT(result, expression) \ + mock_assert((result), (expression), __ASSERT_FILE__, __ASSERT_LINE__) +#else +#define MOCK_ASSERT(result, expression) +#endif + /* GCC and CAR versions */ #define ASSERT(x) { \ if (!__build_time_assert(x) && !(x)) { \ printk(BIOS_EMERG, \ "ASSERTION ERROR: file '%s', line %d\n", \ __ASSERT_FILE__, __ASSERT_LINE__); \ + MOCK_ASSERT(!!(x), #x); \ if (CONFIG(FATAL_ASSERTS)) \ hlt(); \ } \ @@ -45,6 +57,7 @@ "ASSERTION ERROR: file '%s', line %d\n", \ __ASSERT_FILE__, __ASSERT_LINE__); \ printk(BIOS_EMERG, "%s", msg); \ + MOCK_ASSERT(!!(x), (msg)); \ if (CONFIG(FATAL_ASSERTS)) \ hlt(); \ } \ @@ -53,6 +66,7 @@ printk(BIOS_EMERG, \ "ERROR: BUG ENCOUNTERED at file '%s', line %d\n", \ __ASSERT_FILE__, __ASSERT_LINE__); \ + MOCK_ASSERT(0, "BUG ENCOUNTERED"); \ if (CONFIG(FATAL_ASSERTS)) \ hlt(); \ } diff --git a/tests/lib/imd-test.c b/tests/lib/imd-test.c index dce542c..c2bcf0c 100644 --- a/tests/lib/imd-test.c +++ b/tests/lib/imd-test.c @@ -176,9 +176,10 @@ /* Fail when large region doesn't have capacity for more than 1 entry */ lg_region_wrong_size = sizeof(struct imd_root_pointer) + sizeof(struct imd_root) + sizeof(struct imd_entry); - assert_int_equal(-1, imd_create_tiered_empty(&imd, lg_region_wrong_size, - LG_ENTRY_ALIGN, SM_ROOT_SIZE, - SM_ENTRY_ALIGN)); + expect_assert_failure( + imd_create_tiered_empty(&imd, lg_region_wrong_size, LG_ENTRY_ALIGN, + SM_ROOT_SIZE, SM_ENTRY_ALIGN) + ); assert_int_equal(0, imd_create_tiered_empty(&imd, LG_ROOT_SIZE, LG_ENTRY_ALIGN, SM_ROOT_SIZE, SM_ENTRY_ALIGN)); diff --git a/tests/lib/stack-test.c b/tests/lib/stack-test.c index f494c08..bed59aa 100644 --- a/tests/lib/stack-test.c +++ b/tests/lib/stack-test.c @@ -73,7 +73,7 @@ /* Expect failure when checking full stack as absence of guard value at the end of the stack indicates stack overrun. */ - assert_int_equal(-1, checkstack(top_of_stack, 0)); + expect_assert_failure(checkstack(top_of_stack, 0)); } static void test_partialy_filled_stack(void **state) @@ -115,7 +115,7 @@ /* Expect failure when there is no last stack guard value even if no other value was changed. */ - assert_int_equal(-1, checkstack(top_of_stack, 0)); + expect_assert_failure(checkstack(top_of_stack, 0)); } int main(void) -- To view, visit https://review.coreboot.org/c/coreboot/+/51804 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5e8dd1b198ee6fab61e2be3f92baf1178f79bf18 Gerrit-Change-Number: 51804 Gerrit-PatchSet: 5 Gerrit-Owner: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: Jan Dabros <jsd(a)semihalf.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Fagerburg <pfagerburg(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: merged

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Change in coreboot[master]: drivers/mrc_cache: Fix with VBOOT & VBOOT_STARTS_IN_ROMSTAGE
by Patrick Georgi (Code Review) 09 Apr '21

09 Apr '21

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/52157 ) Change subject: drivers/mrc_cache: Fix with VBOOT & VBOOT_STARTS_IN_ROMSTAGE ...................................................................... drivers/mrc_cache: Fix with VBOOT & VBOOT_STARTS_IN_ROMSTAGE This guards code accessing the vboot context which does not exist if vboot starts after romstage. Change-Id: I2a38daa00d6d18df9c5e22858530814e23bb3e00 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52157 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Frans Hendriks <fhendriks(a)eltan.com> --- M src/drivers/mrc_cache/mrc_cache.c 1 file changed, 2 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Frans Hendriks: Looks good to me, approved diff --git a/src/drivers/mrc_cache/mrc_cache.c b/src/drivers/mrc_cache/mrc_cache.c index 8b26ea5..f97031d 100644 --- a/src/drivers/mrc_cache/mrc_cache.c +++ b/src/drivers/mrc_cache/mrc_cache.c @@ -285,7 +285,8 @@ * In recovery mode, force retraining if the memory retrain * switch is set. */ - if (vboot_recovery_mode_enabled() && get_recovery_mode_retrain_switch()) + if (CONFIG(VBOOT_STARTS_IN_BOOTBLOCK) && vboot_recovery_mode_enabled() + && get_recovery_mode_retrain_switch()) return -1; cr = lookup_region(&region, type); -- To view, visit https://review.coreboot.org/c/coreboot/+/52157 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2a38daa00d6d18df9c5e22858530814e23bb3e00 Gerrit-Change-Number: 52157 Gerrit-PatchSet: 2 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/ocp/deltalake: Override DDR frequency limit via VPD variable
by Tim Chu (Code Review) 09 Apr '21

09 Apr '21

Tim Chu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48946 ) Change subject: mb/ocp/deltalake: Override DDR frequency limit via VPD variable ...................................................................... mb/ocp/deltalake: Override DDR frequency limit via VPD variable Use VPD variable "fsp_dimm_freq" to select DDR frequency limit. Tested=On OCP Delta Lake, DDR frequency limit can be changed via VPD. Signed-off-by: Tim Chu <Tim.Chu(a)quantatw.com> Change-Id: I1232feae5090420d8fa42596b46f2d4dcaf9d635 --- M src/mainboard/ocp/deltalake/romstage.c M src/mainboard/ocp/deltalake/vpd.h 2 files changed, 26 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/46/48946/1 diff --git a/src/mainboard/ocp/deltalake/romstage.c b/src/mainboard/ocp/deltalake/romstage.c index f0cdd3d..58ee968 100644 --- a/src/mainboard/ocp/deltalake/romstage.c +++ b/src/mainboard/ocp/deltalake/romstage.c @@ -75,6 +75,28 @@ printk(BIOS_DEBUG, "Setting MemRefreshWatermark %d from VPD\n", val); mupd->FspmConfig.UnusedUpdSpace0[0] = val; } + + /* + * Select DDR Frequency Limit + * 0x0:Auto, 0x5:DDR_1333, 0x7:DDR_1600, 0x9:DDR_1866, 0xb:DDR_2133, 0xd:DDR_2400, + * 0xf:DDR_2666, 0x11:DDR_2933, 0x13:DDR_3200 + */ + static const unsigned int limit[] = { 0x0, 0x5, 0x7, 0x9, 0xb, 0xd, 0xf, 0x11, 0x13}; + if (vpd_gets(FSP_DIMM_FREQ, val_str, VPD_LEN, VPD_RW_THEN_RO)) { + val = (uint8_t)atol(val_str); + if (val > 8) { + printk(BIOS_DEBUG, "Invalid DdrFreqLimit value from VPD: " + "%d\n", val); + val = FSP_DIMM_FREQ_DEFAULT; + } + printk(BIOS_DEBUG, "Setting DdrFreqLimit %d from VPD\n", val); + mupd->FspmConfig.DdrFreqLimit = limit[val]; + } else { + printk(BIOS_INFO, "Not able to get VPD %s, default set " + "DebugPrintLevel to %d\n", FSP_DIMM_FREQ, + FSP_DIMM_FREQ_DEFAULT); + mupd->FspmConfig.DdrFreqLimit = limit[FSP_DIMM_FREQ_DEFAULT]; + } } /* Update bifurcation settings according to different Configs */ diff --git a/src/mainboard/ocp/deltalake/vpd.h b/src/mainboard/ocp/deltalake/vpd.h index 71a3b09..9246fb0 100644 --- a/src/mainboard/ocp/deltalake/vpd.h +++ b/src/mainboard/ocp/deltalake/vpd.h @@ -40,4 +40,8 @@ #define FSPM_MEMREFRESHWATERMARK "fspm_mem_refresh_watermark" #define FSPM_MEMREFRESHWATERMARK_DEFAULT 1 +/* FSP dimm frequency limit, 0:Auto, 1:DDR_1333, 2:DDR_1600, 3:DDR_1866, 4:DDR_2133, 5:DDR_2400, 6:DDR_2666, 7:DDR_2933, 8:DDR_3200 */ +#define FSP_DIMM_FREQ "fsp_dimm_freq" +#define FSP_DIMM_FREQ_DEFAULT 0 + #endif -- To view, visit https://review.coreboot.org/c/coreboot/+/48946 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1232feae5090420d8fa42596b46f2d4dcaf9d635 Gerrit-Change-Number: 48946 Gerrit-PatchSet: 1 Gerrit-Owner: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-MessageType: newchange

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