Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/50795 )
Change subject: soc/intel/common/block/hda: Use azalia device code
......................................................................
soc/intel/common/block/hda: Use azalia device code
The code is already compiled in on all platforms. Use it as it provides
the same functionality. Note that GCAP is no longer R/WO on these
platforms. However, select `AZALIA_LOCK_DOWN_R_WO_GCAP` just in case.
This will be dropped in a follow-up.
Tested on Prodrive Hermes, still detects and initializes both codecs.
Change-Id: I75424559b2b4aca63fb23bf4f8d5074aa1e1bb31
Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50795
Reviewed-by: Christian Walter <christian.walter(a)9elements.com>
Reviewed-by: Angel Pons <th3fanbus(a)gmail.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org>
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
---
M src/soc/intel/common/block/hda/Kconfig
M src/soc/intel/common/block/hda/hda.c
2 files changed, 6 insertions(+), 39 deletions(-)
Approvals:
build bot (Jenkins): Verified
Angel Pons: Looks good to me, but someone else must approve
Tim Wawrzynczak: Looks good to me, approved
Christian Walter: Looks good to me, approved
diff --git a/src/soc/intel/common/block/hda/Kconfig b/src/soc/intel/common/block/hda/Kconfig
index a2209ab..a01ede4 100644
--- a/src/soc/intel/common/block/hda/Kconfig
+++ b/src/soc/intel/common/block/hda/Kconfig
@@ -6,5 +6,9 @@
config SOC_INTEL_COMMON_BLOCK_HDA_VERB
bool
depends on SOC_INTEL_COMMON_BLOCK_HDA
+ select AZALIA_LOCK_DOWN_R_WO_GCAP
help
Enable initialization of HDA codecs.
+
+config AZALIA_MAX_CODECS
+ default 4 if SOC_INTEL_COMMON_BLOCK_HDA_VERB
diff --git a/src/soc/intel/common/block/hda/hda.c b/src/soc/intel/common/block/hda/hda.c
index ece06ca..3aa2ad7 100644
--- a/src/soc/intel/common/block/hda/hda.c
+++ b/src/soc/intel/common/block/hda/hda.c
@@ -1,58 +1,21 @@
/* SPDX-License-Identifier: GPL-2.0-only */
-#include <console/console.h>
#include <device/device.h>
#include <device/azalia_device.h>
#include <device/pci.h>
#include <device/pci_ids.h>
-#include <soc/intel/common/hda_verb.h>
-#include <soc/ramstage.h>
-
-#if CONFIG(SOC_INTEL_COMMON_BLOCK_HDA_VERB)
-static void codecs_init(uint8_t *base, u32 codec_mask)
-{
- int i;
-
- /* Can support up to 4 codecs */
- for (i = 3; i >= 0; i--) {
- if (codec_mask & (1 << i))
- hda_codec_init(base, i,
- cim_verb_data_size, cim_verb_data);
- }
-
- if (pc_beep_verbs_size)
- hda_codec_write(base, pc_beep_verbs_size, pc_beep_verbs);
-}
static void hda_init(struct device *dev)
{
- struct resource *res;
- int codec_mask;
- uint8_t *base;
-
- res = find_resource(dev, PCI_BASE_ADDRESS_0);
- if (!res)
- return;
-
- base = res2mmio(res, 0, 0);
- if (!base)
- return;
-
- codec_mask = hda_codec_detect(base);
- if (codec_mask) {
- printk(BIOS_INFO, "HDA: codec_mask = %02x\n", codec_mask);
- codecs_init(base, codec_mask);
- }
+ if (CONFIG(SOC_INTEL_COMMON_BLOCK_HDA_VERB))
+ azalia_audio_init(dev);
}
-#endif
static struct device_operations hda_ops = {
.read_resources = pci_dev_read_resources,
.set_resources = pci_dev_set_resources,
.enable_resources = pci_dev_enable_resources,
-#if CONFIG(SOC_INTEL_COMMON_BLOCK_HDA_VERB)
.init = hda_init,
-#endif
.ops_pci = &pci_dev_ops_pci,
.scan_bus = scan_static_bus
};
--
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Jonathan Zhang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/52735 )
Change subject: doc/relnotes/4.14: add Intel Xeon-SP support status change
......................................................................
doc/relnotes/4.14: add Intel Xeon-SP support status change
Signed-off-by: Jonathan Zhang <jonzhang(a)fb.com>
Change-Id: Ibead1c75bb4e41fedc2799366b5b006d76fc8f4e
---
M Documentation/releases/coreboot-4.14-relnotes.md
1 file changed, 24 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/35/52735/1
diff --git a/Documentation/releases/coreboot-4.14-relnotes.md b/Documentation/releases/coreboot-4.14-relnotes.md
index e383c2e..d36ea63 100644
--- a/Documentation/releases/coreboot-4.14-relnotes.md
+++ b/Documentation/releases/coreboot-4.14-relnotes.md
@@ -52,4 +52,28 @@
Significant changes
-------------------
+### Intel Xeon Sacalable Processor support became mature
+
+Intel Xeon Scalable Processor (Xeon-SP) family [1] is designed
+primarily to serve the needs of server market.
+
+coreboot support for Xeon-SP is in src/soc/intel/xeon_sp directory.
+This release has support for SkyLake-SP (SKX-SP) which is the 2nd
+generation, and for CooperLake-SP (CPX-SP) which is the 3rd generation
+or the latest generation [2] on market.
+
+With this release, the codebase for multiple generations of Xeon-SP
+were unified and optimized:
+* SKX-SP soc code is used in OCP TiogaPass mainboard [3]. Support for
+this board is in Proof Of Concept Status.
+* CPX-SP soc code is used in OCP DeltaLake mainboard. Support for
+this board is in DVT (Design Validation Test) exit equivalent status.
+Features supported, (performance/stability) test scopes, known issues,
+features gaps are described in [4].
+
### Add significant changes here
+
+[1] https://www.intel.in/content/www/in/en/products/details/processors/xeon/sca…
+[2] https://www.intel.in/content/www/in/en/products/docs/processors/xeon/3rd-ge…
+[3] https://doc.coreboot.org/mainboard/ocp/tiogapass.html
+[4] https://doc.coreboot.org/mainboard/ocp/deltalake.html
--
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Attention is currently required from: Anjaneya "Reddy" Chagam, Jonathan Zhang, David Hendricks, Stefan Reinauer, Angel Pons, Subrata Banik.
Hello Lance Zhao, build bot (Jenkins), Anjaneya "Reddy" Chagam, David Hendricks, Stefan Reinauer, Angel Pons, Subrata Banik,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/52047
to look at the new patch set (#5).
Change subject: src/acpi: Add initial support for HMAT
......................................................................
src/acpi: Add initial support for HMAT
Add initial HMAT (Heterogeneous Memory Attribute Table) support based
on ACPI spec 6.4 section 5.2.27.
Add functions to create HMAT table (revision 2) and create HMAT Memory
Proximity Domain Attribute (MPDA) Structure.
TESTED=Simulated HMAT table creation on OCP DeltaLake server, dumped
the HMAT table and exmained the content. HMAT table and one MPDA
structure are added.
OCP Delatake server is based on Intel CooperLake Scalable Processor
which does not support CXL (Compute Express Link). Therefore solution
level testing is not done.
Signed-off-by: Jonathan Zhang <jonzhang(a)fb.com>
Change-Id: I5ee60ff990c3cea799c5cbdf7eead818b1bb4f9b
---
M src/acpi/acpi.c
M src/include/acpi/acpi.h
2 files changed, 119 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/47/52047/5
--
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Anil Kumar K has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52681 )
Change subject: mb/intel/adlrvp: Set SKUID for adlrvp to 255
......................................................................
Patch Set 1:
(1 comment)
Patchset:
PS1:
> Correct. If you adjust the value in your model. […]
@Nathan. What do u suggest ? Could u provide a change for model.yaml to remove SKU ID . Once we test the change to work i will abandon this patch .
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Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52649 )
Change subject: soc/amd/cezanne: Update STAPM vars with units
......................................................................
Patch Set 3: Code-Review+1
(1 comment)
File src/soc/amd/cezanne/chip.h:
https://review.coreboot.org/c/coreboot/+/52649/comment/371f216c_a723da31
PS2, Line 57: W
> Same as the comment in the previous patch. […]
i'd keep the mixed case here to have the correct spelling of the units, but don't have a too strong opinion on this
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Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/52671 )
Change subject: superio/nuvoton/npcd378: Fall back to non-negative value
......................................................................
superio/nuvoton/npcd378: Fall back to non-negative value
This change is needed to update the option API to use unsigned integers.
The CMOS option system does not support negative numbers. So, adjust the
call to get_int_option() to use 3 as fallback instead of -1.
Change-Id: I46c5f5c6f47f99379cbafc0d60258b99dc512e9d
Signed-off-by: Angel Pons <th3fanbus(a)gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52671
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
Reviewed-by: Patrick Rudolph <siro(a)das-labor.org>
Reviewed-by: Nico Huber <nico.h(a)gmx.de>
---
M src/superio/nuvoton/npcd378/superio.c
1 file changed, 2 insertions(+), 2 deletions(-)
Approvals:
build bot (Jenkins): Verified
Nico Huber: Looks good to me, approved
Patrick Rudolph: Looks good to me, approved
diff --git a/src/superio/nuvoton/npcd378/superio.c b/src/superio/nuvoton/npcd378/superio.c
index 6a56ac8..3645832 100644
--- a/src/superio/nuvoton/npcd378/superio.c
+++ b/src/superio/nuvoton/npcd378/superio.c
@@ -68,8 +68,8 @@
npcd378_hwm_write_start(res->base);
- int fan_lvl = get_int_option("psu_fan_lvl", -1);
- if (fan_lvl < 0 || fan_lvl > 7)
+ unsigned int fan_lvl = get_int_option("psu_fan_lvl", 3);
+ if (fan_lvl > 7)
fan_lvl = 3;
uint8_t pwm = NPCD378_HWM_PSU_FAN_MIN +
--
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