coreboot-gerrit April 2021

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: sc7280: Add GSI FW download support
by build bot (Jenkins) (Code Review) 29 Apr '21

29 Apr '21

Attention is currently required from: Ravi kumar, Martin Roth. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52371 ) Change subject: sc7280: Add GSI FW download support ...................................................................... Patch Set 4: (11 comments) File src/soc/qualcomm/sc7280/include/soc/qupv3_config.h: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-117959): https://review.coreboot.org/c/coreboot/+/52371/comment/6e34aa83_db1b1bc6 PS4, Line 77: { open brace '{' following struct go on the same line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-117959): https://review.coreboot.org/c/coreboot/+/52371/comment/f346c9f6_0cc9da16 PS4, Line 79: uint32_t iram_dword1; /* word 1 of a single IRAM firmware entry */ please, no space before tabs Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-117959): https://review.coreboot.org/c/coreboot/+/52371/comment/de79dccc_1c34022b PS4, Line 83: { open brace '{' following struct go on the same line File src/soc/qualcomm/sc7280/qupv3_config.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-117959): https://review.coreboot.org/c/coreboot/+/52371/comment/ed4c1147_9b9d4cdd PS4, Line 204: write32(&regs->gsi_periph_base_lsb,0); space required after that ',' (ctx:VxV) Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-117959): https://review.coreboot.org/c/coreboot/+/52371/comment/e8b0852e_40e9e201 PS4, Line 205: write32(&regs->gsi_periph_base_msb,0); space required after that ',' (ctx:VxV) Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-117959): https://review.coreboot.org/c/coreboot/+/52371/comment/7ea3f8dd_7465461a PS4, Line 210: if (fwIep[i].offset < GSI_REG_BASE_SIZE) { braces {} are not necessary for single statement blocks Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-117959): https://review.coreboot.org/c/coreboot/+/52371/comment/d7664948_94e43995 PS4, Line 221: memcpy((&regs->gsi_inst_ramn),(void *)fwIRam, space required after that ',' (ctx:VxV) Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-117959): https://review.coreboot.org/c/coreboot/+/52371/comment/04ec83a6_3af82718 PS4, Line 223: setbits_le32(&regs->gsi_mcs_cfg, GSI_MCS_CFG_MCS_ENABLE_BMSK ); space prohibited before that close parenthesis ')' Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-117959): https://review.coreboot.org/c/coreboot/+/52371/comment/33a8f5f2_88015834 PS4, Line 224: setbits_le32(&regs->gsi_cfg, GSI_CFG_DOUBLE_MCS_CLK_FREQ_BMSK | GSI_CFG_GSI_ENABLE_BMSK); line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-117959): https://review.coreboot.org/c/coreboot/+/52371/comment/22cd0127_5359661c PS4, Line 226: write32(&regs->gsi_ee_n_scratch_0_addr,0x0); space required after that ',' (ctx:VxV) Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-117959): https://review.coreboot.org/c/coreboot/+/52371/comment/d03950b3_3e2f6f44 PS4, Line 227: write32(&regs->ee_n_gsi_ee_generic_cmd,0x81); space required after that ',' (ctx:VxV) -- To view, visit https://review.coreboot.org/c/coreboot/+/52371 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8b966a6a074fc43c62d2639da9cf68b083cc7319 Gerrit-Change-Number: 52371 Gerrit-PatchSet: 4 Gerrit-Owner: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Comment-Date: Wed, 28 Apr 2021 14:40:39 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: sc7280: cpucp loading changes
by build bot (Jenkins) (Code Review) 29 Apr '21

29 Apr '21

Attention is currently required from: Ravi kumar, Shelley Chen, Martin Roth, Julius Werner. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49768 ) Change subject: sc7280: cpucp loading changes ...................................................................... Patch Set 31: (42 comments) File src/soc/qualcomm/sc7280/cpucp_load_reset.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-117951): https://review.coreboot.org/c/coreboot/+/49768/comment/f0dca2a1_7e1968ae PS31, Line 15: uint32_t val = read32(EPSSTOP_SECURE_ACCESS_OVERRIDE); code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-117951): https://review.coreboot.org/c/coreboot/+/49768/comment/24e22427_c3df3624 PS31, Line 15: uint32_t val = read32(EPSSTOP_SECURE_ACCESS_OVERRIDE); please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-117951): https://review.coreboot.org/c/coreboot/+/49768/comment/2b9192b4_110d4986 PS31, Line 16: val |= 0x1; code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-117951): https://review.coreboot.org/c/coreboot/+/49768/comment/6fd5887a_bfa1fb75 PS31, Line 16: val |= 0x1; please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-117951): https://review.coreboot.org/c/coreboot/+/49768/comment/c36224ee_ffa941e2 PS31, Line 18: /* allow NS access to EPSS memory*/ code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-117951): https://review.coreboot.org/c/coreboot/+/49768/comment/ff7984c3_5c229f1b PS31, Line 19: write32(EPSSTOP_SECURE_ACCESS_OVERRIDE, val); code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-117951): https://review.coreboot.org/c/coreboot/+/49768/comment/aeb6d54f_9d75328f PS31, Line 19: write32(EPSSTOP_SECURE_ACCESS_OVERRIDE, val); please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-117951): https://review.coreboot.org/c/coreboot/+/49768/comment/9fbd7666_d82a4c7d PS31, Line 21: val = read32(EPSSFAST_EPSS_MUC_CLK_CTRL); code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-117951): https://review.coreboot.org/c/coreboot/+/49768/comment/a80f3727_deee5811 PS31, Line 21: val = read32(EPSSFAST_EPSS_MUC_CLK_CTRL); please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-117951): https://review.coreboot.org/c/coreboot/+/49768/comment/35412665_54b1a55d PS31, Line 22: val |= 0x1; code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-117951): https://review.coreboot.org/c/coreboot/+/49768/comment/8d665a45_3d77f127 PS31, Line 22: val |= 0x1; please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-117951): https://review.coreboot.org/c/coreboot/+/49768/comment/80db9b16_8514c060 PS31, Line 24: /* Enable subsystem clock. Required for CPUCP PDMEM access*/ code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-117951): https://review.coreboot.org/c/coreboot/+/49768/comment/4a541f90_f4114c20 PS31, Line 25: write32(EPSSFAST_EPSS_MUC_CLK_CTRL, val); code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-117951): https://review.coreboot.org/c/coreboot/+/49768/comment/a93b1fb0_7c021248 PS31, Line 25: write32(EPSSFAST_EPSS_MUC_CLK_CTRL, val); please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-117951): https://review.coreboot.org/c/coreboot/+/49768/comment/a25a6a40_54aee4fb PS31, Line 27: while((read32(EPSSFAST_EPSS_MUC_CLK_CTRL) & 0x1) != 0x1); code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-117951): https://review.coreboot.org/c/coreboot/+/49768/comment/937b783c_eecb428a PS31, Line 27: while((read32(EPSSFAST_EPSS_MUC_CLK_CTRL) & 0x1) != 0x1); please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-117951): https://review.coreboot.org/c/coreboot/+/49768/comment/6b0d59da_0aa3d66d PS31, Line 27: while((read32(EPSSFAST_EPSS_MUC_CLK_CTRL) & 0x1) != 0x1); space required before the open parenthesis '(' Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-117951): https://review.coreboot.org/c/coreboot/+/49768/comment/af95fe38_5f7f92b6 PS31, Line 27: while((read32(EPSSFAST_EPSS_MUC_CLK_CTRL) & 0x1) != 0x1); trailing statements should be on next line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-117951): https://review.coreboot.org/c/coreboot/+/49768/comment/c838793b_5da32636 PS31, Line 32: bool cpucp_fw_entry; code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-117951): https://review.coreboot.org/c/coreboot/+/49768/comment/86f1bdb9_ad60d65e PS31, Line 32: bool cpucp_fw_entry; please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-117951): https://review.coreboot.org/c/coreboot/+/49768/comment/381178da_428f9687 PS31, Line 33: printk(BIOS_DEBUG, "\nSOC:CPUCP image loading.\n"); code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-117951): https://review.coreboot.org/c/coreboot/+/49768/comment/56e7803e_9b066e58 PS31, Line 33: printk(BIOS_DEBUG, "\nSOC:CPUCP image loading.\n"); please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-117951): https://review.coreboot.org/c/coreboot/+/49768/comment/896d14e2_e7b7e7b3 PS31, Line 35: struct prog cpucp_fw_prog = code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-117951): https://review.coreboot.org/c/coreboot/+/49768/comment/bb51eda3_72c025da PS31, Line 35: struct prog cpucp_fw_prog = please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-117951): https://review.coreboot.org/c/coreboot/+/49768/comment/8a162283_9c32827f PS31, Line 36: PROG_INIT(PROG_PAYLOAD, CONFIG_CBFS_PREFIX "/cpucp"); code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-117951): https://review.coreboot.org/c/coreboot/+/49768/comment/b8558e6b_01e9020f PS31, Line 36: PROG_INIT(PROG_PAYLOAD, CONFIG_CBFS_PREFIX "/cpucp"); please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-117951): https://review.coreboot.org/c/coreboot/+/49768/comment/a94b5d7e_e43a64e2 PS31, Line 38: cpucp_prepare(); code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-117951): https://review.coreboot.org/c/coreboot/+/49768/comment/1fd748cc_6c6f9a84 PS31, Line 38: cpucp_prepare(); please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-117951): https://review.coreboot.org/c/coreboot/+/49768/comment/c8fb0d75_865b1251 PS31, Line 40: if (prog_locate(&cpucp_fw_prog)) code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-117951): https://review.coreboot.org/c/coreboot/+/49768/comment/da45d4e7_a6a4748b PS31, Line 40: if (prog_locate(&cpucp_fw_prog)) please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-117951): https://review.coreboot.org/c/coreboot/+/49768/comment/add8c44d_e72a5caf PS31, Line 41: die("SOC imagpe: CPUCP_FW not found"); code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-117951): https://review.coreboot.org/c/coreboot/+/49768/comment/238bc0d2_b089ce64 PS31, Line 41: die("SOC imagpe: CPUCP_FW not found"); please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-117951): https://review.coreboot.org/c/coreboot/+/49768/comment/46d3f395_ccbd4b0a PS31, Line 43: cpucp_fw_entry = selfload(&cpucp_fw_prog); code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-117951): https://review.coreboot.org/c/coreboot/+/49768/comment/be2d72f5_e9e3f043 PS31, Line 43: cpucp_fw_entry = selfload(&cpucp_fw_prog); please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-117951): https://review.coreboot.org/c/coreboot/+/49768/comment/58433d69_f26632cb PS31, Line 44: if (!cpucp_fw_entry) code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-117951): https://review.coreboot.org/c/coreboot/+/49768/comment/d45a0779_69d50c35 PS31, Line 44: if (!cpucp_fw_entry) please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-117951): https://review.coreboot.org/c/coreboot/+/49768/comment/640e3b3d_c3416d19 PS31, Line 45: die("SOC image: CPUCP load failed"); code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-117951): https://review.coreboot.org/c/coreboot/+/49768/comment/86a5bfb7_4f502173 PS31, Line 45: die("SOC image: CPUCP load failed"); please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-117951): https://review.coreboot.org/c/coreboot/+/49768/comment/00170d63_5295b833 PS31, Line 47: printk(BIOS_DEBUG, "\nSOC:CPUCP image loaded successfully.\n"); code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-117951): https://review.coreboot.org/c/coreboot/+/49768/comment/e8b24973_a57d71aa PS31, Line 47: printk(BIOS_DEBUG, "\nSOC:CPUCP image loaded successfully.\n"); please, no spaces at the start of a line File src/soc/qualcomm/sc7280/soc.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-117951): https://review.coreboot.org/c/coreboot/+/49768/comment/5c6909b4_e8c051dd PS31, Line 20: REGION_SIZE(dram_cpucp) / KiB); code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-117951): https://review.coreboot.org/c/coreboot/+/49768/comment/c692eb48_a8f3072a PS31, Line 20: REGION_SIZE(dram_cpucp) / KiB); please, no spaces at the start of a line -- To view, visit https://review.coreboot.org/c/coreboot/+/49768 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idac22c8cb231658616999bc577bdf49f9aa7ae74 Gerrit-Change-Number: 49768 Gerrit-PatchSet: 31 Gerrit-Owner: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Ravi Kumar Bokka <c_rbokka(a)qualcomm.corp-partner.google.com> Gerrit-Attention: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Attention: Shelley Chen <shchen(a)google.com> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Comment-Date: Wed, 28 Apr 2021 14:38:01 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: sc7280: aop loading changes
by build bot (Jenkins) (Code Review) 29 Apr '21

29 Apr '21

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Change in coreboot[master]: sc7280: shrm.elf loading changes
by build bot (Jenkins) (Code Review) 29 Apr '21

29 Apr '21

Attention is currently required from: Ravi kumar, Shelley Chen, Martin Roth, mturney mturney, Julius Werner. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49392 ) Change subject: sc7280: shrm.elf loading changes ...................................................................... Patch Set 32: (1 comment) File src/soc/qualcomm/sc7280/shrm_load_reset.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-117949): https://review.coreboot.org/c/coreboot/+/49392/comment/8559b266_4811980f PS32, Line 9: void shrm_fw_load_reset() Bad function definition - void shrm_fw_load_reset() should probably be void shrm_fw_load_reset(void) -- To view, visit https://review.coreboot.org/c/coreboot/+/49392 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I44484573a829eaefbd34907c6fe78d427506a762 Gerrit-Change-Number: 49392 Gerrit-PatchSet: 32 Gerrit-Owner: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: mturney mturney <mturney(a)codeaurora.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Ravi Kumar Bokka <c_rbokka(a)qualcomm.corp-partner.google.com> Gerrit-Attention: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Attention: Shelley Chen <shchen(a)google.com> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: mturney mturney <mturney(a)codeaurora.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Comment-Date: Wed, 28 Apr 2021 14:36:49 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/skylake: Allow to use Amber Lake FSP
by Nico Huber (Code Review) 29 Apr '21

29 Apr '21

Attention is currently required from: Timofey Komarov, Felix Singer, Angel Pons, Patrick Rudolph. Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52692 ) Change subject: soc/intel/skylake: Allow to use Amber Lake FSP ...................................................................... Patch Set 5: Code-Review+1 (2 comments) File src/soc/intel/skylake/Kconfig: https://review.coreboot.org/c/coreboot/+/52692/comment/349f73da_f7c5e84f PS5, Line 19: select SOC_INTEL_COMMON_SKYLAKE_BASE You can also select SKYLAKE_SOC_PCH_H here. https://review.coreboot.org/c/coreboot/+/52692/comment/3336e067_70b67be5 PS5, Line 95: default 16 if MAINBOARD_SUPPORTS_COFFEELAKE_CPU > I'd do this in CB:52693 Alternatively, keep it in this change, but adapt the commit message; i.e. make it about the platform not the FSP. e.g. something like: soc/intel/skylake: Add Kconfig option for LGA1151v2 Provide a SOC_INTEL_SKYLAKE_LGA1151_V2 option to select correct defaults for the combination of a Union Point PCH with LGA1151v2. This includes: FSP... MAX_CPUS... PCH_H... -- To view, visit https://review.coreboot.org/c/coreboot/+/52692 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7b6b9c676da55088cb5a12a218ea58d349ee440c Gerrit-Change-Number: 52692 Gerrit-PatchSet: 5 Gerrit-Owner: Timofey Komarov <happycorsair(a)yandex.ru> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Singer <felixsinger(a)posteo.net> Gerrit-Attention: Timofey Komarov <happycorsair(a)yandex.ru> Gerrit-Attention: Felix Singer <felixsinger(a)posteo.net> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Wed, 28 Apr 2021 14:30:44 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

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Change in coreboot[master]: sc7280: reserved wlan & wpss dram memory regions
by build bot (Jenkins) (Code Review) 29 Apr '21

29 Apr '21

Attention is currently required from: Ravi kumar, Shelley Chen, mturney mturney, Julius Werner. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50587 ) Change subject: sc7280: reserved wlan & wpss dram memory regions ...................................................................... Patch Set 30: (4 comments) File src/soc/qualcomm/sc7280/soc.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-117938): https://review.coreboot.org/c/coreboot/+/50587/comment/f9984c95_f2f90058 PS30, Line 16: REGION_SIZE(dram_wlan) / KiB); code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-117938): https://review.coreboot.org/c/coreboot/+/50587/comment/4109e3bd_6bbdbcdc PS30, Line 16: REGION_SIZE(dram_wlan) / KiB); please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-117938): https://review.coreboot.org/c/coreboot/+/50587/comment/6cce1d5c_1d7b6c3a PS30, Line 18: REGION_SIZE(dram_wpss) / KiB); code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-117938): https://review.coreboot.org/c/coreboot/+/50587/comment/08c83b16_97fca138 PS30, Line 18: REGION_SIZE(dram_wpss) / KiB); please, no spaces at the start of a line -- To view, visit https://review.coreboot.org/c/coreboot/+/50587 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic98b5d08a0a7b3f772582bf85d94f901a7c53010 Gerrit-Change-Number: 50587 Gerrit-PatchSet: 30 Gerrit-Owner: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: mturney mturney <mturney(a)codeaurora.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Ravi Kumar Bokka <c_rbokka(a)qualcomm.corp-partner.google.com> Gerrit-Attention: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Attention: Shelley Chen <shchen(a)google.com> Gerrit-Attention: mturney mturney <mturney(a)codeaurora.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Comment-Date: Wed, 28 Apr 2021 14:28:34 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/dedede: Create pirika variant
by Henry Sun (Code Review) 29 Apr '21

29 Apr '21

Attention is currently required from: Paul2 Huang, Kirk Wang, Shou-Chieh Hsu, Karthik Ramasubramanian. Henry Sun has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52626 ) Change subject: mb/google/dedede: Create pirika variant ...................................................................... Patch Set 1: Code-Review+1 (1 comment) Patchset: PS1: Adding Karthik for review. Thanks! -- To view, visit https://review.coreboot.org/c/coreboot/+/52626 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I57bf33deeadacc88800f9ce1d3d54385ba56c798 Gerrit-Change-Number: 52626 Gerrit-PatchSet: 1 Gerrit-Owner: Kirk Wang Gerrit-Reviewer: Alex1 Kao <alex1_kao(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Henry Sun <henrysun(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Kirk Wang <kirk_wang(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Paul2 Huang <paul2_huang(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Shou-Chieh Hsu <shouchieh(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Ariel Chang <ariel_chang(a)pegatron.corp-partner.google.com> Gerrit-CC: Hao Chou <hao_chou(a)pegatron.corp-partner.google.com> Gerrit-CC: Wayne3 Wang <wayne3_wang(a)pegatron.corp-partner.google.com> Gerrit-Attention: Paul2 Huang <paul2_huang(a)pegatron.corp-partner.google.com> Gerrit-Attention: Kirk Wang Gerrit-Attention: Shou-Chieh Hsu <shouchieh(a)google.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Wed, 28 Apr 2021 14:28:05 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: drivers/intel/gma/Kconfig: Simplify CFL/WHL/CML conditions
by Nico Huber (Code Review) 29 Apr '21

29 Apr '21

Attention is currently required from: Angel Pons, Patrick Rudolph. Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52715 ) Change subject: drivers/intel/gma/Kconfig: Simplify CFL/WHL/CML conditions ...................................................................... Patch Set 1: Code-Review+2 (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/52715/comment/d3be6449_465d1693 PS1, Line 8: NB. It works like this because CANNONLAKE in coreboot means anything with a Cannon Point PCH *except* Cannon Lake. -- To view, visit https://review.coreboot.org/c/coreboot/+/52715 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id56761b2a57754b8f8d726a4bd2674ffa6fd1159 Gerrit-Change-Number: 52715 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Wed, 28 Apr 2021 14:18:32 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: HACK sc7280: QSIP SPI NOR addressing mode HACK
by Ravi kumar (Code Review) 29 Apr '21

29 Apr '21

Attention is currently required from: Ravi kumar, mturney mturney. Hello build bot (Jenkins), Sajida Bhanu, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/50586 to look at the new patch set (#32). Change subject: HACK sc7280: QSIP SPI NOR addressing mode HACK ...................................................................... HACK sc7280: QSIP SPI NOR addressing mode HACK Force SPI NOR 3 byte addr mode as 4 byte addr mode is not supported. Change-Id: Ied5b647d0fcc8e3effff3bb7c8680ed5a0c1f3d4 Signed-off-by: Veerabhadrarao Badiganti <vbadigan(a)codeaurora.org> Signed-off-by: Shaik Sajida Bhanu <sbhanu(a)codeaurora.org> --- M src/drivers/spi/spi_flash.c M src/mainboard/google/herobrine/Kconfig 2 files changed, 21 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/86/50586/32 -- To view, visit https://review.coreboot.org/c/coreboot/+/50586 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ied5b647d0fcc8e3effff3bb7c8680ed5a0c1f3d4 Gerrit-Change-Number: 50586 Gerrit-PatchSet: 32 Gerrit-Owner: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Reviewer: Sajida Bhanu <sbhanu(a)codeaurora.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Attention: mturney mturney <mturney(a)codeaurora.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: WIP herobrine: Add support for xhci WIP
by Ravi kumar (Code Review) 29 Apr '21

29 Apr '21

Attention is currently required from: Shelley Chen, Ravi kumar, Sandeep Maheswaram, mturney mturney, Julius Werner. Hello Shelley Chen, build bot (Jenkins), Sandeep Maheswaram, mturney mturney, Julius Werner, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/51521 to look at the new patch set (#27). Change subject: WIP herobrine: Add support for xhci WIP ...................................................................... WIP herobrine: Add support for xhci WIP Change-Id: Id1f44b8511281bd496ba06da14b8d8c863ce8bf1 Signed-off-by: Sandeep Maheswaram <sanm(a)codeaurora.org> --- M payloads/libpayload/configs/config.herobrine 1 file changed, 3 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/21/51521/27 -- To view, visit https://review.coreboot.org/c/coreboot/+/51521 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id1f44b8511281bd496ba06da14b8d8c863ce8bf1 Gerrit-Change-Number: 51521 Gerrit-PatchSet: 27 Gerrit-Owner: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Sandeep Maheswaram <sanm(a)codeaurora.org> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: mturney mturney <mturney(a)codeaurora.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Ravi Kumar Bokka <c_rbokka(a)qualcomm.corp-partner.google.com> Gerrit-Attention: Shelley Chen <shchen(a)google.com> Gerrit-Attention: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Attention: Sandeep Maheswaram <sanm(a)codeaurora.org> Gerrit-Attention: mturney mturney <mturney(a)codeaurora.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-MessageType: newpatchset

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coreboot-gerrit April 2021