coreboot-gerrit April 2021

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: mb/google/brya: Add CHROMEOS_DRAM_PART_NUMBER_IN_CBI
by EricR Lai (Code Review) 28 Apr '21

28 Apr '21

Attention is currently required from: EricR Lai. Hello build bot (Jenkins), Tim Wawrzynczak, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/52726 to look at the new patch set (#2). Change subject: mb/google/brya: Add CHROMEOS_DRAM_PART_NUMBER_IN_CBI ...................................................................... mb/google/brya: Add CHROMEOS_DRAM_PART_NUMBER_IN_CBI Brya uses CBI to store dram part number. So enable the config. BUG=b:186571840 BRANCH=none TEST=dmidecode -t 17 can show the dram part number. Signed-off-by: Eric Lai <ericr_lai(a)compal.corp-partner.google.com> Change-Id: I1b4fc4da31d8964763c3e671d84be71996fa5e2a --- M src/mainboard/google/brya/Kconfig 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/26/52726/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/52726 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1b4fc4da31d8964763c3e671d84be71996fa5e2a Gerrit-Change-Number: 52726 Gerrit-PatchSet: 2 Gerrit-Owner: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/google/mancomb: Enable VBOOT_LID_SWITCH
by Raul Rangel (Code Review) 28 Apr '21

28 Apr '21

Attention is currently required from: Furquan Shaikh, Ivy Jian, Karthik Ramasubramanian. Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52602 ) Change subject: mb/google/mancomb: Enable VBOOT_LID_SWITCH ...................................................................... Patch Set 1: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/52602/comment/f8d56851_9469760a PS1, Line 13: TEST=Depthcharge no longer halts complaining that coreboot didn't sample : the pin > Thanks for suggestion,I just tried on depthcharge change, but still halt in depthcarge. […] Need to remove it from here too: https://source.chromium.org/chromiumos/chromiumos/codesearch/+/main:src/thi… -- To view, visit https://review.coreboot.org/c/coreboot/+/52602 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifd0fcec9557bf7ebad64ce9342d3b50eb511522b Gerrit-Change-Number: 52602 Gerrit-PatchSet: 1 Gerrit-Owner: Ivy Jian <ivy_jian(a)compal.corp-partner.google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Mathew King <mathewk(a)chromium.org> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Ivy Jian <ivy_jian(a)compal.corp-partner.google.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Wed, 28 Apr 2021 14:55:40 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Raul Rangel <rrangel(a)chromium.org> Comment-In-Reply-To: Ivy Jian <ivy_jian(a)compal.corp-partner.google.com> Comment-In-Reply-To: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/brya: Add CHROMEOS_DRAM_PART_NUMBER_IN_CBI
by Tim Wawrzynczak (Code Review) 28 Apr '21

28 Apr '21

Attention is currently required from: EricR Lai. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52726 ) Change subject: mb/google/brya: Add CHROMEOS_DRAM_PART_NUMBER_IN_CBI ...................................................................... Patch Set 1: Code-Review+2 (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/52726/comment/5470896d_b51a0b7b PS1, Line 9: is use uses -- To view, visit https://review.coreboot.org/c/coreboot/+/52726 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1b4fc4da31d8964763c3e671d84be71996fa5e2a Gerrit-Change-Number: 52726 Gerrit-PatchSet: 1 Gerrit-Owner: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Comment-Date: Wed, 28 Apr 2021 14:47:14 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/intel/adlrvp: Align chromeos.fmd file with Brya
by Maulik V Vaghela (Code Review) 28 Apr '21

28 Apr '21

Attention is currently required from: Furquan Shaikh, Tim Wawrzynczak. Maulik V Vaghela has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52732 ) Change subject: mb/intel/adlrvp: Align chromeos.fmd file with Brya ...................................................................... Patch Set 1: (2 comments) Patchset: PS1: Updated SI_ALL region to 6 MB since ME.bin size for ADLRVP is 4.8 MB which would be difficult to accomodate within 5 MB along with EC.bin File src/mainboard/intel/adlrvp/chromeos.fmd: https://review.coreboot.org/c/coreboot/+/52732/comment/448a0ddc_0724cf84 PS1, Line 4: SI_EC 0x80000 > windows sku need this Done -- To view, visit https://review.coreboot.org/c/coreboot/+/52732 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I644e2e5ba06d2b816d413a7cc9f5f248d8a6fee8 Gerrit-Change-Number: 52732 Gerrit-PatchSet: 1 Gerrit-Owner: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-CC: Spoorthi K <spoorthi.k(a)intel.com> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Comment-Date: Wed, 28 Apr 2021 14:46:18 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subrata.banik(a)intel.com> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/intel/adlrvp: Align chromeos.fmd file with Brya
by Maulik V Vaghela (Code Review) 28 Apr '21

28 Apr '21

Attention is currently required from: Furquan Shaikh, Maulik V Vaghela, Tim Wawrzynczak. Hello build bot (Jenkins), Furquan Shaikh, Tim Wawrzynczak, Subrata Banik, Meera Ravindranath, Ronak Kanabar, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/52732 to look at the new patch set (#2). Change subject: mb/intel/adlrvp: Align chromeos.fmd file with Brya ...................................................................... mb/intel/adlrvp: Align chromeos.fmd file with Brya While moving to emerge build for coreboot, Adlrvp doesn't have space for CBFS region. We need to update fmd file to align with Brya, so that we have enough space in CBFS and FW_MAIN_* regions to accomodate all necessary binaries such as Microcode, VBT, EC, ME etc. BUG=b:184997582 BRANCH=NONE TEST=Code compiles fine and able to boot adlrvp platform Change-Id: I644e2e5ba06d2b816d413a7cc9f5f248d8a6fee8 Signed-off-by: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> --- M src/mainboard/intel/adlrvp/chromeos.fmd 1 file changed, 38 insertions(+), 32 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/32/52732/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/52732 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I644e2e5ba06d2b816d413a7cc9f5f248d8a6fee8 Gerrit-Change-Number: 52732 Gerrit-PatchSet: 2 Gerrit-Owner: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-CC: Spoorthi K <spoorthi.k(a)intel.com> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: sc7180: Add backlight support for sn65dsi86bridge
by build bot (Jenkins) (Code Review) 28 Apr '21

28 Apr '21

Attention is currently required from: Shelley Chen, Ravi kumar, mturney mturney. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52663 ) Change subject: sc7180: Add backlight support for sn65dsi86bridge ...................................................................... Patch Set 2: (1 comment) File src/drivers/ti/sn65dsi86bridge/sn65dsi86bridge.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-117971): https://review.coreboot.org/c/coreboot/+/52663/comment/7b02863e_8b2bb6d9 PS2, Line 443: uint8_t brightness[2] = {0xff,0xff}; space required after that ',' (ctx:VxV) -- To view, visit https://review.coreboot.org/c/coreboot/+/52663 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie700080f1feabe2d3397c38088a64cff27bfbe55 Gerrit-Change-Number: 52663 Gerrit-PatchSet: 2 Gerrit-Owner: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: mturney mturney <mturney(a)codeaurora.org> Gerrit-CC: Ravi Kumar Bokka <c_rbokka(a)qualcomm.corp-partner.google.com> Gerrit-Attention: Shelley Chen <shchen(a)google.com> Gerrit-Attention: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Attention: mturney mturney <mturney(a)codeaurora.org> Gerrit-Comment-Date: Wed, 28 Apr 2021 14:44:17 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: sc7180: Add display support for mipi panels
by build bot (Jenkins) (Code Review) 28 Apr '21

28 Apr '21

Attention is currently required from: Shelley Chen, Julius Werner, mturney mturney. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52662 ) Change subject: sc7180: Add display support for mipi panels ...................................................................... Patch Set 2: (15 comments) File src/mainboard/google/trogdor/mainboard.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-117970): https://review.coreboot.org/c/coreboot/+/52662/comment/1a0ce7a2_cf289cb4 PS2, Line 101: if(CONFIG(TROGDOR_HAS_MIPI_PANEL)) space required before the open parenthesis '(' File src/soc/qualcomm/sc7180/display/dsi.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-117970): https://review.coreboot.org/c/coreboot/+/52662/comment/25050419_34a284e1 PS2, Line 65: write32(&dsi0->trig_ctrl,DSI_DMA_STREAM1 << 8 | DSI_DMA_TRIGGER_SEL); space required after that ',' (ctx:VxV) Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-117970): https://review.coreboot.org/c/coreboot/+/52662/comment/5576877d_a3fcf937 PS2, Line 172: write32(&dsi0->int_ctrl,0x0); space required after that ',' (ctx:VxV) Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-117970): https://review.coreboot.org/c/coreboot/+/52662/comment/525fac2e_16ec0649 PS2, Line 210: printk(BIOS_ERR, Invalid vsprintf pointer extension '%pk' Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-117970): https://review.coreboot.org/c/coreboot/+/52662/comment/2d1369cd_e21836f9 PS2, Line 281: wmb(); memory barrier without comment Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-117970): https://review.coreboot.org/c/coreboot/+/52662/comment/82c8f040_37163c62 PS2, Line 289: wmb(); memory barrier without comment Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-117970): https://review.coreboot.org/c/coreboot/+/52662/comment/10c37931_187c877a PS2, Line 292: wmb(); memory barrier without comment Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-117970): https://review.coreboot.org/c/coreboot/+/52662/comment/ed301257_426ef738 PS2, Line 299: wmb(); memory barrier without comment Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-117970): https://review.coreboot.org/c/coreboot/+/52662/comment/ac3cbba2_c531d75f PS2, Line 302: wmb(); memory barrier without comment Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-117970): https://review.coreboot.org/c/coreboot/+/52662/comment/a8d8b79b_87c43829 PS2, Line 319: write32(&dsi0->int_ctrl,0x0); space required after that ',' (ctx:VxV) Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-117970): https://review.coreboot.org/c/coreboot/+/52662/comment/0a039e7f_f0ca74a3 PS2, Line 322: setbits32(&dsi0->int_ctrl,DSI_CMD_MODE_DMA_DONE_AK); space required after that ',' (ctx:VxV) Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-117970): https://review.coreboot.org/c/coreboot/+/52662/comment/27f14125_9dca8d28 PS2, Line 325: setbits32(&dsi0->int_ctrl,DSI_CMD_MODE_MDP_DONE_AK); space required after that ',' (ctx:VxV) Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-117970): https://review.coreboot.org/c/coreboot/+/52662/comment/096b5b27_69315dd2 PS2, Line 328: setbits32(&dsi0->int_ctrl,DSI_VIDEO_MODE_DONE_AK); space required after that ',' (ctx:VxV) Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-117970): https://review.coreboot.org/c/coreboot/+/52662/comment/2642375b_ecb43de1 PS2, Line 333: setbits32(&dsi0->int_ctrl,DSI_ERROR_AK); space required after that ',' (ctx:VxV) Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-117970): https://review.coreboot.org/c/coreboot/+/52662/comment/e8d8c28e_5d0f6500 PS2, Line 343: if(!pinfo && !pinfo->init_cmd) space required before the open parenthesis '(' -- To view, visit https://review.coreboot.org/c/coreboot/+/52662 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id698265a4e2399ad1c26e026e9a5f8ecd305467f Gerrit-Change-Number: 52662 Gerrit-PatchSet: 2 Gerrit-Owner: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: mturney mturney <mturney(a)codeaurora.org> Gerrit-CC: Ravi Kumar Bokka <c_rbokka(a)qualcomm.corp-partner.google.com> Gerrit-Attention: Shelley Chen <shchen(a)google.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: mturney mturney <mturney(a)codeaurora.org> Gerrit-Comment-Date: Wed, 28 Apr 2021 14:44:00 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: HACK sc7280: QSIP SPI NOR addressing mode HACK
by build bot (Jenkins) (Code Review) 28 Apr '21

28 Apr '21

Attention is currently required from: Ravi kumar, mturney mturney. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50586 ) Change subject: HACK sc7280: QSIP SPI NOR addressing mode HACK ...................................................................... Patch Set 32: (1 comment) File src/drivers/spi/spi_flash.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-117966): https://review.coreboot.org/c/coreboot/+/50586/comment/27a3437b_8c1e3814 PS32, Line 497: while (1) suspect code indent for conditional statements (16, 16) -- To view, visit https://review.coreboot.org/c/coreboot/+/50586 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ied5b647d0fcc8e3effff3bb7c8680ed5a0c1f3d4 Gerrit-Change-Number: 50586 Gerrit-PatchSet: 32 Gerrit-Owner: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Reviewer: Sajida Bhanu <sbhanu(a)codeaurora.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Attention: mturney mturney <mturney(a)codeaurora.org> Gerrit-Comment-Date: Wed, 28 Apr 2021 14:42:55 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: HACK payloads: Add libpci for arm arch HACK
by build bot (Jenkins) (Code Review) 28 Apr '21

28 Apr '21

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Change in coreboot[master]: sc7280: Add PCIe Root Complex driver in coreboot
by build bot (Jenkins) (Code Review) 28 Apr '21

28 Apr '21

Attention is currently required from: Shelley Chen, Ravi kumar, Martin Roth, mturney mturney, Julius Werner. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52375 ) Change subject: sc7280: Add PCIe Root Complex driver in coreboot ...................................................................... Patch Set 4: (60 comments) File src/soc/qualcomm/sc7280/include/soc/addressmap.h: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-117963): https://review.coreboot.org/c/coreboot/+/52375/comment/f0a13fc6_efd85412 PS4, Line 65: #define PCIE1_IO_ADDR 0x40200000 please, no space before tabs Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-117963): https://review.coreboot.org/c/coreboot/+/52375/comment/785e7bb0_39aae873 PS4, Line 68: #define PCIE1_MEM_SIZE 0x1fd00000 please, no space before tabs Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-117963): https://review.coreboot.org/c/coreboot/+/52375/comment/8a9ff344_be867ea3 PS4, Line 69: #define PCIE_MEM_END 0x404fffff please, no space before tabs Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-117963): https://review.coreboot.org/c/coreboot/+/52375/comment/c5b9f24c_90d593e8 PS4, Line 72: #define PCIE_1_QMP_PHY 0x01C0E000 please, no space before tabs Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-117963): https://review.coreboot.org/c/coreboot/+/52375/comment/faace053_60ef90f3 PS4, Line 76: #define PCE1_QPHY_SERDES 0x01C0E000 please, no space before tabs File src/soc/qualcomm/sc7280/include/soc/pcie.h: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-117963): https://review.coreboot.org/c/coreboot/+/52375/comment/ec54032d_a9f650d2 PS4, Line 12: #define GPIO_PERST 2 please, no space before tabs Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-117963): https://review.coreboot.org/c/coreboot/+/52375/comment/ad2cb324_b67e6ffc PS4, Line 14: #define PCIE_DEV_FUNC (dev,func) PCI_SLOT(devfn) | PCI_FUNC(devfn) space required after that ',' (ctx:VxV) Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-117963): https://review.coreboot.org/c/coreboot/+/52375/comment/f2e9a223_c9be1a79 PS4, Line 14: #define PCIE_DEV_FUNC (dev,func) PCI_SLOT(devfn) | PCI_FUNC(devfn) Macros with complex values should be enclosed in parentheses Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-117963): https://review.coreboot.org/c/coreboot/+/52375/comment/f8307a4f_d05a3149 PS4, Line 94: #define PCIE_DEV(_bus, _dev, _fn) (0x80000000 | \ Macros with complex values should be enclosed in parentheses Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-117963): https://review.coreboot.org/c/coreboot/+/52375/comment/d2be87fb_1a07c416 PS4, Line 106: #define PCIE_BUS_CFG(pri,sec,sub) ((sub & 0xFF)<<16|(sec & 0xFF)<<8|(pri&0xFF)) space required after that ',' (ctx:VxV) Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-117963): https://review.coreboot.org/c/coreboot/+/52375/comment/6d8da29d_48f62d20 PS4, Line 106: #define PCIE_BUS_CFG(pri,sec,sub) ((sub & 0xFF)<<16|(sec & 0xFF)<<8|(pri&0xFF)) space required after that ',' (ctx:VxV) Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-117963): https://review.coreboot.org/c/coreboot/+/52375/comment/f3e58ed8_3252732b PS4, Line 215: #define PCIE1_QMP_PHY_PCS_COM 0x01C0EA00 please, no space before tabs Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-117963): https://review.coreboot.org/c/coreboot/+/52375/comment/cec17a67_9d0da5e9 PS4, Line 216: #define PCE1_QPHY_SERDES 0x01C0E000 please, no space before tabs Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-117963): https://review.coreboot.org/c/coreboot/+/52375/comment/5bb81a39_db10e875 PS4, Line 217: #define PCE1_QPHY_TX0 0x01C0E200 please, no space before tabs Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-117963): https://review.coreboot.org/c/coreboot/+/52375/comment/caa07561_36037716 PS4, Line 218: #define PCE1_QPHY_RX0 0x01C0E400 please, no space before tabs Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-117963): https://review.coreboot.org/c/coreboot/+/52375/comment/5da82612_6bec0572 PS4, Line 230: unsigned int offset; please, no spaces at the start of a line File src/soc/qualcomm/sc7280/include/soc/qcom_qmp_phy.h: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-117963): https://review.coreboot.org/c/coreboot/+/52375/comment/3f1085fd_8c1516bb PS4, Line 61: #define QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX 0x3c please, no space before tabs Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-117963): https://review.coreboot.org/c/coreboot/+/52375/comment/b925ee9b_505ecd0f PS4, Line 62: #define QSERDES_V4_TX_RES_CODE_LANE_OFFSET_RX 0x40 please, no space before tabs File src/soc/qualcomm/sc7280/pcie_host.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-117963): https://review.coreboot.org/c/coreboot/+/52375/comment/2b67f2be_4bd6042b PS4, Line 89: }qmp_phy_cfg_t; space required after that close brace '}' Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-117963): https://review.coreboot.org/c/coreboot/+/52375/comment/ccbd7bc0_57f69f4b PS4, Line 249: .qmp_phy_base = (void *) PCIE_1_QMP_PHY, please, no space before tabs Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-117963): https://review.coreboot.org/c/coreboot/+/52375/comment/c6b53cdc_c2215715 PS4, Line 250: .serdes = (void *) PCE1_QPHY_SERDES, please, no space before tabs Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-117963): https://review.coreboot.org/c/coreboot/+/52375/comment/05a52041_ac4f11c0 PS4, Line 251: .tx0 = (void *) PCE1_QPHY_TX0, please, no space before tabs Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-117963): https://review.coreboot.org/c/coreboot/+/52375/comment/1b0699fe_f76351e7 PS4, Line 252: .rx0 = (void *) PCE1_QPHY_RX0, please, no space before tabs Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-117963): https://review.coreboot.org/c/coreboot/+/52375/comment/768cc836_ddc9ed7b PS4, Line 253: .pcs = (void *) PCIE1_QMP_PHY_PCS_COM, please, no space before tabs Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-117963): https://review.coreboot.org/c/coreboot/+/52375/comment/f0afcb79_876c3c12 PS4, Line 254: .tx1 = (void *) PCE1_QPHY_TX1, please, no space before tabs Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-117963): https://review.coreboot.org/c/coreboot/+/52375/comment/08dbb5ee_d0ca81c3 PS4, Line 255: .rx1 = (void *) PCE1_QPHY_RX1, please, no space before tabs Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-117963): https://review.coreboot.org/c/coreboot/+/52375/comment/a3d66800_7214b229 PS4, Line 256: .pcs_misc = (void *) PCE1_QPHY_PCS_MISC, please, no space before tabs Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-117963): https://review.coreboot.org/c/coreboot/+/52375/comment/adb766c9_3a449b56 PS4, Line 270: .pcs_tbl_num_sec= ARRAY_SIZE(sc7280_qmp_gen3x2_pcie_pcs_tbl), spaces required around that '=' (ctx:VxW) Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-117963): https://review.coreboot.org/c/coreboot/+/52375/comment/dd22a745_73e1acac PS4, Line 272: .pcs_misc_tbl_num= ARRAY_SIZE(sc7280_qmp_pcie_pcs_misc_tbl), spaces required around that '=' (ctx:VxW) Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-117963): https://review.coreboot.org/c/coreboot/+/52375/comment/1e1bfd91_87c426ec PS4, Line 444: printk(BIOS_INFO, "PCIE1: Assert the reset of EP \n"); unnecessary whitespace before a quoted newline Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-117963): https://review.coreboot.org/c/coreboot/+/52375/comment/5fbf02bc_1521ab2d PS4, Line 676: if (!bar_response) { braces {} are not necessary for single statement blocks Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-117963): https://review.coreboot.org/c/coreboot/+/52375/comment/b3fc26c9_d4c0cdc3 PS4, Line 902: const struct qcom_qmp_phy_init_tbl tbl[], int num, uint8_t ln_mask) code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-117963): https://review.coreboot.org/c/coreboot/+/52375/comment/30e2aeb2_78667927 PS4, Line 902: const struct qcom_qmp_phy_init_tbl tbl[], int num, uint8_t ln_mask) please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-117963): https://review.coreboot.org/c/coreboot/+/52375/comment/fc078379_1ab19b62 PS4, Line 908: if (!(t->lane_mask & ln_mask)) { braces {} are not necessary for single statement blocks Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-117963): https://review.coreboot.org/c/coreboot/+/52375/comment/a5dd73a4_8d667461 PS4, Line 966: trailing whitespace Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-117963): https://review.coreboot.org/c/coreboot/+/52375/comment/645e7f06_4bbf3a73 PS4, Line 969: if (ret) { suspect code indent for conditional statements (8, 13) Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-117963): https://review.coreboot.org/c/coreboot/+/52375/comment/ea96a13d_b9219535 PS4, Line 970: printk(BIOS_ERR, " %s(): Pipe clock enable failed\n", __func__); trailing whitespace Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-117963): https://review.coreboot.org/c/coreboot/+/52375/comment/7f50411e_41421c7c PS4, Line 971: return -1; Statements should start on a tabstop Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-117963): https://review.coreboot.org/c/coreboot/+/52375/comment/bab53154_b4d40ed1 PS4, Line 989: pcie_rc_config_t *pcierc = pcie->rc_cfg; code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-117963): https://review.coreboot.org/c/coreboot/+/52375/comment/06dd3e02_181495ac PS4, Line 989: pcie_rc_config_t *pcierc = pcie->rc_cfg; please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-117963): https://review.coreboot.org/c/coreboot/+/52375/comment/ce9b21a9_de720bc3 PS4, Line 990: uint64_t ep_config_base, ep_config_size; code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-117963): https://review.coreboot.org/c/coreboot/+/52375/comment/4fb76569_9db8b104 PS4, Line 990: uint64_t ep_config_base, ep_config_size; please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-117963): https://review.coreboot.org/c/coreboot/+/52375/comment/a0ff43cb_f829ab40 PS4, Line 992: ep_config_base = (uint64_t)pcierc->cfg_base; code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-117963): https://review.coreboot.org/c/coreboot/+/52375/comment/5792b550_bc57d749 PS4, Line 992: ep_config_base = (uint64_t)pcierc->cfg_base; please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-117963): https://review.coreboot.org/c/coreboot/+/52375/comment/45206ea2_7f411b46 PS4, Line 993: ep_config_size = pcierc->cfg_size; code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-117963): https://review.coreboot.org/c/coreboot/+/52375/comment/e464a136_f41b09fd PS4, Line 993: ep_config_size = pcierc->cfg_size; please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-117963): https://review.coreboot.org/c/coreboot/+/52375/comment/b399fedf_e4ce6989 PS4, Line 996: qcom_dw_pcie_prog_outbound_atu(pcie, PCIE_ATU_REGION_INDEX1, code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-117963): https://review.coreboot.org/c/coreboot/+/52375/comment/41a2bd87_32c0acd7 PS4, Line 996: qcom_dw_pcie_prog_outbound_atu(pcie, PCIE_ATU_REGION_INDEX1, please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-117963): https://review.coreboot.org/c/coreboot/+/52375/comment/679bcc65_b4c6718f PS4, Line 997: PCIE_ATU_TYPE_CFG0, code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-117963): https://review.coreboot.org/c/coreboot/+/52375/comment/50095193_5db97f57 PS4, Line 997: PCIE_ATU_TYPE_CFG0, please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-117963): https://review.coreboot.org/c/coreboot/+/52375/comment/b33022c1_874cefc3 PS4, Line 998: ep_config_base, code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-117963): https://review.coreboot.org/c/coreboot/+/52375/comment/693057f1_182e6ea2 PS4, Line 998: ep_config_base, please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-117963): https://review.coreboot.org/c/coreboot/+/52375/comment/cd01d03c_ae2d8c46 PS4, Line 999: (1 << 24), ep_config_size); trailing whitespace Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-117963): https://review.coreboot.org/c/coreboot/+/52375/comment/5a79c6cf_98e84954 PS4, Line 999: (1 << 24), ep_config_size); code indent should use tabs where possible Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-117963): https://review.coreboot.org/c/coreboot/+/52375/comment/65b9fc6b_272b7f69 PS4, Line 999: (1 << 24), ep_config_size); please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-117963): https://review.coreboot.org/c/coreboot/+/52375/comment/0e31d39c_34260dd1 PS4, Line 1057: for (clk = PCIE_1_SLV_Q2A_AXI_CLK; clk < PCIE_CLK_COUNT - 3; clk ++) { space prohibited before that '++' (ctx:WxB) Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-117963): https://review.coreboot.org/c/coreboot/+/52375/comment/44b4eb0d_f78c4f1f PS4, Line 1064: trailing whitespace Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-117963): https://review.coreboot.org/c/coreboot/+/52375/comment/db4eef96_13c9e648 PS4, Line 1092: if(ret) { space required before the open parenthesis '(' Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-117963): https://review.coreboot.org/c/coreboot/+/52375/comment/747e817e_7f84c799 PS4, Line 1126: if(!ret) { space required before the open parenthesis '(' Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-117963): https://review.coreboot.org/c/coreboot/+/52375/comment/569e80d6_a4ae0f74 PS4, Line 1126: if(!ret) { braces {} are not necessary for any arm of this statement -- To view, visit https://review.coreboot.org/c/coreboot/+/52375 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I850fc43c840629667ac1c6de897306adb5a907e5 Gerrit-Change-Number: 52375 Gerrit-PatchSet: 4 Gerrit-Owner: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: mturney mturney <mturney(a)codeaurora.org> Gerrit-CC: Ravi Kumar Bokka <c_rbokka(a)qualcomm.corp-partner.google.com> Gerrit-Attention: Shelley Chen <shchen(a)google.com> Gerrit-Attention: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: mturney mturney <mturney(a)codeaurora.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Comment-Date: Wed, 28 Apr 2021 14:41:57 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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coreboot-gerrit April 2021