Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/52670 )
Change subject: mb/dell/optiplex_9010: Always log chosen fan mode
......................................................................
mb/dell/optiplex_9010: Always log chosen fan mode
Always print the chosen fan mode, not only when get_int_option() returns
the fallback value. Callers of get_int_option() should not try to handle
option-related errors, and simply proceed using the fallback value.
This change is needed to update the option API to use unsigned integers.
The CMOS option system does not support negative numbers.
Change-Id: Ic8adbe557b48a46f785d82fddb16383678705e87
Signed-off-by: Angel Pons <th3fanbus(a)gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52670
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
Reviewed-by: Patrick Rudolph <siro(a)das-labor.org>
Reviewed-by: Nico Huber <nico.h(a)gmx.de>
---
M src/mainboard/dell/optiplex_9010/sch5545_ec.c
1 file changed, 4 insertions(+), 7 deletions(-)
Approvals:
build bot (Jenkins): Verified
Nico Huber: Looks good to me, approved
Patrick Rudolph: Looks good to me, approved
diff --git a/src/mainboard/dell/optiplex_9010/sch5545_ec.c b/src/mainboard/dell/optiplex_9010/sch5545_ec.c
index db13495..9e25f18 100644
--- a/src/mainboard/dell/optiplex_9010/sch5545_ec.c
+++ b/src/mainboard/dell/optiplex_9010/sch5545_ec.c
@@ -656,20 +656,17 @@
ec_read_write_reg(EC_HWM_LDN, 0x02fc, &val_2fc, WRITE_OP);
- int fan_speed_full = get_int_option("fan_full_speed", -1);
- if (fan_speed_full < 0) {
- fan_speed_full = 0;
- printk(BIOS_INFO, "fan_full_speed CMOS option not found. "
- "Fans will be set up for automatic control\n");
- }
-
+ unsigned int fan_speed_full = get_int_option("fan_full_speed", 0);
if (fan_speed_full) {
+ printk(BIOS_INFO, "Will set up fans to run at full speed\n");
ec_read_write_reg(EC_HWM_LDN, 0x0080, &val, READ_OP);
val |= 0x60;
ec_read_write_reg(EC_HWM_LDN, 0x0080, &val, WRITE_OP);
ec_read_write_reg(EC_HWM_LDN, 0x0081, &val, READ_OP);
val |= 0x60;
ec_read_write_reg(EC_HWM_LDN, 0x0081, &val, WRITE_OP);
+ } else {
+ printk(BIOS_INFO, "Will set up fans for automatic control\n");
}
ec_read_write_reg(EC_HWM_LDN, 0x00b8, &val, READ_OP);
--
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Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/52540 )
Change subject: soc/amd/cezanne: copy psp_transfer.h from picasso
......................................................................
soc/amd/cezanne: copy psp_transfer.h from picasso
Cezanne version of psp_transfer.h lacks some necessary definitions.
Currently we don't have any plan to change transfer buffer structure in
cezanne, so just copy'em over.
Signed-off-by: Kangheui Won <khwon(a)chromium.org>
Change-Id: I9361c4ab76c8ded06358a7718d5e447c16414721
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52540
Reviewed-by: Marshall Dawson <marshalldawson3rd(a)gmail.com>
Reviewed-by: Raul Rangel <rrangel(a)chromium.org>
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
---
M src/soc/amd/cezanne/include/soc/psp_transfer.h
1 file changed, 49 insertions(+), 0 deletions(-)
Approvals:
build bot (Jenkins): Verified
Marshall Dawson: Looks good to me, approved
Raul Rangel: Looks good to me, approved
diff --git a/src/soc/amd/cezanne/include/soc/psp_transfer.h b/src/soc/amd/cezanne/include/soc/psp_transfer.h
index f5cd427..96cdae1 100644
--- a/src/soc/amd/cezanne/include/soc/psp_transfer.h
+++ b/src/soc/amd/cezanne/include/soc/psp_transfer.h
@@ -3,7 +3,56 @@
#ifndef AMD_CEZANNE_PSP_TRANSFER_H
#define AMD_CEZANNE_PSP_TRANSFER_H
+# if (CONFIG_CMOS_RECOVERY_BYTE != 0)
+# define CMOS_RECOVERY_BYTE CONFIG_CMOS_RECOVERY_BYTE
+# elif CONFIG(VBOOT_STARTS_BEFORE_BOOTBLOCK)
+# error "Must set CONFIG_CMOS_RECOVERY_BYTE"
+# endif
+
+#define CMOS_RECOVERY_MAGIC_VAL 0x96
+
#define TRANSFER_INFO_SIZE 64
#define TIMESTAMP_BUFFER_SIZE 0x200
+#define TRANSFER_MAGIC_VAL 0x50544953
+
+/* Bit definitions for the psp_info field in the PSP transfer_info_struct */
+#define PSP_INFO_PRODUCTION_MODE 0x00000001UL
+#define PSP_INFO_PRODUCTION_SILICON 0x00000002UL
+#define PSP_INFO_VALID 0x80000000UL
+
+/* Area for things that would cause errors in a linker script */
+#if !defined(__ASSEMBLER__)
+#include <stdint.h>
+
+struct transfer_info_struct {
+ uint32_t magic_val; /* Identifier */
+ uint32_t struct_bytes; /* Size of this structure */
+ uint32_t buffer_size; /* Size of the transfer buffer area */
+
+ /* Offsets from start of transfer buffer */
+ uint32_t workbuf_offset;
+ uint32_t console_offset;
+ uint32_t timestamp_offset;
+ uint32_t fmap_offset;
+
+ uint32_t unused1[5];
+
+ /* Fields reserved for the PSP */
+ uint64_t timestamp; /* Offset 0x30 */
+ uint32_t psp_unused; /* Offset 0x38 */
+ uint32_t psp_info; /* Offset 0x3C */
+};
+
+_Static_assert(sizeof(struct transfer_info_struct) == TRANSFER_INFO_SIZE,
+ "TRANSFER_INFO_SIZE is incorrect");
+
+/* Make sure the PSP transferred information over to x86 side. */
+void verify_psp_transfer_buf(void);
+/* Display the transfer block's PSP_info data */
+void show_psp_transfer_info(void);
+/* Called by bootblock_c_entry in the VBOOT_STARTS_BEFORE_BOOTBLOCK case */
+void boot_with_psp_timestamp(uint64_t base_timestamp);
+
+#endif
#endif /* AMD_CEZANNE_PSP_TRANSFER_H */
--
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Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/52539 )
Change subject: soc/amd/cezanne: copy Kconfig options for psp_verstage
......................................................................
soc/amd/cezanne: copy Kconfig options for psp_verstage
These are just copied from picasso one.
Signed-off-by: Kangheui Won <khwon(a)chromium.org>
Change-Id: I701d6af63b24e86f8e132fad73504e20148a2bf3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52539
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
Reviewed-by: Felix Held <felix-coreboot(a)felixheld.de>
---
M src/soc/amd/cezanne/Kconfig
1 file changed, 72 insertions(+), 1 deletion(-)
Approvals:
build bot (Jenkins): Verified
Felix Held: Looks good to me, approved
diff --git a/src/soc/amd/cezanne/Kconfig b/src/soc/amd/cezanne/Kconfig
index ccdc7b7..3b9bb5f 100644
--- a/src/soc/amd/cezanne/Kconfig
+++ b/src/soc/amd/cezanne/Kconfig
@@ -11,7 +11,7 @@
def_bool y
select ACPI_SOC_NVS
select ARCH_BOOTBLOCK_X86_32
- select ARCH_VERSTAGE_X86_32
+ select ARCH_VERSTAGE_X86_32 if !VBOOT_STARTS_BEFORE_BOOTBLOCK
select ARCH_ROMSTAGE_X86_32
select ARCH_RAMSTAGE_X86_32
select BOOT_DEVICE_SUPPORTS_WRITES if BOOT_DEVICE_SPI_FLASH
@@ -93,6 +93,27 @@
Location in DRAM where the PSP will copy the AGESA PSP Output
Block.
+config PSP_SHAREDMEM_BASE
+ hex
+ default 0x2011000 if VBOOT
+ default 0x0
+ help
+ This variable defines the base address in DRAM memory where PSP copies
+ the vboot workbuf. This is used in the linker script to have a static
+ allocation for the buffer as well as for adding relevant entries in
+ the BIOS directory table for the PSP.
+
+config PSP_SHAREDMEM_SIZE
+ hex
+ default 0x8000 if VBOOT
+ default 0x0
+ help
+ Sets the maximum size for the PSP to pass the vboot workbuf and
+ any logs or timestamps back to coreboot. This will be copied
+ into main memory by the PSP and will be available when the x86 is
+ started. The workbuf's base depends on the address of the reset
+ vector.
+
config PRERAM_CBMEM_CONSOLE_SIZE
hex
default 0x1600
@@ -337,10 +358,60 @@
See #55758 (NDA) for additional bit definitions.
+config PSP_VERSTAGE_FILE
+ string "Specify the PSP_verstage file path"
+ depends on VBOOT_STARTS_BEFORE_BOOTBLOCK
+ default "$(obj)/psp_verstage.bin"
+ help
+ Add psp_verstage file to the build & PSP Directory Table
+
+config PSP_VERSTAGE_SIGNING_TOKEN
+ string "Specify the PSP_verstage Signature Token file path"
+ depends on VBOOT_STARTS_BEFORE_BOOTBLOCK
+ default ""
+ help
+ Add psp_verstage signature token to the build & PSP Directory Table
+
endmenu
config VBOOT
select VBOOT_VBNV_CMOS
select VBOOT_VBNV_CMOS_BACKUP_TO_FLASH
+config VBOOT_STARTS_BEFORE_BOOTBLOCK
+ def_bool n
+ depends on VBOOT
+ select ARCH_VERSTAGE_ARMV7
+ help
+ Runs verstage on the PSP. Only available on
+ certain Chrome OS branded parts from AMD.
+
+config VBOOT_HASH_BLOCK_SIZE
+ hex
+ default 0x9000
+ depends on VBOOT_STARTS_BEFORE_BOOTBLOCK
+ help
+ Because the bulk of the time in psp_verstage to hash the RO cbfs is
+ spent in the overhead of doing svc calls, increasing the hash block
+ size significantly cuts the verstage hashing time as seen below.
+
+ 4k takes 180ms
+ 16k takes 44ms
+ 32k takes 33.7ms
+ 36k takes 32.5ms
+ There's actually still room for an even bigger stack, but we've
+ reached a point of diminishing returns.
+
+config CMOS_RECOVERY_BYTE
+ hex
+ default 0x51
+ depends on VBOOT_STARTS_BEFORE_BOOTBLOCK
+ help
+ If the workbuf is not passed from the PSP to coreboot, set the
+ recovery flag and reboot. The PSP will read this byte, mark the
+ recovery request in VBNV, and reset the system into recovery mode.
+
+ This is the byte before the default first byte used by VBNV
+ (0x26 + 0x0E - 1)
+
endif # SOC_AMD_CEZANNE
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Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52522 )
Change subject: cpu/x86/mtrr: Use a Kconfig for reserving MTRRs for OS
......................................................................
Patch Set 8:
(1 comment)
Patchset:
PS8:
Any other thoughts on this?
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Change subject: drivers/genesyslogic/gl9755: Disable the debug mode of short circuit protection
......................................................................
Patch Set 2:
(2 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/51000/comment/fb96c7d1_3ea35d16
PS1, Line 10: debug mode needs to be turned off.
> No, SCP debug mode bit is not in the current datasheet. […]
Ack
Patchset:
PS2:
Ben, do you mind updating the commit msg?
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Change subject: mb/google/volteer/variant/lindar: Modify ELAN touch screen IRQ trigger method
......................................................................
Patch Set 3: Code-Review+2
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Change subject: cpu/x86/msr: introduce helpers msr_read, msr_write
......................................................................
Patch Set 5: Code-Review+1
(1 comment)
File src/include/cpu/x86/msr.h:
https://review.coreboot.org/c/coreboot/+/52548/comment/6f5451cb_79bb0942
PS5, Line 323: unsigned int
i was wondering why this is not uint32_t, but this matches the definition of the fields of msr_t. not 100% sure if it would be a good idea to change the msr_t element data types from unsigned int to uint32_t, but that would be someting for a follow-up patch, since it's out of scope for this one
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Change subject: mb/google/brya: Add CHROMEOS_DRAM_PART_NUMBER_IN_CBI
......................................................................
Patch Set 2:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/52726/comment/05654acc_0acc9a79
PS1, Line 9: is use
> uses
whoops, my poor english
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