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Change subject: sc7280: Add GSI FW download support
......................................................................
sc7280: Add GSI FW download support
Add GSI Firmware download support for QUP wrappers.
Change-Id: I8b966a6a074fc43c62d2639da9cf68b083cc7319
Signed-off-by: Roja Rani Yarubandi <rojay(a)codeaurora.org>
---
M src/soc/qualcomm/sc7280/Makefile.inc
M src/soc/qualcomm/sc7280/include/soc/addressmap.h
M src/soc/qualcomm/sc7280/include/soc/qcom_qup_se.h
M src/soc/qualcomm/sc7280/include/soc/qupv3_config.h
M src/soc/qualcomm/sc7280/qupv3_config.c
5 files changed, 132 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/71/52371/5
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Change subject: drivers/i2c/designware: Use safe defaults for SCL parameters
......................................................................
Patch Set 1: Code-Review+1
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/52723/comment/2d93680e_6683fe64
PS1, Line 11: If I2C bus step response has not been measured, assume
: the layout to be designed with a minimal capacitance and
: SCL rise and fall times of 0 ns. The calculations will
: add the required amount of reference clocks for the host
: to drive SCL high or low, such that the maximum bus
: frequency specification is met.
nit: fill this out to 72 chars wide
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Change subject: [Do Not Merge] [Test] mb/google/terrador: Disable SaGv
......................................................................
Patch Set 1:
(1 comment)
File src/mainboard/google/volteer/variants/terrador/overridetree.cb:
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-117985):
https://review.coreboot.org/c/coreboot/+/52738/comment/029ae6c0_b2a1480f
PS1, Line 19:
trailing whitespace
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Hello Bora Guvendik, Shaunak Saha, build bot (Jenkins), Wonkyu Kim, Selma Bensaid, Maulik V Vaghela, Jack Rosenthal, Subrata Banik, Bernardo Perez Priego, Anil Kumar K, Varshit B Pandya, Jamie Ryu, Nathan D Ciobanu,
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Change subject: mb/intel/adlrvp: Set SKU ID string for adlrvp to NULL
......................................................................
mb/intel/adlrvp: Set SKU ID string for adlrvp to NULL
The SKU ID parameter in /run/chromeos-config/private/v1/identity.json is set to 255
With this change any SKU ID results in a match and cros_config works OK.
Branch=None
Test=build and boot ADL-M RVP. On DUT execute cros_config / name outputs "adlrvp"
Signed-off-by: Anil Kumar <anil.kumar.k(a)intel.com>
Change-Id: I8e501f995988b95c480637599412c8ddea0814dc
---
M src/mainboard/intel/adlrvp/mainboard.c
1 file changed, 0 insertions(+), 3 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/81/52681/2
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Change subject: doc/relnotes/4.14: add Intel Xeon-SP support status change
......................................................................
Patch Set 1:
(2 comments)
File Documentation/releases/coreboot-4.14-relnotes.md:
https://review.coreboot.org/c/coreboot/+/52735/comment/99bdf04b_dccc55b4
PS1, Line 55: Sacalable
Scalable
https://review.coreboot.org/c/coreboot/+/52735/comment/1d40268e_e46dcc9b
PS1, Line 58: of
of the?
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Change subject: amd/cezanne: Add telemetry setting to UPD
......................................................................
Patch Set 1:
(1 comment)
File src/soc/amd/cezanne/chip.h:
https://review.coreboot.org/c/coreboot/+/52733/comment/f9558ad4_9de3b6c3
PS1, Line 73: uint32_t telemetry_vddcrvddfull_scale_current;
i'd add _mA to match picasso and have the unit right in the struct element name; same in line 75
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Change subject: amd/cezanne: Add telemetry setting to UPD
......................................................................
Patch Set 1:
(1 comment)
File src/soc/amd/cezanne/fsp_m_params.c:
https://review.coreboot.org/c/coreboot/+/52733/comment/aa0fe84d_b5947d74
PS1, Line 121: /* telemetry settings */
"voltage regulator telemetry settings" would be more specific here
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Change subject: amd/cezanne: Add telemetry setting to UPD
......................................................................
Patch Set 1:
(1 comment)
File src/vendorcode/amd/fsp/cezanne/FspmUpd.h:
https://review.coreboot.org/c/coreboot/+/52733/comment/671f4a83_387b2d7e
PS1, Line 106: 0x04C7
see my comment about the alignment on the fsp-side patch. if you add one empty byte before this, the fields won't be unaligned
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Change subject: mb/google/mancomb: Add STAPM values to overridetree
......................................................................
Patch Set 1:
(1 comment)
File src/mainboard/google/mancomb/variants/mancomb/overridetree.cb:
https://review.coreboot.org/c/coreboot/+/52709/comment/c9559251_7725b5b7
PS1, Line 3: register "system_configuration" = "3"
This isn't wrong here, but it should go in the top level devicetree since it's going to be the same for all the mancomb platforms.
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