coreboot-gerrit April 2021

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Change in coreboot[master]: mb/google/guybrush: Remove the GPIO_SIGN_OF_LIFE code
by Raul Rangel (Code Review) 30 Apr '21

30 Apr '21

Attention is currently required from: Martin Roth, Mathew King. Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52740 ) Change subject: mb/google/guybrush: Remove the GPIO_SIGN_OF_LIFE code ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/52740 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I14f89f3e6f780c2da2136a838950ef2bcebc4c3a Gerrit-Change-Number: 52740 Gerrit-PatchSet: 1 Gerrit-Owner: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Mathew King <mathewk(a)chromium.org> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Mathew King <mathewk(a)chromium.org> Gerrit-Comment-Date: Thu, 29 Apr 2021 15:09:15 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/mancomb: Add SPI configuration to Kconfig
by Raul Rangel (Code Review) 30 Apr '21

30 Apr '21

Attention is currently required from: Martin Roth, Matt Papageorge. Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52741 ) Change subject: mb/google/mancomb: Add SPI configuration to Kconfig ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/52741 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icacb68d65fb414197d7b8d45799527d8d2568dc7 Gerrit-Change-Number: 52741 Gerrit-PatchSet: 2 Gerrit-Owner: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Matt Papageorge <matthewpapa07(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Matt Papageorge <matthewpapa07(a)gmail.com> Gerrit-Comment-Date: Thu, 29 Apr 2021 15:08:58 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/brya: select GOOGLE_SMBIOS_MAINBOARD_VERSION
by Tim Wawrzynczak (Code Review) 30 Apr '21

30 Apr '21

Attention is currently required from: Zhuohao Lee. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52754 ) Change subject: mb/google/brya: select GOOGLE_SMBIOS_MAINBOARD_VERSION ...................................................................... Patch Set 1: Code-Review+2 (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/52754/comment/fb856243_1c46fc84 PS1, Line 9: In order to use the function smbios_mainboard_version() : to query the board revision from the EC. : we need to select GOOGLE_SMBIOS_MAINBOARD_VERSION. suggestion: selectin GOOGLE_SMBIOS_MAINBOARD_VERSION allows querying board revision from the EC. -- To view, visit https://review.coreboot.org/c/coreboot/+/52754 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8eeb958f73607afb801794f91fbf91ec7bd5cd8b Gerrit-Change-Number: 52754 Gerrit-PatchSet: 1 Gerrit-Owner: Zhuohao Lee <zhuohao(a)chromium.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Zhuohao Lee <zhuohao(a)chromium.org> Gerrit-Comment-Date: Thu, 29 Apr 2021 15:02:55 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/guybrush: Set system_config to 2 for guybrush boards
by Martin Roth (Code Review) 30 Apr '21

30 Apr '21

Martin Roth has submitted this change. ( https://review.coreboot.org/c/coreboot/+/52680 ) Change subject: mb/google/guybrush: Set system_config to 2 for guybrush boards ...................................................................... mb/google/guybrush: Set system_config to 2 for guybrush boards All guybrush boards should have system_configuration set to 2, so put this in the main devicetree. BUG=b:185209734 TEST=Build & Boot guybrush Signed-off-by: Martin Roth <martinroth(a)chromium.org> Change-Id: I1ce2acb3b4ed51aa9a0aa379ed125f0b04f04d31 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52680 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Raul Rangel <rrangel(a)chromium.org> Reviewed-by: chris wang <Chris.Wang(a)amd.com> --- M src/mainboard/google/guybrush/variants/baseboard/devicetree.cb 1 file changed, 2 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Raul Rangel: Looks good to me, approved chris wang: Looks good to me, but someone else must approve diff --git a/src/mainboard/google/guybrush/variants/baseboard/devicetree.cb b/src/mainboard/google/guybrush/variants/baseboard/devicetree.cb index 305dfbf..b0bfa96 100644 --- a/src/mainboard/google/guybrush/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/guybrush/variants/baseboard/devicetree.cb @@ -41,6 +41,8 @@ # Enable S0i3 support register "s0ix_enable" = "1" + register "system_configuration" = "2" + register "i2c_scl_reset" = "GPIO_I2C0_SCL | GPIO_I2C1_SCL | GPIO_I2C2_SCL | GPIO_I2C3_SCL" -- To view, visit https://review.coreboot.org/c/coreboot/+/52680 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1ce2acb3b4ed51aa9a0aa379ed125f0b04f04d31 Gerrit-Change-Number: 52680 Gerrit-PatchSet: 3 Gerrit-Owner: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: chris wang <Chris.Wang(a)amd.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/google/guybrush: Set system_config to 2 for guybrush boards
by Martin Roth (Code Review) 30 Apr '21

30 Apr '21

Attention is currently required from: Paul Menzel, Felix Held. Martin Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52680 ) Change subject: mb/google/guybrush: Set system_config to 2 for guybrush boards ...................................................................... Patch Set 2: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/52680/comment/8844820e_093c1c91 PS1, Line 9: system_config > Nit: Use the longer term here: system_configuration? Done https://review.coreboot.org/c/coreboot/+/52680/comment/2be4eaf0_bc742ca0 PS1, Line 11: > What bug does this fix? Besides the FSP UPD I didn’t find anything in the source. It doesn't fix a "bug". It's just telling AGESA to set power config 2, which, of course, is only documented in NDA documentation. :-( -- To view, visit https://review.coreboot.org/c/coreboot/+/52680 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1ce2acb3b4ed51aa9a0aa379ed125f0b04f04d31 Gerrit-Change-Number: 52680 Gerrit-PatchSet: 2 Gerrit-Owner: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: chris wang <Chris.Wang(a)amd.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Thu, 29 Apr 2021 15:02:08 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/guybrush: Set system_config to 2 for guybrush boards
by Martin Roth (Code Review) 30 Apr '21

30 Apr '21

Attention is currently required from: Martin Roth, Felix Held. Hello build bot (Jenkins), Raul Rangel, chris wang, Felix Held, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/52680 to look at the new patch set (#2). Change subject: mb/google/guybrush: Set system_config to 2 for guybrush boards ...................................................................... mb/google/guybrush: Set system_config to 2 for guybrush boards All guybrush boards should have system_configuration set to 2, so put this in the main devicetree. BUG=b:185209734 TEST=Build & Boot guybrush Signed-off-by: Martin Roth <martinroth(a)chromium.org> Change-Id: I1ce2acb3b4ed51aa9a0aa379ed125f0b04f04d31 --- M src/mainboard/google/guybrush/variants/baseboard/devicetree.cb 1 file changed, 2 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/80/52680/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/52680 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1ce2acb3b4ed51aa9a0aa379ed125f0b04f04d31 Gerrit-Change-Number: 52680 Gerrit-PatchSet: 2 Gerrit-Owner: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: chris wang <Chris.Wang(a)amd.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/google/mancomb: Remove lid swtich
by Karthik Ramasubramanian (Code Review) 30 Apr '21

30 Apr '21

Attention is currently required from: Furquan Shaikh, Ivy Jian. Karthik Ramasubramanian has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52602 ) Change subject: mb/google/mancomb: Remove lid swtich ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/52602 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifd0fcec9557bf7ebad64ce9342d3b50eb511522b Gerrit-Change-Number: 52602 Gerrit-PatchSet: 2 Gerrit-Owner: Ivy Jian <ivy_jian(a)compal.corp-partner.google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Mathew King <mathewk(a)chromium.org> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Ivy Jian <ivy_jian(a)compal.corp-partner.google.com> Gerrit-Comment-Date: Thu, 29 Apr 2021 14:58:44 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: cpu/x86/mtrr: Use a Kconfig for reserving MTRRs for OS
by Tim Wawrzynczak (Code Review) 30 Apr '21

30 Apr '21

Tim Wawrzynczak has submitted this change. ( https://review.coreboot.org/c/coreboot/+/52522 ) Change subject: cpu/x86/mtrr: Use a Kconfig for reserving MTRRs for OS ...................................................................... cpu/x86/mtrr: Use a Kconfig for reserving MTRRs for OS Some platforms which have large amounts of RAM and also write-combining regions may decide to drop the WC regions in favor of the default when preserving MTRRs for the OS. From a data safety perspective, this is safe to do, but if, say, the graphics framebuffer is the region that is changed from WC to UC/WB, then the performance of writing to the framebuffer will decrease dramatically. Modern OSes typically use Page Attribute Tables (PAT) to determine the cacheability on a page level and usually do not touch the MTRRs. Thus, it is believed to be safe to stop reserving MTRRs for the OS, in general; PentiumII is the exception here in that OSes that still support that may still require MTRRs to be available. In any case, if the OS wants to reprogram all of the MTRRs, it is of course still free to do so (after consulting the e820 table). BUG=b:185452338 TEST=Verify MTRR programming on a brya (where `sa_add_dram_resources` was faked to think it had 32 GiB of DRAM installed) and variable MTRR map includes a WC entry for the framebuffer (and all the RAM): MTRR: default type WB/UC MTRR counts: 13/9. MTRR: UC selected as default type. MTRR: 0 base 0x0000000000000000 mask 0x00003fff80000000 type 6 MTRR: 1 base 0x0000000077000000 mask 0x00003fffff000000 type 0 MTRR: 2 base 0x0000000078000000 mask 0x00003ffff8000000 type 0 MTRR: 3 base 0x0000000090000000 mask 0x00003ffff0000000 type 1 MTRR: 4 base 0x0000000100000000 mask 0x00003fff00000000 type 6 MTRR: 5 base 0x0000000200000000 mask 0x00003ffe00000000 type 6 MTRR: 6 base 0x0000000400000000 mask 0x00003ffc00000000 type 6 MTRR: 7 base 0x0000000800000000 mask 0x00003fff80000000 type 6 MTRR: 8 base 0x000000087fc00000 mask 0x00003fffffc00000 type 0 ADL has 9 variable-range MTRRs, previously 8 of them were used, and there was no separate entry for the framebuffer, thus leaving the default MTRR in place of uncached. Change-Id: I2ae2851248c95fd516627b101ebcb36ec59c29c3 Signed-off-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52522 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> Reviewed-by: Furquan Shaikh <furquan(a)google.com> --- M src/cpu/intel/slot_1/Kconfig M src/cpu/x86/Kconfig M src/cpu/x86/mtrr/mtrr.c 3 files changed, 30 insertions(+), 12 deletions(-) Approvals: build bot (Jenkins): Verified Furquan Shaikh: Looks good to me, approved Angel Pons: Looks good to me, approved diff --git a/src/cpu/intel/slot_1/Kconfig b/src/cpu/intel/slot_1/Kconfig index cc24833..c30e066 100644 --- a/src/cpu/intel/slot_1/Kconfig +++ b/src/cpu/intel/slot_1/Kconfig @@ -17,6 +17,7 @@ select TSC_MONOTONIC_TIMER select UNKNOWN_TSC_RATE select SETUP_XIP_CACHE + select RESERVE_MTRRS_FOR_OS config DCACHE_RAM_BASE hex diff --git a/src/cpu/x86/Kconfig b/src/cpu/x86/Kconfig index 5394cd0..bcaf0bf 100644 --- a/src/cpu/x86/Kconfig +++ b/src/cpu/x86/Kconfig @@ -160,3 +160,13 @@ help The SoC requires different access methods for reading and writing the MSRs. Use SoC specific routines to handle the MSR access. + +config RESERVE_MTRRS_FOR_OS + bool + default n + help + This option allows a platform to reserve 2 MTRRs for the OS usage. + The Intel SDM documents that the the first 6 MTRRs are intended for + the system BIOS and the last 2 are to be reserved for OS usage. + However, modern OSes use PAT to control cacheability instead of + using MTRRs. diff --git a/src/cpu/x86/mtrr/mtrr.c b/src/cpu/x86/mtrr/mtrr.c index cb7ecdc..f1d36da 100644 --- a/src/cpu/x86/mtrr/mtrr.c +++ b/src/cpu/x86/mtrr/mtrr.c @@ -28,10 +28,8 @@ #define MTRR_FIXED_WRBACK_BITS 0 #endif -/* 2 MTRRS are reserved for the operating system */ -#define BIOS_MTRRS 6 -#define OS_MTRRS 2 -#define MTRRS (BIOS_MTRRS + OS_MTRRS) +#define MIN_MTRRS 8 + /* * Static storage size for variable MTRRs. It's sized sufficiently large to * handle different types of CPUs. Empirically, 16 variable MTRRs has not @@ -39,8 +37,7 @@ */ #define NUM_MTRR_STATIC_STORAGE 16 -static int total_mtrrs = MTRRS; -static int bios_mtrrs = BIOS_MTRRS; +static int total_mtrrs; static void detect_var_mtrrs(void) { @@ -56,7 +53,6 @@ total_mtrrs, NUM_MTRR_STATIC_STORAGE); total_mtrrs = NUM_MTRR_STATIC_STORAGE; } - bios_mtrrs = total_mtrrs - OS_MTRRS; } void enable_fixed_mtrr(void) @@ -399,6 +395,11 @@ wrmsr(MTRR_PHYS_MASK(index), msr); } +static int get_os_reserved_mtrrs(void) +{ + return CONFIG(RESERVE_MTRRS_FOR_OS) ? 2 : 0; +} + static void prep_var_mtrr(struct var_mtrr_state *var_state, uint64_t base, uint64_t size, int mtrr_type) { @@ -407,17 +408,20 @@ resource_t rsize; resource_t mask; - /* Some variable MTRRs are attempted to be saved for the OS use. - * However, it's more important to try to map the full address space - * properly. */ - if (var_state->mtrr_index >= bios_mtrrs) - printk(BIOS_WARNING, "Taking a reserved OS MTRR.\n"); if (var_state->mtrr_index >= total_mtrrs) { printk(BIOS_ERR, "ERROR: Not enough MTRRs available! MTRR index is %d with %d MTRRs in total.\n", var_state->mtrr_index, total_mtrrs); return; } + /* + * If desired, 2 variable MTRRs are attempted to be saved for the OS to + * use. However, it's more important to try to map the full address + * space properly. + */ + if (var_state->mtrr_index >= total_mtrrs - get_os_reserved_mtrrs()) + printk(BIOS_WARNING, "Taking a reserved OS MTRR.\n"); + rbase = base; rsize = size; @@ -710,6 +714,7 @@ __calc_var_mtrrs(addr_space, above4gb, address_bits, &wb_deftype_count, &uc_deftype_count); + const int bios_mtrrs = total_mtrrs - get_os_reserved_mtrrs(); if (wb_deftype_count > bios_mtrrs && uc_deftype_count > bios_mtrrs) { printk(BIOS_DEBUG, "MTRR: Removing WRCOMB type. " "WB/UC MTRR counts: %d/%d > %d.\n", @@ -813,6 +818,8 @@ void x86_setup_mtrrs(void) { + /* Without detect, assume the minimum */ + total_mtrrs = MIN_MTRRS; /* Always handle addresses above 4GiB. */ _x86_setup_mtrrs(1); } -- To view, visit https://review.coreboot.org/c/coreboot/+/52522 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2ae2851248c95fd516627b101ebcb36ec59c29c3 Gerrit-Change-Number: 52522 Gerrit-PatchSet: 9 Gerrit-Owner: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Stefan Reinauer <reinauer(a)chromium.org> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/intel/adlrvp: Increase RO/RW region size in chromeos.fmd
by Tim Wawrzynczak (Code Review) 30 Apr '21

30 Apr '21

Attention is currently required from: Maulik V Vaghela. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52732 ) Change subject: mb/intel/adlrvp: Increase RO/RW region size in chromeos.fmd ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/52732 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I644e2e5ba06d2b816d413a7cc9f5f248d8a6fee8 Gerrit-Change-Number: 52732 Gerrit-PatchSet: 3 Gerrit-Owner: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-CC: Spoorthi K <spoorthi.k(a)intel.com> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Comment-Date: Thu, 29 Apr 2021 14:50:45 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/amd/picasso: Move Type 17 DMI generation to common
by Raul Rangel (Code Review) 30 Apr '21

30 Apr '21

Attention is currently required from: Jason Glenesk, Marshall Dawson, Nikolai Vyssotski, Felix Held. Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52746 ) Change subject: soc/amd/picasso: Move Type 17 DMI generation to common ...................................................................... Patch Set 2: (2 comments) File src/soc/amd/common/Kconfig.common: https://review.coreboot.org/c/coreboot/+/52746/comment/b3476b7c_01d656dd PS2, Line 11: _ Add a _COMMON File src/soc/amd/common/fsp/Makefile.inc: https://review.coreboot.org/c/coreboot/+/52746/comment/32ff16ec_e2f11a26 PS2, Line 7: ramstage-y How about `ramstage-$(CONFIG_SOC_AMD_FSP_DMI_TABLES)` += -- To view, visit https://review.coreboot.org/c/coreboot/+/52746 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I46071556bbbbf6435d9e3724bba19e102bd02535 Gerrit-Change-Number: 52746 Gerrit-PatchSet: 2 Gerrit-Owner: Nikolai Vyssotski <nikolai.vyssotski(a)amd.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Rob Barnes <robbarnes(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Nikolai Vyssotski <nikolai.vyssotski(a)amd.corp-partner.google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Thu, 29 Apr 2021 14:46:24 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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coreboot-gerrit April 2021