coreboot-gerrit April 2021

coreboot-gerrit@coreboot.org

1 participants
6269 discussions

Change in coreboot[master]: device/dram: Add support for LPDDR4 4266
by Rob Barnes (Code Review) 29 Apr '21

29 Apr '21

Attention is currently required from: Marshall Dawson, Nikolai Vyssotski, Felix Held. Rob Barnes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52745 ) Change subject: device/dram: Add support for LPDDR4 4266 ...................................................................... Patch Set 2: (3 comments) File src/device/dram/ddr4.c: https://review.coreboot.org/c/coreboot/+/52745/comment/ca7415f6_8211f68e PS2, Line 173: /* check for matching DDR4 speed first */ Can we split this into two functions (ddr4, lpddr4) and require the caller to call the right one based on DMI_T17_MEMORY_TYPE? Is this field sometimes wrong? https://review.coreboot.org/c/coreboot/+/52745/comment/09eb2d46_70d7f1de PS2, Line 175: sizeof(ddr4_speeds)/sizeof(ddr4_speeds[0])); > Prefer ARRAY_SIZE(ddr4_speeds) Please fix. https://review.coreboot.org/c/coreboot/+/52745/comment/dae31b35_2ac6b216 PS2, Line 181: sizeof(lpddr4_speeds)/sizeof(lpddr4_speeds[0])); > Prefer ARRAY_SIZE(lpddr4_speeds) Please fix. -- To view, visit https://review.coreboot.org/c/coreboot/+/52745 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id8ddfc98fff4255670c50e1ddd4d0a1326265772 Gerrit-Change-Number: 52745 Gerrit-PatchSet: 2 Gerrit-Owner: Nikolai Vyssotski <nikolai.vyssotski(a)amd.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Rob Barnes <robbarnes(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Nikolai Vyssotski <nikolai.vyssotski(a)amd.corp-partner.google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Thu, 29 Apr 2021 13:28:05 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Change in coreboot[master]: security/tpm/crtm: Measure FMAP into TPM
by Angel Pons (Code Review) 29 Apr '21

29 Apr '21

Attention is currently required from: Philipp Deppenwiese, Christian Walter, Julius Werner, Arthur Heymans. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52753 ) Change subject: security/tpm/crtm: Measure FMAP into TPM ...................................................................... Patch Set 2: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/52753 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic424a094e7f790cce45c5a98b8bc6d46a8dcca1b Gerrit-Change-Number: 52753 Gerrit-PatchSet: 2 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Thu, 29 Apr 2021 13:22:32 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

Change in coreboot[master]: soc/amd/picasso/dmi.c: Fix builds for boards without Google EC
by Rob Barnes (Code Review) 29 Apr '21

29 Apr '21

Attention is currently required from: Jason Glenesk, Raul Rangel, Marshall Dawson, Nikolai Vyssotski, Felix Held. Rob Barnes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52748 ) Change subject: soc/amd/picasso/dmi.c: Fix builds for boards without Google EC ...................................................................... Patch Set 1: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/52748 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2b200f4fb11513c6fc17a2f0af3e12e5a3e3e5a1 Gerrit-Change-Number: 52748 Gerrit-PatchSet: 1 Gerrit-Owner: Nikolai Vyssotski <nikolai.vyssotski(a)amd.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Rob Barnes <robbarnes(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Nikolai Vyssotski <nikolai.vyssotski(a)amd.corp-partner.google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Thu, 29 Apr 2021 13:21:43 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

Change in coreboot[master]: ChromeOS: Separate NVS from global GNVS
by Kyösti Mälkki (Code Review) 29 Apr '21

29 Apr '21

Attention is currently required from: Lance Zhao, Tim Wawrzynczak, Angel Pons. Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/51638 ) Change subject: ChromeOS: Separate NVS from global GNVS ...................................................................... Patch Set 4: (4 comments) File src/acpi/gnvs.c: https://review.coreboot.org/c/coreboot/+/51638/comment/a7c6c8ae_c841e5d7 PS4, Line 43: chromeos_init_chromeos_acpi > am I missing something? doesn't this patch effectively drop generating chromeos nvs? Looks like I somehow removed [WIP] with rebase. The question is if we should split the initialisation or not. File src/vendorcode/google/chromeos/gnvs.c: https://review.coreboot.org/c/coreboot/+/51638/comment/0f2b0370_438d7d7d PS4, Line 33: static __unused void chromeos_init_chromeos_acpi(void) > Who should call this? That's the question, should the call be inside acpi/gnvs.c which creates dependency on ACPI_SOC_NVS which is inaccurate. (Does not really hurt though). https://review.coreboot.org/c/coreboot/+/51638/comment/929657d2_d05bfd77 PS4, Line 38: chromeos_acpi = cbmem_add(CBMEM_ID_ACPI_GNVS, sizeof(struct chromeos_acpi)); Needs new ID. https://review.coreboot.org/c/coreboot/+/51638/comment/e5460264_8ae02315 PS4, Line 96: static __unused void acpi_fill_cnvs(void) > Who should call this? I was thinking inside vc/google/chromeos/acpi.c:chromeos_dsdt_generator(). Then I realised that calling chromeos_dsdt_generator() from inside mb/ is somewhat pointless as the implementation is not tied to passed dev pointer. And should we query the acpi name with that node, we would not get to Device (CHRW) that this NVS is related to. -- To view, visit https://review.coreboot.org/c/coreboot/+/51638 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ide55964ed53ea1d5b3c1c4e3ebd67286b7d568e4 Gerrit-Change-Number: 51638 Gerrit-PatchSet: 4 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Lance Zhao Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Lance Zhao Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Comment-Date: Thu, 29 Apr 2021 12:51:37 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

1 0

Change in coreboot[master]: amdfwtool: Allocate a little more space for each table
by Bao Zheng (Code Review) 29 Apr '21

29 Apr '21

Attention is currently required from: Zheng Bao. Hello Zheng Bao, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/52756 to review the following change. Change subject: amdfwtool: Allocate a little more space for each table ...................................................................... amdfwtool: Allocate a little more space for each table The AMD tools need to replace or add FW(s) of an image. The total size of each table is specified in header and can not be changed, because the tools don't know what is outside the table. If the new table needs more space, the replacing can not be executed. So we give some extra space for flexibility. Change-Id: Id18db19c711b1ff7e694041408a5c4d30a9384ca Signed-off-by: Zheng Bao <fishbaozi(a)gmail.com> --- M util/amdfwtool/amdfwtool.c 1 file changed, 3 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/56/52756/1 diff --git a/util/amdfwtool/amdfwtool.c b/util/amdfwtool/amdfwtool.c index 403785e..1435efe 100644 --- a/util/amdfwtool/amdfwtool.c +++ b/util/amdfwtool/amdfwtool.c @@ -71,6 +71,7 @@ #define BLOB_ALIGNMENT 0x100U #define TABLE_ERASE_ALIGNMENT _MAX(TABLE_ALIGNMENT, ERASE_ALIGNMENT) #define BLOB_ERASE_ALIGNMENT _MAX(BLOB_ALIGNMENT, ERASE_ALIGNMENT) +#define TABLE_REDUNDANCE (2 * TABLE_ALIGNMENT) #define DEFAULT_SOFT_FUSE_CHAIN "0x1" @@ -531,7 +532,7 @@ break; case PSP_COOKIE: case PSPL2_COOKIE: - table_size = ctx->current - dir->header.additional_info; + table_size = ctx->current - dir->header.additional_info + TABLE_REDUNDANCE; if ((table_size % TABLE_ALIGNMENT) != 0) { fprintf(stderr, "The PSP table size should be 4K aligned\n"); exit(1); @@ -547,7 +548,7 @@ break; case BDT1_COOKIE: case BDT2_COOKIE: - table_size = ctx->current - bdir->header.additional_info; + table_size = ctx->current - bdir->header.additional_info + TABLE_REDUNDANCE; if ((table_size % TABLE_ALIGNMENT) != 0) { fprintf(stderr, "The BIOS table size should be 4K aligned\n"); exit(1); -- To view, visit https://review.coreboot.org/c/coreboot/+/52756 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id18db19c711b1ff7e694041408a5c4d30a9384ca Gerrit-Change-Number: 52756 Gerrit-PatchSet: 1 Gerrit-Owner: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Zheng Bao Gerrit-Attention: Zheng Bao Gerrit-MessageType: newchange

1 0

Change in coreboot[master]: mb/google/dedede/var/boten: Modify DPTF parameters
by Stanley Wu (Code Review) 29 Apr '21

29 Apr '21

Stanley Wu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/52755 ) Change subject: mb/google/dedede/var/boten: Modify DPTF parameters ...................................................................... mb/google/dedede/var/boten: Modify DPTF parameters DPTF paramerters from thermal team. 1. Modify TSR1 sensor as charge sensor. 2. Modify P-state parameter BUG=b:180641150 BRANCH=dedede TEST=build and verified by thermal team. Change-Id: I43002db61de650d29cd85944a4eaea1b2f99aec4 Signed-off-by: Stanley Wu <stanley1.wu(a)lcfc.corp-partner.google.com> --- M src/mainboard/google/dedede/variants/boten/overridetree.cb 1 file changed, 36 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/55/52755/1 diff --git a/src/mainboard/google/dedede/variants/boten/overridetree.cb b/src/mainboard/google/dedede/variants/boten/overridetree.cb index f914b82..c496b63 100644 --- a/src/mainboard/google/dedede/variants/boten/overridetree.cb +++ b/src/mainboard/google/dedede/variants/boten/overridetree.cb @@ -87,15 +87,48 @@ register "policies.passive" = "{ [0] = DPTF_PASSIVE(CPU, CPU, 90, 10000), [1] = DPTF_PASSIVE(CPU, TEMP_SENSOR_0, 80, 60000), - [2] = DPTF_PASSIVE(CPU, TEMP_SENSOR_1, 55, 15000),}" + [2] = DPTF_PASSIVE(CHARGER, TEMP_SENSOR_1, 75, 15000) + }" + ## Critical Policy register "policies.critical" = "{ [0] = DPTF_CRITICAL(CPU, 105, SHUTDOWN), [1] = DPTF_CRITICAL(TEMP_SENSOR_0, 90, SHUTDOWN), - [2] = DPTF_CRITICAL(TEMP_SENSOR_1, 80, SHUTDOWN),}" + [2] = DPTF_CRITICAL(TEMP_SENSOR_1, 90, SHUTDOWN) + }" + + ## Power Limits Control + register "controls.power_limits" = "{ + .pl1 = { + .min_power = 3000, + .max_power = 6000, + .time_window_min = 1 * MSECS_PER_SEC, + .time_window_max = 1 * MSECS_PER_SEC, + .granularity = 200, + }, + .pl2 = { + .min_power = 20000, + .max_power = 20000, + .time_window_min = 1 * MSECS_PER_SEC, + .time_window_max = 1 * MSECS_PER_SEC, + .granularity = 1000, + } + }" + + register "options.tsr[0].desc" = ""Memory"" + register "options.tsr[1].desc" = ""Charger"" + + ## Charger Performance Control (Control, mA) + register "controls.charger_perf" = "{ + [0] = { 255, 3000 }, + [1] = { 24, 2000 }, + [2] = { 16, 1500 }, + [3] = { 8, 1000 } + }" + device generic 0 on end end - end + end # SA Thermal device device pci 14.0 on chip drivers/usb/acpi register "desc" = ""Root Hub"" -- To view, visit https://review.coreboot.org/c/coreboot/+/52755 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I43002db61de650d29cd85944a4eaea1b2f99aec4 Gerrit-Change-Number: 52755 Gerrit-PatchSet: 1 Gerrit-Owner: Stanley Wu <stanley1.wu(a)lcfc.corp-partner.google.com> Gerrit-MessageType: newchange

1 0

Change in coreboot[master]: tests/lib/crc_byte-test: Fix incorrect variable types
by Jakub Czapiga (Code Review) 29 Apr '21

29 Apr '21

Attention is currently required from: Julius Werner, Jan Dabros. Hello build bot (Jenkins), Paul Fagerburg, Julius Werner, Jan Dabros, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/52708 to look at the new patch set (#2). Change subject: tests/lib/crc_byte-test: Fix incorrect variable types ...................................................................... tests/lib/crc_byte-test: Fix incorrect variable types Some crc16_byte() and crc32_byte() tests had uint8_t instead of uint16_t or uint32_t. That caused CRC values to be truncated and made tests incorrect. Also fix incorrect pre-calculated CRC values and change test buffer name to more the accurate. Signed-off-by: Jakub Czapiga <jacz(a)semihalf.com> Change-Id: I61ee029a6950a8dfeb54520b634eaf4ed6bac576 --- M tests/lib/crc_byte-test.c 1 file changed, 23 insertions(+), 20 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/08/52708/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/52708 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I61ee029a6950a8dfeb54520b634eaf4ed6bac576 Gerrit-Change-Number: 52708 Gerrit-PatchSet: 2 Gerrit-Owner: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: Jan Dabros <jsd(a)semihalf.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Paul Fagerburg <pfagerburg(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Jan Dabros <jsd(a)semihalf.com> Gerrit-MessageType: newpatchset

1 0

Change in coreboot[master]: mb/siemens/mc_apl{1,2,3,5,6}: Tune I2C frequency
by Mario Scheithauer (Code Review) 29 Apr '21

29 Apr '21

Attention is currently required from: Furquan Shaikh, Kyösti Mälkki, Werner Zeh. Mario Scheithauer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52721 ) Change subject: mb/siemens/mc_apl{1,2,3,5,6}: Tune I2C frequency ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: > It's not really setting the i2c speed twice, the second one is telling the provided SCL hcnt/lcnt ar […] oh understand, thanks for the clarification -- To view, visit https://review.coreboot.org/c/coreboot/+/52721 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iab634190bda5fa2a4fdf2ebaa1e45ac897d84deb Gerrit-Change-Number: 52721 Gerrit-PatchSet: 1 Gerrit-Owner: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Comment-Date: Thu, 29 Apr 2021 09:03:59 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Mario Scheithauer <mario.scheithauer(a)siemens.com> Comment-In-Reply-To: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: comment

1 0

Change in coreboot[master]: soc/amd/picasso: Add entry for PSP NVRAM data & RPMC data
by Bao Zheng (Code Review) 29 Apr '21

29 Apr '21

Attention is currently required from: Jason Glenesk, Raul Rangel, ritul guru, Zheng Bao, Felix Held. Bao Zheng has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/51836 ) Change subject: soc/amd/picasso: Add entry for PSP NVRAM data & RPMC data ...................................................................... Patch Set 8: (1 comment) Patchset: PS8: This need to be abandoned. -- To view, visit https://review.coreboot.org/c/coreboot/+/51836 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0e0c9d651b7c544eabbed8acc0d26ae55960ca3f Gerrit-Change-Number: 51836 Gerrit-PatchSet: 8 Gerrit-Owner: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Zheng Bao Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: ritul guru <ritul.bits(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: ritul guru <ritul.bits(a)gmail.com> Gerrit-Attention: Zheng Bao Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Thu, 29 Apr 2021 09:00:41 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Change in coreboot[master]: amdfwtool: Remove the misleading option characters
by Bao Zheng (Code Review) 29 Apr '21

29 Apr '21

Attention is currently required from: Martin Roth, Zheng Bao. Bao Zheng has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52657 ) Change subject: amdfwtool: Remove the misleading option characters ...................................................................... Patch Set 4: (1 comment) Patchset: PS4: > Why? How are these misleading? It's very common for programs to have both short and long options. […] the reason is that we are almost out of letters. and in future, more FW need to be added and more letters are needed. Even now many letters were picked at random. Maybe we should keep some short option like -h -d? -- To view, visit https://review.coreboot.org/c/coreboot/+/52657 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8b0d53d5e5eb494741b7fac32029cf16cabe66d8 Gerrit-Change-Number: 52657 Gerrit-PatchSet: 4 Gerrit-Owner: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Eric Peers <epeers(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Zheng Bao Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Zheng Bao Gerrit-Comment-Date: Thu, 29 Apr 2021 08:56:59 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Martin Roth <martinroth(a)google.com> Gerrit-MessageType: comment

1 0

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit April 2021