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Change subject: mb/google/guybrush: Set system_config to 2 for guybrush boards
......................................................................
Patch Set 1:
(2 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/52680/comment/9220166a_c73deeb2
PS1, Line 9: system_config
Nit: Use the longer term here: system_configuration?
https://review.coreboot.org/c/coreboot/+/52680/comment/aae7a3ab_3cf2e721
PS1, Line 11:
What bug does this fix? Besides the FSP UPD I didn’t find anything in the source.
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Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/52675 )
Change subject: ec/lenovo/h8/h8.c: Skip setting volume if out of range
......................................................................
ec/lenovo/h8/h8.c: Skip setting volume if out of range
This change is needed to update the option API to use unsigned integers.
The CMOS option system does not support negative numbers.
The volume field is only 8 bits long. Do not set the volume if it is out
of range. Also, use an out-of-range value as fallback to skip setting
the volume when it cannot be read using the option API, to preserve the
current behavior.
Change-Id: I7af68bb5c1ecd4489ab4b826b9a5e7999c77b1ff
Signed-off-by: Angel Pons <th3fanbus(a)gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52675
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
Reviewed-by: Patrick Rudolph <siro(a)das-labor.org>
Reviewed-by: Nico Huber <nico.h(a)gmx.de>
---
M src/ec/lenovo/h8/h8.c
1 file changed, 2 insertions(+), 2 deletions(-)
Approvals:
build bot (Jenkins): Verified
Nico Huber: Looks good to me, approved
Patrick Rudolph: Looks good to me, approved
diff --git a/src/ec/lenovo/h8/h8.c b/src/ec/lenovo/h8/h8.c
index be2eee6..e17f0fb 100644
--- a/src/ec/lenovo/h8/h8.c
+++ b/src/ec/lenovo/h8/h8.c
@@ -299,8 +299,8 @@
h8_trackpoint_enable(1);
h8_usb_power_enable(1);
- int volume = get_int_option("volume", -1);
- if (volume >= 0 && !acpi_is_wakeup_s3())
+ unsigned int volume = get_int_option("volume", ~0);
+ if (volume <= 0xff && !acpi_is_wakeup_s3())
ec_write(H8_VOLUME_CONTROL, volume);
val = (CONFIG(H8_SUPPORT_BT_ON_WIFI) || h8_has_bdc(dev)) &&
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Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/51775 )
Change subject: chromeec: Fix google_chromeec_status_check timeout
......................................................................
chromeec: Fix google_chromeec_status_check timeout
Rewrite google_chromeec_status_check to use stopwatch instead of a
delay in a while loop. In practice the while loop ends up taking
much longer than one second to timeout. Using stopwatch library will
accurately timeout after one second.
BUG=b:183524609
TEST=Build and run on guybrush
BRANCH=None
Change-Id: I363ff7453bcf81581884f92797629a6f96d42580
Signed-off-by: Rob Barnes <robbarnes(a)google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51775
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
Reviewed-by: Furquan Shaikh <furquan(a)google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org>
---
M src/ec/google/chromeec/ec_lpc.c
1 file changed, 13 insertions(+), 16 deletions(-)
Approvals:
build bot (Jenkins): Verified
Furquan Shaikh: Looks good to me, approved
Tim Wawrzynczak: Looks good to me, approved
diff --git a/src/ec/google/chromeec/ec_lpc.c b/src/ec/google/chromeec/ec_lpc.c
index b9c9728..3b2a746 100644
--- a/src/ec/google/chromeec/ec_lpc.c
+++ b/src/ec/google/chromeec/ec_lpc.c
@@ -7,6 +7,7 @@
#include <device/pnp.h>
#include <ec/google/common/mec.h>
#include <stdint.h>
+#include <timer.h>
#include "chip.h"
#include "ec.h"
@@ -92,23 +93,19 @@
static int google_chromeec_status_check(u16 port, u8 mask, u8 cond)
{
- u8 ec_status = read_byte(port);
- u32 time_count = 0;
+ struct stopwatch timeout_sw;
+ /* One second is more than plenty for any EC operation to complete */
+ const uint64_t ec_status_timeout_us = 1 * USECS_PER_SEC;
+ /* Wait 1 usec between read attempts */
+ const uint64_t ec_status_read_period_us = 1;
- /*
- * One second is more than plenty for any EC operation to complete
- * (and the bus accessing/code execution) overhead will make the
- * timeout even longer.
- */
-#define MAX_EC_TIMEOUT_US 1000000
-
- while ((ec_status & mask) != cond) {
- udelay(1);
- if (time_count++ == MAX_EC_TIMEOUT_US)
- return -1;
- ec_status = read_byte(port);
- }
- return 0;
+ stopwatch_init_usecs_expire(&timeout_sw, ec_status_timeout_us);
+ do {
+ if ((read_byte(port) & mask) == cond)
+ return 0;
+ udelay(ec_status_read_period_us);
+ } while (!stopwatch_expired(&timeout_sw));
+ return -1;
}
static int google_chromeec_wait_ready(u16 port)
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Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/52679 )
Change subject: docs/mb/supermicro/x11ssm-f: rework flashing section
......................................................................
docs/mb/supermicro/x11ssm-f: rework flashing section
The board can be flashed without adding a diode by just leaving VCC
unconnected. Rework the flashing section to describes that.
Change-Id: I37d55ffdbcfba4f3a1113a82f16ec8766bbb6e6c
Signed-off-by: Michael Niewöhner <foss(a)mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52679
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
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---
M Documentation/mainboard/supermicro/x11-lga1151-series/x11ssm-f/x11ssm-f.md
1 file changed, 8 insertions(+), 3 deletions(-)
Approvals:
build bot (Jenkins): Verified
Tim Wawrzynczak: Looks good to me, approved
diff --git a/Documentation/mainboard/supermicro/x11-lga1151-series/x11ssm-f/x11ssm-f.md b/Documentation/mainboard/supermicro/x11-lga1151-series/x11ssm-f/x11ssm-f.md
index 9f18b79..4e42809 100644
--- a/Documentation/mainboard/supermicro/x11-lga1151-series/x11ssm-f/x11ssm-f.md
+++ b/Documentation/mainboard/supermicro/x11-lga1151-series/x11ssm-f/x11ssm-f.md
@@ -4,9 +4,14 @@
## Flashing coreboot
-The board can be flashed externally. FTDI FT2232H and FT232H based programmers worked. For this,
-one needs to add a diode between VCC and the flash chip. The flash IC [MX25L12873F] can be found
-near PCH PCIe Slot 4.
+The flash IC [MX25L12873F] can be found near PCH PCIe Slot 4.
+
+The board can be flashed externally with a SOIC test clip or probes. Since
+there is no diode between VCC3.3 and the flash chip, so VCC must **not** be
+connected. Instead, the flash chip is powered from VCC3.3, which is always-on
+(even in S5). WP# and HOLD# have pull-ups and don't need to be connected.
+
+FTDI FT2232H and FT232H based programmers worked.
Flashing is also possible through the BMC web interface, when a valid license was entered.
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Patrick Georgi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52668 )
Change subject: soc/mediatek/mt8195: add pmif/spmi/pmic driver
......................................................................
Patch Set 3:
(1 comment)
Patchset:
PS3:
We generally prefer to have mainboard and SoC level code in separate commits. Would you mind splitting this in two?
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