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Change subject: soc/amd/picasso/dmi.c: Fix builds for boards without Google EC
......................................................................
Patch Set 1: Code-Review+2
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Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/52722 )
Change subject: mb/google/asurada: Fix power on delay
......................................................................
mb/google/asurada: Fix power on delay
From ANX7625 spec, the delay between powering on power supplies and GPIO
should be larger than 10ms. Since it takes about 4ms for the previous
GPIO EN_PP3300_EDP_DX to be pulled up, increase the delay from 2ms to
14ms.
BUG=b:157716104
TEST=emerge-asurada coreboot
BRANCH=asurada
Change-Id: If73747bdaec5ac069b048920d27e27178bc3cedc
Signed-off-by: Yu-Ping Wu <yupingso(a)chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52722
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
Reviewed-by: Hung-Te Lin <hungte(a)chromium.org>
---
M src/mainboard/google/asurada/mainboard.c
1 file changed, 1 insertion(+), 1 deletion(-)
Approvals:
build bot (Jenkins): Verified
Hung-Te Lin: Looks good to me, approved
diff --git a/src/mainboard/google/asurada/mainboard.c b/src/mainboard/google/asurada/mainboard.c
index 86e8d5f..f5489de 100644
--- a/src/mainboard/google/asurada/mainboard.c
+++ b/src/mainboard/google/asurada/mainboard.c
@@ -77,7 +77,7 @@
gpio_output(GPIO_EN_PP1000_EDPBRDG, 1);
gpio_output(GPIO_EN_PP1800_EDPBRDG_DX, 1);
gpio_output(GPIO_EN_PP3300_EDP_DX, 1);
- mdelay(2);
+ mdelay(14);
gpio_output(GPIO_EDPBRDG_PWREN, 1);
mdelay(10);
gpio_output(GPIO_EDPBRDG_RST_ODL, 1);
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Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52721 )
Change subject: mb/siemens/mc_apl{1,2,3,5,6}: Tune I2C frequency
......................................................................
Patch Set 2: Code-Review+1
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/52721/comment/83f07037_938e15a2
PS2, Line 13: computes the needed timings correctly.
nit: Depends of the order things are submitted if the note about defaults is still correct or not.
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Werner Zeh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52721 )
Change subject: mb/siemens/mc_apl{1,2,3,5,6}: Tune I2C frequency
......................................................................
Patch Set 2:
(1 comment)
Patchset:
PS1:
> The .rise_time_ns approach might be the recommended and more recent one to use.
Yes, I have switched to this approach in patchset #2.
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Hello build bot (Jenkins), Furquan Shaikh, Mario Scheithauer, Kyösti Mälkki,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/52721
to look at the new patch set (#2).
Change subject: mb/siemens/mc_apl{1,2,3,5,6}: Tune I2C frequency
......................................................................
mb/siemens/mc_apl{1,2,3,5,6}: Tune I2C frequency
All the boards in the patch have a constraint for the I2C bus to operate
on 100 kHz. Since the default values produce a higher frequency than
expected, provide dedicated values for rise time, fall time and
data hold time on mainboard level. Giving these values the driver
computes the needed timings correctly.
TEST=Measure I2C frequency on all boards while coreboot accesses
external RTC and make sure it is 100 kHz.
Change-Id: Iab634190bda5fa2a4fdf2ebaa1e45ac897d84deb
Signed-off-by: Werner Zeh <werner.zeh(a)siemens.com>
---
M src/mainboard/siemens/mc_apl1/variants/mc_apl1/devicetree.cb
M src/mainboard/siemens/mc_apl1/variants/mc_apl2/devicetree.cb
M src/mainboard/siemens/mc_apl1/variants/mc_apl3/devicetree.cb
M src/mainboard/siemens/mc_apl1/variants/mc_apl5/devicetree.cb
M src/mainboard/siemens/mc_apl1/variants/mc_apl6/devicetree.cb
5 files changed, 44 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/21/52721/2
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Rob Barnes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52230 )
Change subject: soc/amd/cezanne: Supply SMBIOS/DMI Type 17 data
......................................................................
Patch Set 5:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/52230/comment/a3f8a89e_a0ff66fc
PS1, Line 16: but then stoneyridge will break
> Done
Can dmi_info.h be in common too?
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Rob Barnes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52746 )
Change subject: soc/amd/picasso: Move Type 17 DMI generation to common
......................................................................
Patch Set 2: Code-Review+2
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