coreboot-gerrit April 2021

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Change in coreboot[master]: mb/google/mancomb: Add STAPM values to overridetree
by Marshall Dawson (Code Review) 29 Apr '21

29 Apr '21

Attention is currently required from: Martin Roth, Chris Wang, chris wang. Marshall Dawson has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52709 ) Change subject: mb/google/mancomb: Add STAPM values to overridetree ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/52709 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib3ed76e5212a5a8b5fb4fcc3d6884ceff82377b7 Gerrit-Change-Number: 52709 Gerrit-PatchSet: 3 Gerrit-Owner: chris wang <Chris.Wang(a)amd.com> Gerrit-Reviewer: Chris Wang <chris.wang(a)amd.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Chris Wang <chris.wang(a)amd.corp-partner.google.com> Gerrit-Attention: chris wang <Chris.Wang(a)amd.com> Gerrit-Comment-Date: Thu, 29 Apr 2021 16:13:22 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/pcengines/apu2/OemCustomize.c: make AGESA AmdInitPost happy
by Michał Żygowski (Code Review) 29 Apr '21

29 Apr '21

Michał Żygowski has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/52759 ) Change subject: mb/pcengines/apu2/OemCustomize.c: make AGESA AmdInitPost happy ...................................................................... mb/pcengines/apu2/OemCustomize.c: make AGESA AmdInitPost happy Bank interleaving does not work on this platform, disable it. Additionally enable ECC feature on SKUs supporting it. AmdIntPost returns success thanks to these settings. TEST=boot apu2 4GB ECC and apu3 2GB no ECC and see AGESA_SUCCESS after AmdInitPost Signed-off-by: Michał Żygowski <michal.zygowski(a)3mdeb.com> Change-Id: I010645f53b404341895d0545855905e81c89165e --- M src/mainboard/pcengines/apu2/OemCustomize.c 1 file changed, 16 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/59/52759/1 diff --git a/src/mainboard/pcengines/apu2/OemCustomize.c b/src/mainboard/pcengines/apu2/OemCustomize.c index 6e6b5a2..95af6ef 100644 --- a/src/mainboard/pcengines/apu2/OemCustomize.c +++ b/src/mainboard/pcengines/apu2/OemCustomize.c @@ -3,6 +3,8 @@ #include <AGESA.h> #include <northbridge/amd/agesa/state_machine.h> +#include "gpio_ftns.h" + static const PCIe_PORT_DESCRIPTOR PortList[] = { { 0, @@ -78,3 +80,17 @@ InitEarly->PlatformConfig.CStateMode = CStateModeC6; InitEarly->PlatformConfig.CpbMode = CpbModeAuto; } + +void board_BeforeInitPost(struct sysinfo *cb, AMD_POST_PARAMS *Post) +{ + /* + * Bank interleaving does not work on this platform. + * Disable it so AGESA will return success. + */ + Post->MemConfig.EnableBankIntlv = FALSE; + /* 4GB variants have ECC */ + if (get_spd_offset()) + Post->MemConfig.EnableEccFeature = TRUE; + else + Post->MemConfig.EnableEccFeature = FALSE; +} -- To view, visit https://review.coreboot.org/c/coreboot/+/52759 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I010645f53b404341895d0545855905e81c89165e Gerrit-Change-Number: 52759 Gerrit-PatchSet: 1 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/amd/common: Remove eSPI decode workaround
by Martin Roth (Code Review) 29 Apr '21

29 Apr '21

Martin Roth has submitted this change. ( https://review.coreboot.org/c/coreboot/+/52677 ) Change subject: soc/amd/common: Remove eSPI decode workaround ...................................................................... soc/amd/common: Remove eSPI decode workaround We no longer lock up if we clear the port 80 bit. I'm assuming this was fixed when we configured the PSP to no longer setup eSPI. BUG=b:183974365 TEST=Boot guybrush to OS Signed-off-by: Raul E Rangel <rrangel(a)chromium.org> Change-Id: I1530d08974d42e0b06eb783521dea32fca752d85 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52677 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> Reviewed-by: Martin Roth <martinroth(a)google.com> --- M src/soc/amd/common/block/lpc/espi_util.c 1 file changed, 1 insertion(+), 5 deletions(-) Approvals: build bot (Jenkins): Verified Martin Roth: Looks good to me, approved Marshall Dawson: Looks good to me, approved diff --git a/src/soc/amd/common/block/lpc/espi_util.c b/src/soc/amd/common/block/lpc/espi_util.c index 82f2a85..7752eb5 100644 --- a/src/soc/amd/common/block/lpc/espi_util.c +++ b/src/soc/amd/common/block/lpc/espi_util.c @@ -103,11 +103,7 @@ unsigned int idx; /* First turn off all enable bits, then zero base, range, and size registers */ - /* - * There is currently a bug where the SMU will lock up at times if the port80h enable - * bit is cleared. See b/183974365 - */ - espi_write16(ESPI_DECODE, (espi_read16(ESPI_DECODE) & ESPI_DECODE_IO_0x80_EN)); + espi_write16(ESPI_DECODE, 0); for (idx = 0; idx < ESPI_GENERIC_IO_WIN_COUNT; idx++) { espi_write16(ESPI_IO_RANGE_BASE(idx), 0); -- To view, visit https://review.coreboot.org/c/coreboot/+/52677 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1530d08974d42e0b06eb783521dea32fca752d85 Gerrit-Change-Number: 52677 Gerrit-PatchSet: 2 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/amd/common: Remove eSPI decode workaround
by Martin Roth (Code Review) 29 Apr '21

29 Apr '21

Attention is currently required from: Jason Glenesk, Raul Rangel, Felix Held. Martin Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52677 ) Change subject: soc/amd/common: Remove eSPI decode workaround ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/52677 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1530d08974d42e0b06eb783521dea32fca752d85 Gerrit-Change-Number: 52677 Gerrit-PatchSet: 1 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Thu, 29 Apr 2021 15:35:55 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/guybrush,mancomb: only print warning in mainboard_smi_gpi
by Martin Roth (Code Review) 29 Apr '21

29 Apr '21

Martin Roth has submitted this change. ( https://review.coreboot.org/c/coreboot/+/52360 ) Change subject: mb/google/guybrush,mancomb: only print warning in mainboard_smi_gpi ...................................................................... mb/google/guybrush,mancomb: only print warning in mainboard_smi_gpi guybrush and mancomb don't configure any GPIO as PAD_SMI. Since mainboard_smi_gpi will only get called for a GEVENT that will cause a non-SCI SMI, this isn't expected to be called. For the unexpected and very unlikely case that it still does get called, put a printk into mainboard_smi_gpi to see what is happening there. TEST=none Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: Ifd6e3348ecc078932bf6cf5b0830b4b034d274bb Reviewed-on: https://review.coreboot.org/c/coreboot/+/52360 Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> Reviewed-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/google/guybrush/smihandler.c M src/mainboard/google/mancomb/smihandler.c 2 files changed, 6 insertions(+), 2 deletions(-) Approvals: build bot (Jenkins): Verified Marshall Dawson: Looks good to me, approved Angel Pons: Looks good to me, but someone else must approve diff --git a/src/mainboard/google/guybrush/smihandler.c b/src/mainboard/google/guybrush/smihandler.c index 6facb76..04280db 100644 --- a/src/mainboard/google/guybrush/smihandler.c +++ b/src/mainboard/google/guybrush/smihandler.c @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ #include <baseboard/variants.h> +#include <console/console.h> #include <cpu/x86/smm.h> #include <ec/google/chromeec/ec.h> #include <ec/google/chromeec/smm.h> @@ -9,7 +10,8 @@ void mainboard_smi_gpi(u32 gpi_sts) { - chromeec_smi_process_events(); + printk(BIOS_WARNING, "No GPIO is set up as PAD_SMI, so %s should never end up being " + "called. gpi_status is %x.\n", __func__, gpi_sts); } void mainboard_smi_sleep(u8 slp_typ) diff --git a/src/mainboard/google/mancomb/smihandler.c b/src/mainboard/google/mancomb/smihandler.c index 6facb76..04280db 100644 --- a/src/mainboard/google/mancomb/smihandler.c +++ b/src/mainboard/google/mancomb/smihandler.c @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ #include <baseboard/variants.h> +#include <console/console.h> #include <cpu/x86/smm.h> #include <ec/google/chromeec/ec.h> #include <ec/google/chromeec/smm.h> @@ -9,7 +10,8 @@ void mainboard_smi_gpi(u32 gpi_sts) { - chromeec_smi_process_events(); + printk(BIOS_WARNING, "No GPIO is set up as PAD_SMI, so %s should never end up being " + "called. gpi_status is %x.\n", __func__, gpi_sts); } void mainboard_smi_sleep(u8 slp_typ) -- To view, visit https://review.coreboot.org/c/coreboot/+/52360 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifd6e3348ecc078932bf6cf5b0830b4b034d274bb Gerrit-Change-Number: 52360 Gerrit-PatchSet: 4 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Mathew King <mathewk(a)chromium.org> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/google/zork/smihandler: only print warning in mainboard_smi_gpi
by Martin Roth (Code Review) 29 Apr '21

29 Apr '21

Martin Roth has submitted this change. ( https://review.coreboot.org/c/coreboot/+/52359 ) Change subject: mb/google/zork/smihandler: only print warning in mainboard_smi_gpi ...................................................................... mb/google/zork/smihandler: only print warning in mainboard_smi_gpi zork doesn't configure any GPIO as PAD_SMI. Since mainboard_smi_gpi will only get called for a GEVENT that will cause a non-SCI SMI, this isn't expected to be called. For the unexpected and very unlikely case that it still does get called, put a printk into mainboard_smi_gpi to see what is happening there. TEST=none Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I14c67b21a83b334558cdd54ebf700924aa9d0808 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52359 Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> Reviewed-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/google/zork/smihandler.c 1 file changed, 4 insertions(+), 2 deletions(-) Approvals: build bot (Jenkins): Verified Marshall Dawson: Looks good to me, approved Angel Pons: Looks good to me, but someone else must approve diff --git a/src/mainboard/google/zork/smihandler.c b/src/mainboard/google/zork/smihandler.c index 802487b..3a10dd2 100644 --- a/src/mainboard/google/zork/smihandler.c +++ b/src/mainboard/google/zork/smihandler.c @@ -2,6 +2,7 @@ #include <acpi/acpi.h> #include <baseboard/variants.h> +#include <console/console.h> #include <cpu/x86/smm.h> #include <ec/google/chromeec/smm.h> #include <gpio.h> @@ -11,9 +12,10 @@ void mainboard_smi_gpi(u32 gpi_sts) { - if (CONFIG(EC_GOOGLE_CHROMEEC)) - chromeec_smi_process_events(); + printk(BIOS_WARNING, "No GPIO is set up as PAD_SMI, so %s should never end up being " + "called. gpi_status is %x.\n", __func__, gpi_sts); } + void mainboard_smi_sleep(u8 slp_typ) { size_t num_gpios; -- To view, visit https://review.coreboot.org/c/coreboot/+/52359 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I14c67b21a83b334558cdd54ebf700924aa9d0808 Gerrit-Change-Number: 52359 Gerrit-PatchSet: 4 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/google/zork/smihandler: only print warning in mainboard_smi_gpi
by Martin Roth (Code Review) 29 Apr '21

29 Apr '21

Attention is currently required from: Raul Rangel, Marshall Dawson, Felix Held. Martin Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52359 ) Change subject: mb/google/zork/smihandler: only print warning in mainboard_smi_gpi ...................................................................... Patch Set 3: (1 comment) File src/mainboard/google/zork/smihandler.c: https://review.coreboot.org/c/coreboot/+/52359/comment/0f29cc4a_a484b307 PS2, Line 15: chromeec_smi_process_events > there are 32 SCI GEVENTs which different things can be mapped to the code setting up enabled GPIO GE […] Ack -- To view, visit https://review.coreboot.org/c/coreboot/+/52359 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I14c67b21a83b334558cdd54ebf700924aa9d0808 Gerrit-Change-Number: 52359 Gerrit-PatchSet: 3 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Thu, 29 Apr 2021 15:31:10 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Raul Rangel <rrangel(a)chromium.org> Comment-In-Reply-To: Marshall Dawson <marshalldawson3rd(a)gmail.com> Comment-In-Reply-To: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/amd/common: Remove eSPI decode workaround
by Marshall Dawson (Code Review) 29 Apr '21

29 Apr '21

Attention is currently required from: Jason Glenesk, Raul Rangel, Martin Roth, Felix Held. Marshall Dawson has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52677 ) Change subject: soc/amd/common: Remove eSPI decode workaround ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/52677 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1530d08974d42e0b06eb783521dea32fca752d85 Gerrit-Change-Number: 52677 Gerrit-PatchSet: 1 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Thu, 29 Apr 2021 15:27:19 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/amd/cezanne: add verstage files
by Martin Roth (Code Review) 29 Apr '21

29 Apr '21

Attention is currently required from: Jason Glenesk, Raul Rangel, Marshall Dawson, Kangheui Won, Felix Held. Martin Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52752 ) Change subject: soc/amd/cezanne: add verstage files ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/52752 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iac48c92a787adabfdaec96b6e8d2e24708d7e652 Gerrit-Change-Number: 52752 Gerrit-PatchSet: 1 Gerrit-Owner: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Kangheui Won <khwon(a)chromium.org> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Thu, 29 Apr 2021 15:26:28 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: [HACK] reduce memory usgae on cezanne psp_verstage
by Martin Roth (Code Review) 29 Apr '21

29 Apr '21

Attention is currently required from: Jason Glenesk, Raul Rangel, Marshall Dawson, Kangheui Won, Felix Held. Martin Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52751 ) Change subject: [HACK] reduce memory usgae on cezanne psp_verstage ...................................................................... Patch Set 1: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/52751/comment/db365613_36e1a329 PS1, Line 7: usgae Usage https://review.coreboot.org/c/coreboot/+/52751/comment/ef2e5e55_3a5a54c9 PS1, Line 7: [HACK] If you don't plan to submit this, you might want to mark it "DNS" and then toggle the WIP flag. If you do plan to submit it, maybe just mark things with a TODO to expand them later when we can. Or maybe just mark it to revert this patch in the future. -- To view, visit https://review.coreboot.org/c/coreboot/+/52751 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I30730a6dc53e2449981c635ecfe63029c73e58ee Gerrit-Change-Number: 52751 Gerrit-PatchSet: 1 Gerrit-Owner: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Kangheui Won <khwon(a)chromium.org> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Thu, 29 Apr 2021 15:24:14 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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coreboot-gerrit April 2021