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shkim has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/51049 )
Change subject: mb/google/dedede/var/sasuke: Configure GPP_B7 as GPO_HIGH
......................................................................
Patch Set 1:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/51049/comment/aeb6c3ab_9b92829d
PS1, Line 9: Sasuke doesn't have SAR sensor, we
: would keep this signal as high.
> Should it still be high. […]
GPO_HIGH config was a suggestion in b:180492044. GPP_B7 is wired to SAR input of LTE modem physically, so discussed about keeping signal to high in the tracker.
I think we can use PAD_NC(GPP_B7, UP_20K) like you said as well, which one is batter?
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Change subject: mb/google/asurada: Add generic DRAM groups
......................................................................
Patch Set 1:
(1 comment)
Patchset:
PS1:
need ddr_type in sdram struct.
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Change subject: soc/mediatek/mt8192: Increase PRERAM_CBMEM_CONSOLE to 128K
......................................................................
Patch Set 2: Code-Review+2
(1 comment)
File src/soc/mediatek/mt8192/include/soc/memlayout.ld:
https://review.coreboot.org/c/coreboot/+/51174/comment/58919bea_2c3a3af6
PS1, Line 51: 128K
> Yes. […]
I thought you said "For full calibration, the romstage log can be as large as 430K"?
If 430k is not enough, how large does it usually needs?
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Julius Werner has submitted this change. ( https://review.coreboot.org/c/coreboot/+/51126 )
Change subject: soc/rockchip/rk3399/sdram: Simplify error condition
......................................................................
soc/rockchip/rk3399/sdram: Simplify error condition
There is no need for explicit 0 comparison, any return value not equal
to 0 is treated as error.
Change-Id: I72612af4108a616b6247ee68c8ac2a53242b0853
Signed-off-by: Moritz Fischer <moritzf(a)google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51126
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---
M src/soc/rockchip/rk3399/sdram.c
1 file changed, 1 insertion(+), 1 deletion(-)
Approvals:
build bot (Jenkins): Verified
Paul Menzel: Looks good to me, but someone else must approve
Julius Werner: Looks good to me, approved
diff --git a/src/soc/rockchip/rk3399/sdram.c b/src/soc/rockchip/rk3399/sdram.c
index 0fdef71..6d58b6a 100644
--- a/src/soc/rockchip/rk3399/sdram.c
+++ b/src/soc/rockchip/rk3399/sdram.c
@@ -1133,7 +1133,7 @@
* step may fail, before that, we just reset the
* system, and start again.
*/
- if (pctl_cfg(channel, params) != 0) {
+ if (pctl_cfg(channel, params)) {
printk(BIOS_ERR, "pctl_cfg fail, reset\n");
board_reset();
}
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Change subject: intel/common/block/memory: Add saving memory info API
......................................................................
intel/common/block/memory: Add saving memory info API
Memory information is stored into CBMEM later to be used to generate
SMBIOS table 17.
Including implementation for CNL and TGL SOC's.
Signed-off-by: Bernardo Perez Priego <bernardo.perez.priego(a)intel.com>
Change-Id: I78d14c71d5d19f58e6a27ed5ef8269c6678f32a5
---
M src/soc/intel/cannonlake/Kconfig
M src/soc/intel/cannonlake/romstage/romstage.c
A src/soc/intel/common/block/include/intelblocks/meminfo.h
M src/soc/intel/common/block/memory/Kconfig
M src/soc/intel/common/block/memory/Makefile.inc
A src/soc/intel/common/block/memory/meminfo.c
M src/soc/intel/tigerlake/Kconfig
M src/soc/intel/tigerlake/romstage/romstage.c
8 files changed, 157 insertions(+), 206 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/05/51105/5
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Change subject: soc/mediatek/mt8192: Increase PRERAM_CBMEM_CONSOLE to 128K
......................................................................
Patch Set 2:
(2 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/51174/comment/6ceef39a_b4ed9c39
PS1, Line 9: 128K
> What is the current default?
Done
File src/soc/mediatek/mt8192/include/soc/memlayout.ld:
https://review.coreboot.org/c/coreboot/+/51174/comment/75e157f4_079aa5a2
PS1, Line 51: 128K
> Do you mean config CONSOLE_CBMEM_BUFFER_SIZE ? We can definitely increase that as well.
Yes. However, even if we increase it to >=430K, there's still no enough space for PRERAM_CBMEM_CONSOLE to store the whole full-k log. Therefore it seems there's no need to increase CONSOLE_CBMEM_BUFFER_SIZE.
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Change subject: soc/mediatek/mt8192: Increase PRERAM_CBMEM_CONSOLE to 128K
......................................................................
soc/mediatek/mt8192: Increase PRERAM_CBMEM_CONSOLE to 128K
Move PRERAM_CBMEM_CONSOLE to SRAM L2C and increase its size from 15K to
128K. With this change, more DRAM calibration logs can be kept in CBMEM
console.
BUG=none
TEST=emerge-asurada coreboot
TEST=Hayato boots
BRANCH=none
Change-Id: I896884d298e197149f75865e9d00579124a34404
Signed-off-by: Yu-Ping Wu <yupingso(a)chromium.org>
---
M src/soc/mediatek/mt8192/include/soc/memlayout.ld
1 file changed, 1 insertion(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/51174/2
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Change subject: intel/common/block/memory: Add saving memory info API
......................................................................
intel/common/block/memory: Add saving memory info API
Memory information is stored into CBMEM later to be used to generate
SMBIOS table 17.
Including implementation for CNL, SKL and TGL SOC's.
Signed-off-by: Bernardo Perez Priego <bernardo.perez.priego(a)intel.com>
Change-Id: I78d14c71d5d19f58e6a27ed5ef8269c6678f32a5
---
M src/soc/intel/cannonlake/Kconfig
M src/soc/intel/cannonlake/romstage/romstage.c
A src/soc/intel/common/block/include/intelblocks/meminfo.h
M src/soc/intel/common/block/memory/Kconfig
M src/soc/intel/common/block/memory/Makefile.inc
A src/soc/intel/common/block/memory/meminfo.c
M src/soc/intel/skylake/Kconfig
M src/soc/intel/skylake/romstage/romstage.c
M src/soc/intel/tigerlake/Kconfig
M src/soc/intel/tigerlake/romstage/romstage.c
10 files changed, 165 insertions(+), 311 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/05/51105/4
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