Raul Rangel has uploaded a new patch set (#2). ( https://review.coreboot.org/c/sublime-text-coreboot-syntax/+/51241 )
Change subject: Add coreboot device tree syntax
......................................................................
Add coreboot device tree syntax
Let's make it easy on the eyes when reading device tree files!
Signed-off-by: Raul E Rangel <rrangel(a)chromium.org>
Change-Id: Ie121113201f281d7a68038c4991c453bbaefbe43
---
A README.md
A coreboot-devicetree.sublime-syntax
A screenshots/Coreboot Device Tree.png
3 files changed, 163 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/sublime-text-coreboot-syntax refs/changes/41/51241/2
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Gerrit-Change-Id: Ie121113201f281d7a68038c4991c453bbaefbe43
Gerrit-Change-Number: 51241
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Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/51164 )
Change subject: security/tpm/tss/vendor/cr50: Introduce vendor sub-command to reset EC
......................................................................
Patch Set 3: Code-Review+2
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Change subject: mb/google/guybrush: Enable Chrome EC
......................................................................
mb/google/guybrush: Enable Chrome EC
BUG=b:180507937
TEST=builds
Signed-off-by: Mathew King <mathewk(a)chromium.org>
Change-Id: I3cdd6422b1bc53ea934346327359cbc6d86baeeb
---
M src/mainboard/google/guybrush/Kconfig
M src/mainboard/google/guybrush/Makefile.inc
A src/mainboard/google/guybrush/ec.c
M src/mainboard/google/guybrush/mainboard.c
A src/mainboard/google/guybrush/variants/baseboard/include/baseboard/ec.h
A src/mainboard/google/guybrush/variants/guybrush/include/variant/ec.h
6 files changed, 75 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/43/51043/4
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Change subject: mb/google/volteer/variants: Disable non-existing BT PCI interface and add BT flag
......................................................................
mb/google/volteer/variants: Disable non-existing BT PCI interface and add BT flag
Remove the CNVi BT PCI config and add BT flag. There is no PCI host interface
in this version of CNVi.
TEST: BT is checked using 'lsusb -d 8087:0026' from OS to make sure BT is
enumerated.
Change-Id: Ic700021d7a09be63ffc2715f31992257e2e893af
Signed-off-by: Cliff Huang <cliff.huang(a)intel.com>
---
M src/mainboard/google/volteer/variants/baseboard/devicetree.cb
1 file changed, 2 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/98/50898/8
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Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/51197 )
Change subject: [WIP] vc/amd/fsp/cezanne: add platform_descriptors.c
......................................................................
Patch Set 4:
(1 comment)
File src/vendorcode/amd/fsp/cezanne/platform_descriptors.h:
https://review.coreboot.org/c/coreboot/+/51197/comment/7508ba54_7ba1bd16
PS4, Line 57: CLK_GPP_REQ0 = 0x09,
not sure if CLK_GPP_REQ[0..4] exist. i only see CLK_REQ[0..6] in the reference board schematics
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Change subject: mb/google/volteer: Configure tcss port information for early tcss init
......................................................................
mb/google/volteer: Configure tcss port information for early tcss init
Implement the mainboard_tcss_get_port_info weak function so that the TCSS
muxes can be properly configured to ensure mapping is correct in mux. This
ensures that any devices that are connected during boot are not improperly
configured by the Kernel.
BUG=b:180426950
BRANCH=firmare-volteer-13672.B
TEST= Verified that the SOC code that initialized TCSS muxes to disconnect
mode is executing properly for all TCSS ports and verified that USB3 devices
are no longer downgrading to USB2 speed if connected during boot.
Change-Id: I59e5c5a7d2ab5ef5293abe6c59c3a585b25f7b75
Signed-off-by: Brandon Breitenstein <brandon.breitenstein(a)intel.com>
---
M src/mainboard/google/volteer/Kconfig
M src/mainboard/google/volteer/mainboard.c
2 files changed, 59 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/95/51195/8
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Change subject: soc/intel/tigerlake: Enable TCSS Muxes to disconnect mode during boot
......................................................................
soc/intel/tigerlake: Enable TCSS Muxes to disconnect mode during boot
TCSS muxes being left uninitialized during boot is causing some USB3
devices to downgrade to USB2 speed. To properly configure the Type C ports
the muxes should be set to disconnected state during boot so that the port
mapping of USB2/3 devices is properly setup prior to Kernel initializing
devices.
BUG=b:180426950
BRANCH=firmware-volteer-13672.B
TEST= Connected USB3 storage device and rebooted the system multiple
times to verify that devices were no longer downgrading to USB2 speed.
Change-Id: I4352072a4a7d6ccb1364b38377831f3c22ae8fb4
Signed-off-by: Brandon Breitenstein <brandon.breitenstein(a)intel.com>
---
M src/soc/intel/tigerlake/Kconfig
M src/soc/intel/tigerlake/Makefile.inc
M src/soc/intel/tigerlake/early_tcss.c
M src/soc/intel/tigerlake/fsp_params.c
M src/soc/intel/tigerlake/include/soc/early_tcss.h
5 files changed, 123 insertions(+), 58 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/94/51194/9
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