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Change subject: vc/amd/fsp/picasso: increase FSPS UPD block size from 0x152 to 0x202
......................................................................
Patch Set 4: Code-Review+2
(1 comment)
Patchset:
PS4:
since the fsp update has landed, this can be merged without causing trouble
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Change subject: mb/google/guybrush: Enable Chrome EC
......................................................................
Patch Set 4:
(2 comments)
File src/mainboard/google/guybrush/mainboard.c:
https://review.coreboot.org/c/coreboot/+/51043/comment/4feae6b9_8d2d7db7
PS4, Line 22: mainboard_ec_init
Do we need to configure the GPIOs before the EC? I'm not sure what the default state of the eSPI pins is.
File src/mainboard/google/guybrush/variants/baseboard/include/baseboard/ec.h:
https://review.coreboot.org/c/coreboot/+/51043/comment/b9601404_dc632b23
PS4, Line 26: SMI
Are we really using SMIs for this?
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Change subject: soc/intel/tigerlake: Enable TCSS Muxes to disconnect mode during boot
......................................................................
Patch Set 9:
(1 comment)
Patchset:
PS9:
> Any idea why this is showing merge conflict? I rebased to master and still showing it builds fine wi […]
I think it is just because of the relation chain. Since earlier CL touches the same files, gerrit identifies this as a merge conflict. I don't think there is any action required.
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Change subject: soc/intel/tigerlake: Enable TCSS Muxes to disconnect mode during boot
......................................................................
Patch Set 9:
(1 comment)
Patchset:
PS9:
Any idea why this is showing merge conflict? I rebased to master and still showing it builds fine with build bot etc
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Change subject: soc/intel/broadwell/pch: Use Lynx Point smbus.c
......................................................................
Patch Set 1: Code-Review+2
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Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/51242 )
Change subject: [RFC] soc/amd/cezanne/chipset.cb: clean up and change some aliases
......................................................................
[RFC] soc/amd/cezanne/chipset.cb: clean up and change some aliases
With the aliases some of the comments are redundant. I'm still not sure
if the Ethernet controller on the embedded SKUs supports 10G or only 1G.
Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de>
Change-Id: I1e432c12f92a622f8ee05be19acb2c304dd74afb
---
M src/soc/amd/cezanne/chipset.cb
1 file changed, 24 insertions(+), 24 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/42/51242/1
diff --git a/src/soc/amd/cezanne/chipset.cb b/src/soc/amd/cezanne/chipset.cb
index 5e3d269..cb05750 100644
--- a/src/soc/amd/cezanne/chipset.cb
+++ b/src/soc/amd/cezanne/chipset.cb
@@ -4,48 +4,48 @@
end
device domain 0 on
device pci 00.0 alias gnb on end
- device pci 0.2 alias iommu off end # IOMMU
+ device pci 00.2 alias iommu off end
- device pci 1.0 on end # Dummy Host Bridge, do not disable
- device pci 1.1 alias gpp_bridge_1_1 off end # GPP Bridge 0
- device pci 1.2 alias gpp_bridge_1_2 off end # GPP Bridge 1
- device pci 1.3 alias gpp_bridge_1_3 off end # GPP Bridge 2
+ device pci 01.0 on end # Dummy Host Bridge, do not disable
+ device pci 01.1 alias gpp_gfx_bridge_0 off end
+ device pci 01.2 alias gpp_gfx_bridge_1 off end
+ device pci 01.3 alias gpp_gfx_bridge_2 off end
- device pci 2.0 on end # Dummy Host Bridge, do not disable
- device pci 2.1 alias gpp_bridge_2_1 off end # GPP Bridge 0
- device pci 2.2 alias gpp_bridge_2_2 off end # GPP Bridge 1
- device pci 2.3 alias gpp_bridge_2_3 off end # GPP Bridge 2
- device pci 2.4 alias gpp_bridge_2_4 off end # GPP Bridge 3
- device pci 2.5 alias gpp_bridge_2_5 off end # GPP Bridge 4
- device pci 2.6 alias gpp_bridge_2_6 off end # GPP Bridge 5
- device pci 2.7 alias gpp_bridge_2_7 off end # GPP Bridge 6
+ device pci 02.0 on end # Dummy Host Bridge, do not disable
+ device pci 02.1 alias gpp_bridge_0 off end
+ device pci 02.2 alias gpp_bridge_1 off end
+ device pci 02.3 alias gpp_bridge_2 off end
+ device pci 02.4 alias gpp_bridge_3 off end
+ device pci 02.5 alias gpp_bridge_4 off end
+ device pci 02.6 alias gpp_bridge_5 off end
+ device pci 02.7 alias gpp_bridge_6 off end
- device pci 8.0 on end # Dummy Host Bridge, do not disable
- device pci 8.1 alias gpp_bridge_a off # Internal GPP Bridge 0 to Bus A
+ device pci 08.0 on end # Dummy Host Bridge, do not disable
+ device pci 08.1 alias gpp_bridge_a off # Internal GPP Bridge 0 to Bus A
device pci 0.0 alias gfx off end # Internal GPU (GFX)
- device pci 0.1 alias gfx_az off end # Display HD Audio Controller (GFXAZ)
+ device pci 0.1 alias gfx_hda off end # Display HD Audio Controller (GFXAZ)
device pci 0.2 alias crypto off end # Crypto Coprocessor
- device pci 0.3 alias xhci_0 off end # USB 3.1 (USB0)
- device pci 0.4 alias xhci_1 off end # USB 3.1 (USB1)
+ device pci 0.3 alias xhci_0 off end
+ device pci 0.4 alias xhci_1 off end
device pci 0.5 alias acp off end # Audio Processor (ACP)
- device pci 0.6 alias standalone_az off end # Audio Processor HD Audio Controller (Standalone AZ)
+ device pci 0.6 alias hda off end # Audio Processor HD Audio Controller (main AZ)
device pci 0.7 alias mp2 off end # Sensor Fusion Hub (MP2)
end
- device pci 8.2 alias gpp_bridge_b off # Internal GPP Bridge 1 to Bus B
+ device pci 08.2 alias gpp_bridge_b off # Internal GPP Bridge 1 to Bus B
device pci 0.0 alias sata_0 off end # first SATA controller; AHCI Mode
device pci 0.1 alias sata_1 off end # second SATA Controller; SATA Raid/AHCI Mode
device pci 0.2 alias xgbe_0 off end # 10 GbE Controller Port 0 (XGBE0)
device pci 0.3 alias xgbe_1 off end # 10 GbE Controller Port 1 (XGBE1)
end
- device pci 8.3 alias gpp_bridge_c off # Internal GPP Bridge 2 to Bus C
+ device pci 08.3 alias gpp_bridge_c off # Internal GPP Bridge 2 to Bus C
device pci 0.0 alias dummy_function_c off end # PCIe Dummy Function
device pci 0.2 alias i2s_ac97 off end # I2S/AC'97 Audio
end
- device pci 14.0 alias smbus on end # SMBus, primary FCH function
- device pci 14.3 alias lpc_bridge on end # LPC Bridge
+ device pci 14.0 alias smbus on end # primary FCH function
+ device pci 14.3 alias lpc_bridge on end
- device pci 18.0 alias data_fabric_0 on end # Data fabric [0-7]
+ device pci 18.0 alias data_fabric_0 on end
device pci 18.1 alias data_fabric_1 on end
device pci 18.2 alias data_fabric_2 on end
device pci 18.3 alias data_fabric_3 on end
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Mariusz Szafrański has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/51180 )
Change subject: util/sconfig: Fix for multidomain support sconfig/devicetree.cb
......................................................................
Patch Set 2:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/51180/comment/a944778d_d900f919
PS2, Line 7: multidomain
> If it's okay with you, I'd be interested in knowing the use-cases for multi-domain support. […]
It`s ok, can be done in public no prob. with that
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Hello build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/51240
to look at the new patch set (#3).
Change subject: mb/google/guybrush: Add ACPI support for Chrome EC
......................................................................
mb/google/guybrush: Add ACPI support for Chrome EC
BUG=b:180507937
TEST=builds
Signed-off-by: Mathew King <mathewk(a)chromium.org>
Change-Id: Icb8aba87390475cad7a2a9911c3832a59c987b65
---
M src/mainboard/google/guybrush/dsdt.asl
M src/mainboard/google/guybrush/variants/baseboard/include/baseboard/ec.h
2 files changed, 47 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/40/51240/3
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Mathew King has uploaded a new patch set (#2). ( https://review.coreboot.org/c/coreboot/+/51240 )
Change subject: mb/google/guybrush: Add ACPI support for Chrome EC
......................................................................
mb/google/guybrush: Add ACPI support for Chrome EC
BUG=b:180507937
TEST=builds
Signed-off-by: Mathew King <mathewk(a)chromium.org>
Change-Id: Icb8aba87390475cad7a2a9911c3832a59c987b65
---
M src/mainboard/google/guybrush/dsdt.asl
M src/mainboard/google/guybrush/variants/baseboard/include/baseboard/ec.h
2 files changed, 47 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/40/51240/2
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