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Change subject: intel/common/block/memory: Add saving memory info API
......................................................................
Patch Set 6:
(3 comments)
File src/drivers/intel/fsp2_0/hob_memory_info.c:
PS2:
> In my opinion, this file belongs in soc/intel/common/block/memory. […]
Done
https://review.coreboot.org/c/coreboot/+/51105/comment/59ceaf90_6e1bc455
PS2, Line 16: #ifndef CHANNEL_NOT_PRESENT
: #define CHANNEL_NOT_PRESENT 0 // There is no channel present on the controller.
: #endif
: #ifndef CHANNEL_DISABLED
: #define CHANNEL_DISABLED 1 // There is a channel present but it is disabled.
: #endif
: #ifndef CHANNEL_PRESENT
: #define CHANNEL_PRESENT 2 // There is a channel present and it is enabled.
: #endif
> These should come from the FSP headers and not defined in coreboot. […]
Done
File src/drivers/intel/fsp2_0/memory_init.c:
https://review.coreboot.org/c/coreboot/+/51105/comment/b5637405_a333d5d6
PS1, Line 40: #define FSP_SMBIOS_MEMORY_INFO_GUID \
: { \
: 0xd4, 0x71, 0x20, 0x9b, 0x54, 0xb0, 0x0c, 0x4e, \
: 0x8d, 0x09, 0x11, 0xcf, 0x8b, 0x9f, 0x03, 0x23 \
: }
> This is a platform specific HOB. It is not defined in PI spec or FSP spec. […]
Done
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Change subject: mb/google/volteer/variant/lindar: Disable SA GV for EVT build MB
......................................................................
Patch Set 5:
(2 comments)
File src/mainboard/google/volteer/romstage.c:
https://review.coreboot.org/c/coreboot/+/51200/comment/07f86d34_18fd021c
PS5, Line 28: void __weak memcfg_variant_init(FSPM_UPD *mupd)
: {
: uint32_t board_version;
: FSP_M_CONFIG *mem_cfg = &mupd->FspmConfig;
:
: if ((google_chromeec_get_board_version(&board_version) == 0) && (board_version == 1))
: mem_cfg->SaGv = 0x00;
: }
This should be put to the lindar/memory.c. You can just put the empty function for the other projects:
void __weak memcfg_variant_init(FSPM_UPD *mupd)
{
}
File src/mainboard/google/volteer/variants/baseboard/include/baseboard/variants.h:
https://review.coreboot.org/c/coreboot/+/51200/comment/6d3682b2_7d38f725
PS5, Line 23: __weak
remove the __weak
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Change subject: mb/google/volteer/variant/lindar: Disable SA GV for EVT build MB
......................................................................
Patch Set 5:
(1 comment)
File src/mainboard/google/volteer/variants/baseboard/include/baseboard/variants.h:
https://review.coreboot.org/c/coreboot/+/51200/comment/b7989fb0_9123e497
PS5, Line 23: void __weak memcfg_variant_init(FSPM_UPD *mupd);
Using weak declarations can have unintended link defects
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Change subject: mb/google/volteer/variant/lindar: Disable SA GV for EVT build MB
......................................................................
mb/google/volteer/variant/lindar: Disable SA GV for EVT build MB
Disable SA GV in EVT MB, because factory used Samsung memory with wrong date code.
So we need to use board version to judement MB phase to disable SA GV.
Disable SA GV when board version equal.
BUG=b:179747696
BRANCH=firmware-volteer-13672.B
TEST=Built and booted into OS.
Signed-off-by: Kevin Chang <kevin.chang(a)lcfc.corp-partner.google.com>
Change-Id: I51f4adcf0dd8dbf1cf39d8aec6e4303565551e5f
Signed-off-by: Kevin Chang <kevin.chang(a)lcfc.corp-partner.google.com>
---
M src/mainboard/google/volteer/romstage.c
M src/mainboard/google/volteer/variants/baseboard/include/baseboard/variants.h
2 files changed, 11 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/00/51200/5
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Change subject: intel/common/block/memory: Add saving memory info API
......................................................................
intel/common/block/memory: Add saving memory info API
Memory information is stored into CBMEM later to be used to generate
SMBIOS table 17.
Including implementation for CNL and TGL SOC's.
Signed-off-by: Bernardo Perez Priego <bernardo.perez.priego(a)intel.com>
Change-Id: I78d14c71d5d19f58e6a27ed5ef8269c6678f32a5
---
M src/soc/intel/cannonlake/Kconfig
M src/soc/intel/cannonlake/romstage/romstage.c
A src/soc/intel/common/block/include/intelblocks/meminfo.h
M src/soc/intel/common/block/memory/Kconfig
M src/soc/intel/common/block/memory/Makefile.inc
A src/soc/intel/common/block/memory/meminfo.c
M src/soc/intel/tigerlake/Kconfig
M src/soc/intel/tigerlake/romstage/romstage.c
8 files changed, 157 insertions(+), 206 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/05/51105/6
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Change subject: vendor: mediatek: Add mediatek mt8192 dram initialization code
......................................................................
Patch Set 21:
(1 comment)
Patchset:
PS21:
@xixi, please consider again changing the license to GPL-2.0-only OR BSD-3-Clause. I think that will be easier when we have changes here in future (if we do want to keep both versions synced)
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Change subject: src/mediatek/common: Add DRAM common files
......................................................................
Patch Set 2:
(4 comments)
File src/soc/mediatek/common/Kconfig:
https://review.coreboot.org/c/coreboot/+/51203/comment/4711fb42_e9873ca9
PS1, Line 1: config MEDIATEK_DRAM_DVFS
: bool
: default n
: help
: This option enables DRAM calibration with multiple frequencies (low,
: medium and high frequency groups, with total 7 frequencies) for DVFS
: feature. All supported data rates are: 800, 1200, 1600, 1866, 2400,
: 3200, 4266.
:
: config MEDIATEK_DRAM_DVFS_LIMIT_FREQ_CNT
: bool
: default y
: select MEDIATEK_DRAM_DVFS
: help
: This options limit DRAM frequency calibration count from total 7 to 3,
: other frequency will directly use the low frequency shu result.
:
: config MEMORY_TEST
: bool
: default y
: help
: This option enables memory basic compare test to verify the DRAM read
: or write is as expected.
:
I think we have to move this to an if-block so only MTK platforms will have these options, otherwise other non-mtk configs will also have them.
Please check amd common/Kconfig*.
File src/soc/mediatek/common/dram_init.c:
https://review.coreboot.org/c/coreboot/+/51203/comment/f1aaed76_e96c7c88
PS1, Line 10: extern void (*do_putc)(unsigned char c);
I think we don't need this anymore?
https://review.coreboot.org/c/coreboot/+/51203/comment/f94c135b_d4c052bf
PS1, Line 30: const
If mt_set_emi can't take const, what about just removing the const for init_dram_by_params?
So we don't need to cast below, and make it more clear.
File src/soc/mediatek/common/memory.c:
https://review.coreboot.org/c/coreboot/+/51203/comment/157afba9_b54c6f93
PS1, Line 28: } else {
: printk(BIOS_DEBUG, "[MEM] complex R/W mem test passed\n");
: }
:
remove the else and move the printk to either add printing rank number, or move to outside of the for-loop.
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Hello Hung-Te Lin, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
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Change subject: src/mediatek/common: Add DRAM common files
......................................................................
src/mediatek/common: Add DRAM common files
To reduce duplicated dram sources on seperate SOCs,
add dpm, dram_init, dramc_params, memory(fast-k or full-k)
implementations, also add dramc log level macro header files.
Signed-off-by: Xi Chen <xixi.chen(a)mediatek.com>
Change-Id: I557c96b3d09828472b8b6f932b0192a90894043e
---
A src/soc/mediatek/common/Kconfig
A src/soc/mediatek/common/dpm.c
A src/soc/mediatek/common/dram_init.c
A src/soc/mediatek/common/dramc_param.c
A src/soc/mediatek/common/include/soc/dpm.h
A src/soc/mediatek/common/include/soc/dramc_common.h
A src/soc/mediatek/common/include/soc/dramc_param.h
A src/soc/mediatek/common/include/soc/emi.h
A src/soc/mediatek/common/memory.c
M src/soc/mediatek/mt8173/Kconfig
M src/soc/mediatek/mt8183/Kconfig
11 files changed, 649 insertions(+), 8 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/51203/2
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Change subject: src/mediatek/common: Add DRAM common files
......................................................................
Patch Set 1:
(1 comment)
Patchset:
PS1:
Hmmm. Can you try to do 'move' instead of 'add'?
I think most files here are identical to the 8192 implementation, so we can just say "Move DRAM implementation from 8192 to common"
That's easier to prevent reviewing every files again.
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