Hello Bora Guvendik, build bot (Jenkins), Patrick Georgi, Martin Roth, Selma Bensaid, Varun Joshi, Thejaswani Putta, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
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Change subject: soc/intel/tigerlake: Add romstage common stage file
......................................................................
soc/intel/tigerlake: Add romstage common stage file
Signed-off-by: Bernardo Perez Priego <bernardo.perez.priego(a)intel.com>
Change-Id: I9480649aedd9f3aee1033b8f53dd0be03877e338
---
M src/soc/intel/tigerlake/Kconfig
M src/soc/intel/tigerlake/Makefile.inc
M src/soc/intel/tigerlake/include/soc/romstage.h
M src/soc/intel/tigerlake/romstage/Makefile.inc
M src/soc/intel/tigerlake/romstage/fsp_params.c
D src/soc/intel/tigerlake/romstage/pch.c
M src/soc/intel/tigerlake/romstage/romstage.c
7 files changed, 18 insertions(+), 144 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/22/39222/6
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Change subject: security/intel/txt: Add weak function to skip TXT lockdown
......................................................................
Patch Set 1:
(1 comment)
File src/security/intel/txt/txt.h:
https://review.coreboot.org/c/coreboot/+/50236/comment/6561684b_485b81d4
PS1, Line 29: /* Allow platform override to skip TXT init, e.g. required for RAS error injection. */
skip TXT lockdown
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Hello build bot (Jenkins), Patrick Georgi, David Hendricks, Paul Menzel,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/49310
to look at the new patch set (#8).
Change subject: util/board_status/board_status.sh: build the cbmem binary when absent
......................................................................
util/board_status/board_status.sh: build the cbmem binary when absent
Signed-off-by: Idwer Vollering <vidwer(a)gmail.com>
Change-Id: Ia6442e8ba5e789fc5eab89b6796ec45635f1e923
---
M util/board_status/board_status.sh
1 file changed, 11 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/10/49310/8
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Change subject: util/board_status/board_status.sh: absorb and inject user identification from the top-level git directory
......................................................................
Patch Set 7:
(1 comment)
File util/board_status/board_status.sh:
https://review.coreboot.org/c/coreboot/+/49311/comment/35ec0be1_7529be2b
PS7, Line 524: git_username="$(git config -f .git/config user.name)"
> What if the user set up their git configuration globally instead of locally, or didn't set these at […]
Which one should have precendence, the local settings?
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Change subject: hatch: Modify genesis PcieClkSrc settings
......................................................................
Patch Set 2:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/50101/comment/a829c4b3_e879169c
PS2, Line 9: to work around issue with Longsys SSD
> My understanding of hybrid storage devices is that there are two devices seen on two separate PCIe RPs, but they share the same CLKSRC. Thus, while configuring these RPs in devicetree, you need to set both as enabled, but configure CLKSRC for only one of those.
That matches my expectations as well, hence my surprise by this patch from Quanta.
> > After chatting again with them, I confirmed this new SSD module is a raw PCIe drive (not SATA). Apparently the original settings only supported SATA drives.
> I don't think that is accurate. SATA does not really require the CLKSRC/CLKREQ programming.
TBH I didn't even know raw PCIe SSDs were a thing 😕. I'll work in Quanta once I get my hands on this SSD module; this is all new to me.
> I don't think there is clear understanding of the problem or how the change is really helping. I would recommend ensuring the design is understood and then translating that into appropriate device tree configs.
100% agree. I've decided to leave this review open until we better understand the situation. Quanta agreed to simply not use this SSD module for now.
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Change subject: soc/intel/cannonlake: Configure GPIOs again after FSP-S is done
......................................................................
Patch Set 5:
(1 comment)
Patchset:
PS5:
> Padcfg gets locked down by FSP anyways before any payload / OS starts.
I think it is configurable using `PchUnlockGpioPads`
> Well, as already mentioned, see CB:45211. All these UPDs will change pad config.
Oh okay. Since there was no follow-up change in that series, it was not clear how the missing special function pads were utilized at mainboard level.
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Change subject: soc/intel/*: drop UART pad configuration from common code
......................................................................
Patch Set 26:
(1 comment)
Patchset:
PS26:
> Shouldn't, but it does :/ see current discussion at CB:48340. I'll check if we can do anything for platforms without the new UPD
Ouch, sorry guys, I didn't mean CB:48340 but CB:31250.
@Tim have a look at CB:45211, please. These UPDs will change pad config. I wouldn't call that *sometimes* :/
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