coreboot-gerrit February 2021

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Change in coreboot[master]: soc/amd/cezanne: populate some FSP-M UPDs
by Felix Held (Code Review) 02 Feb '21

02 Feb '21

Attention is currently required from: Justin Frodsham, Jason Glenesk, Marshall Dawson. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50239 ) Change subject: soc/amd/cezanne: populate some FSP-M UPDs ...................................................................... Patch Set 2: -Code-Review -- To view, visit https://review.coreboot.org/c/coreboot/+/50239 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I81a812662f921d0bf8d436238d338b6a1fa6a9ee Gerrit-Change-Number: 50239 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Justin Frodsham <justin.frodsham(a)amd.corp-partner.google.com> Gerrit-Attention: Justin Frodsham <justin.frodsham(a)amd.corp-partner.google.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Comment-Date: Tue, 02 Feb 2021 21:24:46 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: nb/intel/pineview/bootblock.c: include <arch/pci_io_cfg.h>
by HAOUAS Elyes (Code Review) 02 Feb '21

02 Feb '21

HAOUAS Elyes has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/49539 ) Change subject: nb/intel/pineview/bootblock.c: include <arch/pci_io_cfg.h> ...................................................................... Abandoned -- To view, visit https://review.coreboot.org/c/coreboot/+/49539 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic82876433361e206be4c71d71bbc4b4e95213479 Gerrit-Change-Number: 49539 Gerrit-PatchSet: 3 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Damien Zammit Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: abandon

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Change in coreboot[master]: vendorcode/amd/fsp/cezanne: add UPD structs from FSP build
by Felix Held (Code Review) 02 Feb '21

02 Feb '21

Attention is currently required from: Justin Frodsham. Hello Justin Frodsham, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/50242 to review the following change. Change subject: vendorcode/amd/fsp/cezanne: add UPD structs from FSP build ...................................................................... vendorcode/amd/fsp/cezanne: add UPD structs from FSP build There will be incompatible changes during the further development of the coreboot+FSP support for Cezanne, but we do need the FSP-M UPD struct size to match the one in the FSP header. See CB:50241 for details. Signed-off-by: Justin Frodsham <justin.frodsham(a)protonmail.com> Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: Icade1d7bcab7b85cdd25c4114590eb23b914edcd --- M src/vendorcode/amd/fsp/cezanne/FspmUpd.h M src/vendorcode/amd/fsp/cezanne/FspsUpd.h 2 files changed, 99 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/42/50242/1 diff --git a/src/vendorcode/amd/fsp/cezanne/FspmUpd.h b/src/vendorcode/amd/fsp/cezanne/FspmUpd.h index 338133c..960d0b4 100644 --- a/src/vendorcode/amd/fsp/cezanne/FspmUpd.h +++ b/src/vendorcode/amd/fsp/cezanne/FspmUpd.h @@ -12,7 +12,61 @@ /** Fsp M Configuration **/ typedef struct __packed { - uint16_t UpdTerminator; + /** Offset 0x0040**/ uint32_t pci_express_base_addr; + /** Offset 0x0044**/ uint32_t serial_port_base; + /** Offset 0x0048**/ uint32_t serial_port_use_mmio; + /** Offset 0x004C**/ uint32_t serial_port_stride; + /** Offset 0x0050**/ uint32_t serial_port_baudrate; + /** Offset 0x0054**/ uint32_t serial_port_refclk; + /** Offset 0x0058**/ uint32_t telemetry_vddcr_vdd_slope_mA; + /** Offset 0x005C**/ uint32_t telemetry_vddcr_vdd_slope2_mA; + /** Offset 0x0060**/ uint32_t telemetry_vddcr_vdd_slope3_mA; + /** Offset 0x0064**/ uint32_t telemetry_vddcr_vdd_slope4_mA; + /** Offset 0x0068**/ uint32_t telemetry_vddcr_vdd_slope5_mA; + /** Offset 0x006C**/ uint32_t telemetry_vddcr_vdd_offset; + /** Offset 0x0070**/ uint32_t telemetry_vddcr_soc_slope_mA; + /** Offset 0x0074**/ uint32_t telemetry_vddcr_soc_offset; + /** Offset 0x0078**/ uint8_t aa_mode_en; + /** Offset 0x0079**/ uint8_t unused2; + /** Offset 0x007A**/ uint8_t unused3; + /** Offset 0x007B**/ uint8_t unused4; + /** Offset 0x007C**/ uint32_t fast_ppt_limit_mW; + /** Offset 0x0080**/ uint32_t slow_ppt_limit_mW; + /** Offset 0x0084**/ uint32_t slow_ppt_time_constant_s; + /** Offset 0x0088**/ uint32_t psi0_current_limit_mA; + /** Offset 0x008C**/ uint32_t psi0_soc_current_limit_mA; + /** Offset 0x0090**/ uint32_t thermctl_limit_degreeC; + /** Offset 0x0094**/ uint32_t vrm_maximum_current_limit_mA; + /** Offset 0x0098**/ uint32_t vrm_soc_maximum_current_limit_mA; + /** Offset 0x009C**/ uint32_t sustained_power_limit_mW; + /** Offset 0x00A0**/ uint32_t stapm_time_constant_s; + /** Offset 0x00A4**/ uint32_t prochot_l_deassertion_ramp_time_ms; + /** Offset 0x00A8**/ uint32_t vrm_current_limit_mA; + /** Offset 0x00AC**/ uint32_t vrm_soc_current_limit_mA; + /** Offset 0x00B0**/ uint32_t vddcr_soc_voltage_margin_mV; + /** Offset 0x00B4**/ uint32_t vddcr_vdd_voltage_margin_mV; + /** Offset 0x00B8**/ uint32_t smu_feature_control_defines; + /** Offset 0x00BC**/ uint32_t smu_feature_control_defines_ext; + /** Offset 0x00C0**/ uint8_t sb_tsi_alert_comparator_mode_en; + /** Offset 0x00C1**/ uint8_t system_config; + /** Offset 0x00C2**/ uint8_t core_dldo_bypass; + /** Offset 0x00C3**/ uint8_t min_soc_vid_offset; + /** Offset 0x00C4**/ uint8_t aclk_dpm0_freq_400MHz; + /** Offset 0x00C5**/ uint8_t unused5; + /** Offset 0x00C6**/ uint8_t unused6; + /** Offset 0x00C7**/ uint8_t sata_enable; + /** Offset 0x00C8**/ uint32_t tseg_size; + /** Offset 0x00CC**/ uint8_t pspp_policy; + /** Offset 0x00CD**/ uint8_t audio_soundwire; + /** Offset 0x00CE**/ uint8_t hd_audio_enable; + /** Offset 0x00CF**/ uint8_t unused9; + /** Offset 0x00D0**/ uint32_t bert_size; + /** Offset 0x00D4**/ uint8_t UnusedUpdSpace0; + /** Offset 0x00D5**/ uint8_t ccx_down_core_mode; + /** Offset 0x00D6**/ uint8_t ccx_disable_smt; + /** Offset 0x00D7**/ uint8_t UnusedUpdSpace1[41]; + /** Offset 0x0100**/ uint16_t Reserved100; + /** Offset 0x0102**/ uint16_t UpdTerminator; } FSP_M_CONFIG; /** Fsp M UPD Configuration diff --git a/src/vendorcode/amd/fsp/cezanne/FspsUpd.h b/src/vendorcode/amd/fsp/cezanne/FspsUpd.h index 2b7f19c..d4f8aea 100644 --- a/src/vendorcode/amd/fsp/cezanne/FspsUpd.h +++ b/src/vendorcode/amd/fsp/cezanne/FspsUpd.h @@ -10,7 +10,50 @@ #include <FspUpd.h> typedef struct __packed { - uint16_t UpdTerminator; + /** Offset 0x0020**/ uint32_t emmc0_mode; + /** Offset 0x0024**/ uint16_t emmc0_init_khz_preset; + /** Offset 0x0026**/ uint8_t emmc0_sdr104_hs400_driver_strength; + /** Offset 0x0027**/ uint8_t emmc0_ddr50_driver_strength; + /** Offset 0x0028**/ uint8_t emmc0_sdr50_driver_strength; + /** Offset 0x0029**/ uint8_t unused0[7]; + /** Offset 0x0030**/ uint8_t dxio_descriptor0[16]; + /** Offset 0x0040**/ uint8_t dxio_descriptor1[16]; + /** Offset 0x0050**/ uint8_t dxio_descriptor2[16]; + /** Offset 0x0060**/ uint8_t dxio_descriptor3[16]; + /** Offset 0x0070**/ uint8_t dxio_descriptor4[16]; + /** Offset 0x0080**/ uint8_t dxio_descriptor5[16]; + /** Offset 0x0090**/ uint8_t dxio_descriptor6[16]; + /** Offset 0x00A0**/ uint8_t dxio_descriptor7[16]; + /** Offset 0x00B0**/ uint8_t unused1[16]; + /** Offset 0x00C0**/ uint32_t ddi_descriptor0; + /** Offset 0x00C4**/ uint32_t ddi_descriptor1; + /** Offset 0x00C8**/ uint32_t ddi_descriptor2; + /** Offset 0x00CC**/ uint32_t ddi_descriptor3; + /** Offset 0x00D0**/ uint8_t unused2[16]; + /** Offset 0x00E0**/ uint8_t fch_usb_version_major; + /** Offset 0x00E1**/ uint8_t fch_usb_version_minor; + /** Offset 0x00E2**/ uint8_t fch_usb_2_port0_phy_tune[9]; + /** Offset 0x00EB**/ uint8_t fch_usb_2_port1_phy_tune[9]; + /** Offset 0x00F4**/ uint8_t fch_usb_2_port2_phy_tune[9]; + /** Offset 0x00FD**/ uint8_t fch_usb_2_port3_phy_tune[9]; + /** Offset 0x0106**/ uint8_t fch_usb_2_port4_phy_tune[9]; + /** Offset 0x010F**/ uint8_t fch_usb_2_port5_phy_tune[9]; + /** Offset 0x0118**/ uint8_t fch_usb_device_removable; + /** Offset 0x0119**/ uint8_t fch_usb_3_port_force_gen1; + /** Offset 0x011A**/ uint8_t fch_usb_u3_rx_det_wa_enable; + /** Offset 0x011B**/ uint8_t fch_usb_u3_rx_det_wa_portmap; + /** Offset 0x011C**/ uint8_t fch_usb_early_debug_select_enable; + /** Offset 0x011D**/ uint8_t unused3; + /** Offset 0x011E**/ uint32_t xhci_oc_pin_select; + /** Offset 0x0122**/ uint8_t xhci0_force_gen1; + /** Offset 0x0123**/ uint8_t xhci_sparse_mode_enable; + /** Offset 0x0124**/ uint32_t gnb_ioapic_base; + /** Offset 0x0128**/ uint8_t gnb_ioapic_id; + /** Offset 0x0129**/ uint8_t fch_ioapic_id; + /** Offset 0x012A**/ uint8_t UnusedUpdSpace0[6]; + /** Offset 0x0130**/ uint8_t unused4[16]; + /** Offset 0x0140**/ uint8_t UnusedUpdSpace1[16]; + /** Offset 0x0150**/ uint16_t UpdTerminator; } FSP_S_CONFIG; /** Fsp S UPD Configuration -- To view, visit https://review.coreboot.org/c/coreboot/+/50242 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icade1d7bcab7b85cdd25c4114590eb23b914edcd Gerrit-Change-Number: 50242 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Justin Frodsham <justin.frodsham(a)protonmail.com> Gerrit-Attention: Justin Frodsham <justin.frodsham(a)protonmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/amd/cezanne: populate some FSP-M UPDs
by Felix Held (Code Review) 02 Feb '21

02 Feb '21

Attention is currently required from: Justin Frodsham, Jason Glenesk, Marshall Dawson. Hello build bot (Jenkins), Jason Glenesk, Raul Rangel, Marshall Dawson, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/50239 to look at the new patch set (#2). Change subject: soc/amd/cezanne: populate some FSP-M UPDs ...................................................................... soc/amd/cezanne: populate some FSP-M UPDs Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I81a812662f921d0bf8d436238d338b6a1fa6a9ee --- M src/soc/amd/cezanne/romstage.c 1 file changed, 9 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/39/50239/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/50239 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I81a812662f921d0bf8d436238d338b6a1fa6a9ee Gerrit-Change-Number: 50239 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Justin Frodsham <justin.frodsham(a)amd.corp-partner.google.com> Gerrit-Attention: Justin Frodsham <justin.frodsham(a)amd.corp-partner.google.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: nb/intel/x/bootblock.c Revert `include <arch/pci_io_cfg.h>`
by HAOUAS Elyes (Code Review) 02 Feb '21

02 Feb '21

Attention is currently required from: Damien Zammit, Angel Pons, Patrick Rudolph. HAOUAS Elyes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50231 ) Change subject: nb/intel/x/bootblock.c Revert `include <arch/pci_io_cfg.h>` ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/50231 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifba05717dad404a844618815c5347a05e07a3362 Gerrit-Change-Number: 50231 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Damien Zammit Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Damien Zammit Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Tue, 02 Feb 2021 21:22:54 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: drivers/intel/fsp2_0/memory_init: check if UPD struct has expected size
by Justin Frodsham (Code Review) 02 Feb '21

02 Feb '21

Attention is currently required from: Furquan Shaikh, Subrata Banik, Andrey Petrov, Patrick Rudolph, Felix Held. Justin Frodsham has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50241 ) Change subject: drivers/intel/fsp2_0/memory_init: check if UPD struct has expected size ...................................................................... Patch Set 1: Code-Review+1 (1 comment) Patchset: PS1: Looks good. -- To view, visit https://review.coreboot.org/c/coreboot/+/50241 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia7e9f6f20d0091bbb4abfd42abb40b485da2079d Gerrit-Change-Number: 50241 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Justin Frodsham <justin.frodsham(a)amd.corp-partner.google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Tue, 02 Feb 2021 20:49:40 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: [WIP] soc/amd/picasso: add UPD for USB3 phy setting adjsut
by Chris Wang (Code Review) 02 Feb '21

02 Feb '21

Attention is currently required from: Jason Glenesk, Raul Rangel, Marshall Dawson, chris wang, Felix Held. Chris Wang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50240 ) Change subject: [WIP] soc/amd/picasso: add UPD for USB3 phy setting adjsut ...................................................................... Patch Set 2: (4 comments) File src/soc/amd/picasso/fsp_params.c: https://review.coreboot.org/c/coreboot/+/50240/comment/f20cfeb0_ca072b9a PS1, Line 131: memcpy (&scfg->usb_3_port0_phy_tune, &cfg->usb3_phy_tune_params[0], > space prohibited between function name and open parenthesis '(' done https://review.coreboot.org/c/coreboot/+/50240/comment/572dbeb3_b5b03f30 PS1, Line 133: memcpy (&scfg->usb_3_port1_phy_tune, &cfg->usb3_phy_tune_params[1], > space prohibited between function name and open parenthesis '(' done https://review.coreboot.org/c/coreboot/+/50240/comment/7d4e65b0_ac051a72 PS1, Line 135: memcpy (&scfg->usb_3_port2_phy_tune, &cfg->usb3_phy_tune_params[2], > space prohibited between function name and open parenthesis '(' done https://review.coreboot.org/c/coreboot/+/50240/comment/cb410b30_55021681 PS1, Line 137: memcpy (&scfg->usb_3_port3_phy_tune, &cfg->usb3_phy_tune_params[3], > space prohibited between function name and open parenthesis '(' done -- To view, visit https://review.coreboot.org/c/coreboot/+/50240 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1d5f69e840952cc5171af1ce8597628d1bede5cb Gerrit-Change-Number: 50240 Gerrit-PatchSet: 2 Gerrit-Owner: chris wang <Chris.Wang(a)amd.com> Gerrit-Reviewer: Chris Wang <chris.wang(a)amd.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: chris wang <Chris.Wang(a)amd.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Tue, 02 Feb 2021 20:45:53 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: comment

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Change in coreboot[master]: drivers/intel/fsp2_0/memory_init: check if UPD struct has expected size
by Felix Held (Code Review) 02 Feb '21

02 Feb '21

Attention is currently required from: Furquan Shaikh, Subrata Banik, Andrey Petrov, Patrick Rudolph. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50241 ) Change subject: drivers/intel/fsp2_0/memory_init: check if UPD struct has expected size ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: this patch should be tested against all SoCs that use FSP 2.x before it gets merged -- To view, visit https://review.coreboot.org/c/coreboot/+/50241 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia7e9f6f20d0091bbb4abfd42abb40b485da2079d Gerrit-Change-Number: 50241 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Tue, 02 Feb 2021 20:45:22 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: [WIP] soc/amd/picasso: add UPD for USB3 phy setting adjsut
by chris wang (Code Review) 02 Feb '21

02 Feb '21

Attention is currently required from: Jason Glenesk, Raul Rangel, Marshall Dawson, Chris Wang, Felix Held. Hello Jason Glenesk, Raul Rangel, Marshall Dawson, Chris Wang, Felix Held, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/50240 to look at the new patch set (#2). Change subject: [WIP] soc/amd/picasso: add UPD for USB3 phy setting adjsut ...................................................................... [WIP] soc/amd/picasso: add UPD for USB3 phy setting adjsut add UPD for USB3 phy setting adjust Usb 3.1 PHY Parameters: 1. RX_EQ_DELTA_IQ_OVRD_VAL- Override value for rx_eq_delta_iq. Range 0-0xF 2. RX_EQ_DELTA_IQ_OVRD_EN - Enable override value for rx_eq_delta_iq. Range 0-0x1 3. Override value for rx_vref_ctrl. Range 0 - 0x1F 4. Enable override value for rx_vref_ctrl. Range 0 - 0x1 5. Override value for tx_vboost_lvl: 0 - 0x7. 6. Enable override value for tx_vboost_lvl. Range: 0 - 0x1 7. Override value for rx_vref_ctrl. Range 0 - 0x1F 8. Enable override value for rx_vref_ctrl. Range 0 - 0x1 9. Override value for tx_vboost_lvl: 0 - 0x7. 10. Enable override value for tx_vboost_lvl. Range: 0 - 0x1 BUG=b:175192931 TEST=Build Change-Id: I1d5f69e840952cc5171af1ce8597628d1bede5cb Signed-off-by: Chris Wang <chris.wang(a)amd.corp-partner.google.com> --- M src/soc/amd/picasso/chip.h M src/soc/amd/picasso/fsp_params.c M src/vendorcode/amd/fsp/picasso/FspsUpd.h 3 files changed, 80 insertions(+), 21 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/40/50240/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/50240 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1d5f69e840952cc5171af1ce8597628d1bede5cb Gerrit-Change-Number: 50240 Gerrit-PatchSet: 2 Gerrit-Owner: chris wang <Chris.Wang(a)amd.com> Gerrit-Reviewer: Chris Wang <chris.wang(a)amd.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Chris Wang <chris.wang(a)amd.corp-partner.google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: drivers/intel/fsp2_0/memory_init: check if UPD struct has expected size
by Felix Held (Code Review) 02 Feb '21

02 Feb '21

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/50241 ) Change subject: drivers/intel/fsp2_0/memory_init: check if UPD struct has expected size ...................................................................... drivers/intel/fsp2_0/memory_init: check if UPD struct has expected size If the UPD size in coreboot sizes mismatches the one from the FSP-M binary, call die(). We ran into the issue in soc/amd/cezanne, where the UPD struct in coreboot was smaller than the one in the FSP, so the defaults didn't get completely copied. TEST=Mandolin still boots. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: Ia7e9f6f20d0091bbb4abfd42abb40b485da2079d --- M src/drivers/intel/fsp2_0/memory_init.c 1 file changed, 3 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/41/50241/1 diff --git a/src/drivers/intel/fsp2_0/memory_init.c b/src/drivers/intel/fsp2_0/memory_init.c index 92f3d9d..aba8447 100644 --- a/src/drivers/intel/fsp2_0/memory_init.c +++ b/src/drivers/intel/fsp2_0/memory_init.c @@ -239,6 +239,9 @@ upd = (FSPM_UPD *)(hdr->cfg_region_offset + hdr->image_base); + if (hdr->cfg_region_size != sizeof(FSPM_UPD)) + die("FSPM_UPD struct size doesn't match expected UPD size.\n"); + fsp_verify_upd_header_signature(upd->FspUpdHeader.Signature, FSPM_UPD_SIGNATURE); /* Copy the default values from the UPD area */ -- To view, visit https://review.coreboot.org/c/coreboot/+/50241 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia7e9f6f20d0091bbb4abfd42abb40b485da2079d Gerrit-Change-Number: 50241 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

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coreboot-gerrit February 2021