coreboot-gerrit February 2021

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Change in coreboot[master]: util/board_status/board_status.sh: build the cbmem binary when absent
by Idwer Vollering (Code Review) 02 Feb '21

02 Feb '21

Attention is currently required from: David Hendricks. Idwer Vollering has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49310 ) Change subject: util/board_status/board_status.sh: build the cbmem binary when absent ...................................................................... Patch Set 8: (1 comment) File util/board_status/board_status.sh: https://review.coreboot.org/c/coreboot/+/49310/comment/0fcb6f51_e924a0da PS7, Line 416: [ ! -x util/cbmem/cbmem ]; then > Should these changes to in the 'else' clause? '-n' tests if the string is not empty, in which case t […] Should the built cbmem binary be removed afterwards? -- To view, visit https://review.coreboot.org/c/coreboot/+/49310 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia6442e8ba5e789fc5eab89b6796ec45635f1e923 Gerrit-Change-Number: 49310 Gerrit-PatchSet: 8 Gerrit-Owner: Idwer Vollering <vidwer(a)gmail.com> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Comment-Date: Tue, 02 Feb 2021 20:40:40 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: David Hendricks <david.hendricks(a)gmail.com> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/*: drop UART pad configuration from common code
by Tim Wawrzynczak (Code Review) 02 Feb '21

02 Feb '21

Attention is currently required from: Lance Zhao, Nico Huber, Michael Niewöhner. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48829 ) Change subject: soc/intel/*: drop UART pad configuration from common code ...................................................................... Patch Set 26: (1 comment) Patchset: PS26: > @Tim you were probably speaking of TGL/JSL, where GpioOverride was introduced. […] Sorry yes, that's what I meant, for newer FSPs we were able to get the gpio override UPD added -- To view, visit https://review.coreboot.org/c/coreboot/+/48829 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id03719eb8bd0414083148471ed05dea62a895126 Gerrit-Change-Number: 48829 Gerrit-PatchSet: 26 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Lance Zhao Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Lance Zhao Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Comment-Date: Tue, 02 Feb 2021 20:40:40 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Lance Zhao Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Comment-In-Reply-To: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-MessageType: comment

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Change in coreboot[master]: [WIP] soc/amd/picasso: add UPD for USB3 phy setting adjsut
by build bot (Jenkins) (Code Review) 02 Feb '21

02 Feb '21

Attention is currently required from: Jason Glenesk, Raul Rangel, Marshall Dawson, Chris Wang, Felix Held. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50240 ) Change subject: [WIP] soc/amd/picasso: add UPD for USB3 phy setting adjsut ...................................................................... Patch Set 1: (4 comments) File src/soc/amd/picasso/fsp_params.c: https://review.coreboot.org/c/coreboot/+/50240/comment/6a46b62a_af1a1117 PS1, Line 131: memcpy (&scfg->usb_3_port0_phy_tune, &cfg->usb3_phy_tune_params[0], space prohibited between function name and open parenthesis '(' https://review.coreboot.org/c/coreboot/+/50240/comment/30605882_4d4c8315 PS1, Line 133: memcpy (&scfg->usb_3_port1_phy_tune, &cfg->usb3_phy_tune_params[1], space prohibited between function name and open parenthesis '(' https://review.coreboot.org/c/coreboot/+/50240/comment/93ed4e61_432b6336 PS1, Line 135: memcpy (&scfg->usb_3_port2_phy_tune, &cfg->usb3_phy_tune_params[2], space prohibited between function name and open parenthesis '(' https://review.coreboot.org/c/coreboot/+/50240/comment/588a38cf_cefe6bb8 PS1, Line 137: memcpy (&scfg->usb_3_port3_phy_tune, &cfg->usb3_phy_tune_params[3], space prohibited between function name and open parenthesis '(' -- To view, visit https://review.coreboot.org/c/coreboot/+/50240 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1d5f69e840952cc5171af1ce8597628d1bede5cb Gerrit-Change-Number: 50240 Gerrit-PatchSet: 1 Gerrit-Owner: chris wang <Chris.Wang(a)amd.com> Gerrit-Reviewer: Chris Wang <chris.wang(a)amd.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Chris Wang <chris.wang(a)amd.corp-partner.google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Tue, 02 Feb 2021 20:40:27 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: [WIP] soc/amd/picasso: add UPD for USB3 phy setting adjsut
by chris wang (Code Review) 02 Feb '21

02 Feb '21

Attention is currently required from: Chris Wang. Hello Chris Wang, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/50240 to review the following change. Change subject: [WIP] soc/amd/picasso: add UPD for USB3 phy setting adjsut ...................................................................... [WIP] soc/amd/picasso: add UPD for USB3 phy setting adjsut add UPD for USB3 phy setting adjust Usb 3.1 PHY Parameters: 1. RX_EQ_DELTA_IQ_OVRD_VAL- Override value for rx_eq_delta_iq. Range 0-0xF 2. RX_EQ_DELTA_IQ_OVRD_EN - Enable override value for rx_eq_delta_iq. Range 0-0x1 3. Override value for rx_vref_ctrl. Range 0 - 0x1F 4. Enable override value for rx_vref_ctrl. Range 0 - 0x1 5. Override value for tx_vboost_lvl: 0 - 0x7. 6. Enable override value for tx_vboost_lvl. Range: 0 - 0x1 7. Override value for rx_vref_ctrl. Range 0 - 0x1F 8. Enable override value for rx_vref_ctrl. Range 0 - 0x1 9. Override value for tx_vboost_lvl: 0 - 0x7. 10. Enable override value for tx_vboost_lvl. Range: 0 - 0x1 BUG=b:175192931 TEST=Build Change-Id: I1d5f69e840952cc5171af1ce8597628d1bede5cb Signed-off-by: Chris Wang <chris.wang(a)amd.corp-partner.google.com> --- M src/soc/amd/picasso/chip.h M src/soc/amd/picasso/fsp_params.c M src/vendorcode/amd/fsp/picasso/FspsUpd.h 3 files changed, 80 insertions(+), 21 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/40/50240/1 diff --git a/src/soc/amd/picasso/chip.h b/src/soc/amd/picasso/chip.h index 244d783..ca2c672 100644 --- a/src/soc/amd/picasso/chip.h +++ b/src/soc/amd/picasso/chip.h @@ -65,7 +65,14 @@ uint32_t rfmux_config; }; -#define USB_PORT_COUNT 6 +#define USB_PORT_COUNT 6 + +struct __packed usb3_phy_tune { + uint8_t rx_eq_delta_iq_ovrd_val; + uint8_t rx_eq_delta_iq_ovrd_en; +}; + +#define USB3_PORT_COUNT 4 #define USB_PD_PORT_COUNT 2 enum sd_emmc_driver_strength { @@ -247,6 +254,30 @@ USB_OC_NONE = 0xf, } usb_port_overcurrent_pin[USB_PORT_COUNT]; + /* Usb 3.1 PHY Parameters */ + uint8_t usb3_phy_en; + /* + * 1,RX_EQ_DELTA_IQ_OVRD_VAL- Override value for rx_eq_delta_iq. Range 0-0xF + * 2,RX_EQ_DELTA_IQ_OVRD_EN - Enable override value for rx_eq_delta_iq. Range 0-0x1 + */ + struct usb3_phy_tune usb3_phy_tune_params[USB3_PORT_COUNT]; + /* Override value for rx_vref_ctrl. Range 0 - 0x1F */ + uint8_t usb3_rx_vref_ctrl; + /* Enable override value for rx_vref_ctrl. Range 0 - 0x1 */ + uint8_t usb3_rx_vref_ctrl_en; + /* Override value for tx_vboost_lvl: 0 - 0x7. */ + uint8_t usb_3_tx_vboost_lvl; + /* Enable override value for tx_vboost_lvl. Range: 0 - 0x1 */ + uint8_t usb_3_tx_vboost_lvl_en; + /* Override value for rx_vref_ctrl. Range 0 - 0x1F.*/ + uint8_t usb_3_rx_vref_ctrl_x; + /* Enable override value for rx_vref_ctrl. Range 0 - 0x1. */ + uint8_t usb_3_rx_vref_ctrl_en_x; + /* Override value for tx_vboost_lvl: 0 - 0x7. */ + uint8_t usb_3_tx_vboost_lvl_x; + /* Enable override value for tx_vboost_lvl. Range: 0 - 0x1. */ + uint8_t usb_3_tx_vboost_lvl_en_x; + /* The array index is the general purpose PCIe clock output number. */ enum gpp_clk_req_setting gpp_clk_config[GPP_CLK_OUTPUT_COUNT]; /* If using an external 48MHz OSC for codec, will disable internal X48M_OSC */ diff --git a/src/soc/amd/picasso/fsp_params.c b/src/soc/amd/picasso/fsp_params.c index 731a564..cd0208f 100644 --- a/src/soc/amd/picasso/fsp_params.c +++ b/src/soc/amd/picasso/fsp_params.c @@ -126,6 +126,25 @@ scfg->xhci_oc_pin_select |= (cfg->usb_port_overcurrent_pin[i] & 0xf) << (i * 4); } + + if (cfg->usb3_phy_en) { + memcpy (&scfg->usb_3_port0_phy_tune, &cfg->usb3_phy_tune_params[0], + izeof(scfg->usb_3_port0_phy_tune[0])); + memcpy (&scfg->usb_3_port1_phy_tune, &cfg->usb3_phy_tune_params[1], + izeof(scfg->usb_3_port0_phy_tune[1])); + memcpy (&scfg->usb_3_port2_phy_tune, &cfg->usb3_phy_tune_params[2], + izeof(scfg->usb_3_port0_phy_tune[2])); + memcpy (&scfg->usb_3_port3_phy_tune, &cfg->usb3_phy_tune_params[3], + izeof(scfg->usb_3_port0_phy_tune[3])); + scfg->usb_3_rx_vref_ctrl = cfg->usb3_rx_vref_ctrl; + scfg->usb_3_rx_vref_ctrl_en = cfg->usb3_rx_vref_ctrl_en; + scfg->usb_3_tx_vboost_lvl = cfg->usb_3_tx_vboost_lvl; + scfg->usb_3_tx_vboost_lvl_en = cfg->usb_3_tx_vboost_lvl_en; + scfg->usb_3_rx_vref_ctrl_x = cfg->usb_3_rx_vref_ctrl_x; + scfg->usb_3_rx_vref_ctrl_en_x = cfg->usb_3_rx_vref_ctrl_en_x; + scfg->usb_3_tx_vboost_lvl_x = cfg->usb_3_tx_vboost_lvl_x; + scfg->usb_3_tx_vboost_lvl_en_x = cfg->usb_3_tx_vboost_lvl_en_x; + } } static void fsp_assign_ioapic_upds(FSP_S_CONFIG *scfg) diff --git a/src/vendorcode/amd/fsp/picasso/FspsUpd.h b/src/vendorcode/amd/fsp/picasso/FspsUpd.h index ee516f8..35758c2 100644 --- a/src/vendorcode/amd/fsp/picasso/FspsUpd.h +++ b/src/vendorcode/amd/fsp/picasso/FspsUpd.h @@ -39,26 +39,35 @@ /** Offset 0x0124**/ uint32_t gnb_ioapic_base; /** Offset 0x0128**/ uint8_t gnb_ioapic_id; /** Offset 0x0129**/ uint8_t fch_ioapic_id; - /** Offset 0x012A**/ uint8_t UnusedUpdSpace0[6]; - /** Offset 0x0130**/ uint8_t unused4; - /** Offset 0x0131**/ uint8_t DpPhyOverride; - /** Offset 0x0132**/ uint16_t EDpPhySel; - /** Offset 0x0134**/ uint8_t EDpVersion; - /** Offset 0x0135**/ uint8_t EDpTableSize; - /** Offset 0x0136**/ uint8_t DpVsPemphLevel; - /** Offset 0x0137**/ uint16_t MarginDeemPh; - /** Offset 0x0139**/ uint8_t Deemph6db4; - /** Offset 0x013A**/ uint8_t BoostAdj; - /** Offset 0x013B**/ uint16_t backlight_pwmhz; - /** Offset 0x013D**/ uint8_t pwron_digon_to_de; - /** Offset 0x013E**/ uint8_t pwron_de_to_varybl; - /** Offset 0x013F**/ uint8_t pwrdown_varybloff_to_de; - /** Offset 0x0140**/ uint8_t pwrdown_de_to_digoff; - /** Offset 0x0141**/ uint8_t pwroff_delay; - /** Offset 0x0142**/ uint8_t pwron_varybl_to_blon; - /** Offset 0x0143**/ uint8_t pwrdown_bloff_to_varybloff; - /** Offset 0x0144**/ uint8_t min_allowed_bl_level; - /** Offset 0x0145**/ uint8_t UnusedUpdSpace1[11]; + /** Offset 0x012A**/ uint16_t edp_phy_override; + /** Offset 0x012C**/ uint8_t edp_physel; + /** Offset 0x012D**/ uint8_t edp_dp_vs_pemph_level; + /** Offset 0x012E**/ uint16_t edp_margin_deemph; + /** Offset 0x0130**/ uint8_t edp_deemph_6db_4; + /** Offset 0x0131**/ uint8_t edp_boost_adj; + /** Offset 0x0132**/ uint16_t backlight_pwmhz; + /** Offset 0x0134**/ uint8_t pwron_digon_to_de; + /** Offset 0x0135**/ uint8_t pwron_de_to_varybl; + /** Offset 0x0136**/ uint8_t pwrdown_varybloff_to_de; + /** Offset 0x0137**/ uint8_t pwrdown_de_to_digoff; + /** Offset 0x0138**/ uint8_t pwroff_delay; + /** Offset 0x0139**/ uint8_t pwron_varybl_to_blon; + /** Offset 0x013A**/ uint8_t pwrdown_bloff_to_varybloff; + /** Offset 0x013B**/ uint8_t min_allowed_bl_level; + /** Offset 0x013C**/ uint8_t usb_3_phy_enable; + /** Offset 0x013D**/ uint8_t usb_3_port0_phy_tune[2]; + /** Offset 0x013F**/ uint8_t usb_3_port1_phy_tune[2]; + /** Offset 0x0141**/ uint8_t usb_3_port2_phy_tune[2]; + /** Offset 0x0143**/ uint8_t usb_3_port3_phy_tune[2]; + /** Offset 0x0145**/ uint8_t usb_3_rx_vref_ctrl; + /** Offset 0x0146**/ uint8_t usb_3_rx_vref_ctrl_en; + /** Offset 0x0147**/ uint8_t usb_3_tx_vboost_lvl; + /** Offset 0x0148**/ uint8_t usb_3_tx_vboost_lvl_en; + /** Offset 0x0149**/ uint8_t usb_3_rx_vref_ctrl_x; + /** Offset 0x014A**/ uint8_t usb_3_rx_vref_ctrl_en_x; + /** Offset 0x014B**/ uint8_t usb_3_tx_vboost_lvl_x; + /** Offset 0x014C**/ uint8_t usb_3_tx_vboost_lvl_en_x; + /** Offset 0x014D**/ uint8_t UnusedUpdSpace0[3]; /** Offset 0x0150**/ uint16_t UpdTerminator; } FSP_S_CONFIG; -- To view, visit https://review.coreboot.org/c/coreboot/+/50240 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1d5f69e840952cc5171af1ce8597628d1bede5cb Gerrit-Change-Number: 50240 Gerrit-PatchSet: 1 Gerrit-Owner: chris wang <Chris.Wang(a)amd.com> Gerrit-Reviewer: Chris Wang <chris.wang(a)amd.corp-partner.google.com> Gerrit-Attention: Chris Wang <chris.wang(a)amd.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/amd/cezanne: pass MMCONF base address to FSP via UPD
by Felix Held (Code Review) 02 Feb '21

02 Feb '21

Attention is currently required from: Justin Frodsham, Jason Glenesk, Marshall Dawson. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50239 ) Change subject: soc/amd/cezanne: pass MMCONF base address to FSP via UPD ...................................................................... Patch Set 1: Code-Review-2 (1 comment) Patchset: PS1: let's wait with this one; Justin found a problem while we were discussing things; will push a patch that tries to detect that problem soon, but need to test it first -- To view, visit https://review.coreboot.org/c/coreboot/+/50239 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I81a812662f921d0bf8d436238d338b6a1fa6a9ee Gerrit-Change-Number: 50239 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Justin Frodsham <justin.frodsham(a)amd.corp-partner.google.com> Gerrit-Attention: Justin Frodsham <justin.frodsham(a)amd.corp-partner.google.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Comment-Date: Tue, 02 Feb 2021 20:36:23 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/*: drop UART pad configuration from common code
by Michael Niewöhner (Code Review) 02 Feb '21

02 Feb '21

Attention is currently required from: Lance Zhao, Nico Huber, Tim Wawrzynczak. Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48829 ) Change subject: soc/intel/*: drop UART pad configuration from common code ...................................................................... Patch Set 26: (1 comment) Patchset: PS26: > > Shouldn't, but it does :/ see current discussion at CB:48340. […] @Tim you were probably speaking of TGL/JSL, where GpioOverride was introduced. So, we have a that problem with anything before TGL, where FSP touches pad config -- To view, visit https://review.coreboot.org/c/coreboot/+/48829 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id03719eb8bd0414083148471ed05dea62a895126 Gerrit-Change-Number: 48829 Gerrit-PatchSet: 26 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Lance Zhao Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Lance Zhao Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Comment-Date: Tue, 02 Feb 2021 20:32:51 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Lance Zhao Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Comment-In-Reply-To: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/volteer: update thermal table for Eldrid
by Tim Wawrzynczak (Code Review) 02 Feb '21

02 Feb '21

Attention is currently required from: Keith Short, Nick Vaccaro, Nick Chen. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50111 ) Change subject: mb/google/volteer: update thermal table for Eldrid ...................................................................... Patch Set 1: Code-Review+1 (1 comment) File src/mainboard/google/volteer/variants/eldrid/overridetree.cb: https://review.coreboot.org/c/coreboot/+/50111/comment/9ca11714_5177bff2 PS1, Line 104: 60.8 This will turn into `60` (it's an unsigned int type), did you mean 60? -- To view, visit https://review.coreboot.org/c/coreboot/+/50111 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2f1fe9a6de4dbb587b79cb8758c5458a3ae5d768 Gerrit-Change-Number: 50111 Gerrit-PatchSet: 1 Gerrit-Owner: Nick Chen <nick_xr_chen(a)wistron.corp-partner.google.com> Gerrit-Reviewer: Keith Short <keithshort(a)chromium.org> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Anfernee Chen <anfernee_chen(a)wistron.corp-partner.google.com> Gerrit-CC: Casper Chang <casper_chang(a)wistron.corp-partner.google.com> Gerrit-CC: Malik Hsu <malik_hsu(a)wistron.corp-partner.google.com> Gerrit-CC: Mark Hsieh <mark_hsieh(a)wistron.corp-partner.google.com> Gerrit-CC: Scott Chao <scott_chao(a)wistron.corp-partner.google.com> Gerrit-Attention: Keith Short <keithshort(a)chromium.org> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Attention: Nick Chen <nick_xr_chen(a)wistron.corp-partner.google.com> Gerrit-Comment-Date: Tue, 02 Feb 2021 20:30:59 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: drivers/intel/dptf: Add OEM variables support
by Tim Wawrzynczak (Code Review) 02 Feb '21

02 Feb '21

Attention is currently required from: Furquan Shaikh, Justin TerAvest, Sumeet R Pawnikar, Todd Broch, Aaron Durbin, Patrick Rudolph, Karthik Ramasubramanian. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50127 ) Change subject: drivers/intel/dptf: Add OEM variables support ...................................................................... Patch Set 1: (3 comments) File src/drivers/intel/dptf/dptf.c: https://review.coreboot.org/c/coreboot/+/50127/comment/6b676b82_b7dfab14 PS1, Line 129: DPTF_DEVICE_HID_EISAID If this is the correct _HID, then I think you'll also need a `_UID` of 0 for the DPTF device itself, and a `_UID` here of 1 since they share this _HID. https://review.coreboot.org/c/coreboot/+/50127/comment/779e3871_6fc55a3a PS1, Line 128: if (CONFIG(DPTF_USE_EISA_HID)) : acpigen_emit_eisaid(DPTF_DEVICE_HID_EISAID); If `DPTF_USE_EISA_HID` is not defined, then there will be an invalid `_HID` object here. If it's only supported by newer DPTF implementations, then it'll have to be the EISA type. https://review.coreboot.org/c/coreboot/+/50127/comment/d8847656_ea152a7f PS1, Line 248: acpigen_write_package(6); : acpigen_pop_len(); /* Scope */ This is just an empty package -- To view, visit https://review.coreboot.org/c/coreboot/+/50127 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iaf3cf7b40e9a441b41d0c659d76895a58669c2fb Gerrit-Change-Number: 50127 Gerrit-PatchSet: 1 Gerrit-Owner: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Justin TerAvest <teravest(a)chromium.org> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Todd Broch <tbroch(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Justin TerAvest <teravest(a)chromium.org> Gerrit-Attention: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Attention: Todd Broch <tbroch(a)chromium.org> Gerrit-Attention: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Tue, 02 Feb 2021 20:27:22 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/amd/cezanne: pass MMCONF base address to FSP via UPD
by Raul Rangel (Code Review) 02 Feb '21

02 Feb '21

Attention is currently required from: Justin Frodsham, Jason Glenesk, Marshall Dawson, Felix Held. Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50239 ) Change subject: soc/amd/cezanne: pass MMCONF base address to FSP via UPD ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/50239 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I81a812662f921d0bf8d436238d338b6a1fa6a9ee Gerrit-Change-Number: 50239 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Justin Frodsham <justin.frodsham(a)amd.corp-partner.google.com> Gerrit-Attention: Justin Frodsham <justin.frodsham(a)amd.corp-partner.google.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Tue, 02 Feb 2021 20:20:18 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/cannonlake: Configure GPIOs again after FSP-S is done
by Michael Niewöhner (Code Review) 02 Feb '21

02 Feb '21

Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31250 ) Change subject: soc/intel/cannonlake: Configure GPIOs again after FSP-S is done ...................................................................... Patch Set 5: (1 comment) Patchset: PS5: > > Padcfg gets locked down by FSP anyways before any payload / OS starts. > > I think it is configurable using `PchUnlockGpioPads` Ack. I wasn't aware that it's actually used. > > > Well, as already mentioned, see CB:45211. All these UPDs will change pad config. > > Oh okay. Since there was no follow-up change in that series, it was not clear how the missing special function pads were utilized at mainboard level. Yeah, I have a patch locally, but never pushed it because I realized later, that we should configure the UPDs in any case because we won't know when Intel does more than pad config in the future with some of these UPDs :S -- To view, visit https://review.coreboot.org/c/coreboot/+/31250 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7787aa8f185f633627bcedc7f23504bf4a5250b4 Gerrit-Change-Number: 31250 Gerrit-PatchSet: 5 Gerrit-Owner: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Comment-Date: Tue, 02 Feb 2021 20:09:23 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Furquan Shaikh <furquan(a)google.com> Comment-In-Reply-To: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-MessageType: comment

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coreboot-gerrit February 2021