coreboot-gerrit February 2021

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Change in coreboot[master]: soc/amd/picasso: Fix copy-paste error in macro definitions
by Felix Held (Code Review) 02 Feb '21

02 Feb '21

Attention is currently required from: Jason Glenesk, Raul Rangel, Bao Zheng, Marshall Dawson. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50232 ) Change subject: soc/amd/picasso: Fix copy-paste error in macro definitions ...................................................................... Patch Set 2: Code-Review+1 (1 comment) Patchset: PS2: I'll wait with the +2 until Jason had a chance to have a look as well, but this fix looks correct to me. thanks for spotting that -- To view, visit https://review.coreboot.org/c/coreboot/+/50232 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I78370e17d2396f77ab820771f93cf15957bcf674 Gerrit-Change-Number: 50232 Gerrit-PatchSet: 2 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Bao Zheng <zheng.bao(a)amd.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Bao Zheng <zheng.bao(a)amd.corp-partner.google.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Comment-Date: Tue, 02 Feb 2021 19:26:05 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: [TESTONLY]: Remove default CHROMEOS=y
by Nico Huber (Code Review) 02 Feb '21

02 Feb '21

Attention is currently required from: Kyösti Mälkki. Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50118 ) Change subject: [TESTONLY]: Remove default CHROMEOS=y ...................................................................... Patch Set 2: Code-Review+1 (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/50118/comment/0d214b69_374e72bb PS2, Line 7: [TESTONLY]: Remove default CHROMEOS=y It discussed this a little lately in CB:49056. What stalled me was the idea to first set up a linter to check for it. Otherwise, we'd keep circling. -- To view, visit https://review.coreboot.org/c/coreboot/+/50118 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I16fcf62a23dae1b21c77cee275c867f9c1de893b Gerrit-Change-Number: 50118 Gerrit-PatchSet: 2 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Furquan Shaikh <furquan(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-CC: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Comment-Date: Tue, 02 Feb 2021 19:25:27 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/amd/cezanne: pass MMCONF base address to FSP via UPD
by Felix Held (Code Review) 02 Feb '21

02 Feb '21

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/50239 ) Change subject: soc/amd/cezanne: pass MMCONF base address to FSP via UPD ...................................................................... soc/amd/cezanne: pass MMCONF base address to FSP via UPD Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I81a812662f921d0bf8d436238d338b6a1fa6a9ee --- M src/soc/amd/cezanne/romstage.c M src/vendorcode/amd/fsp/cezanne/FspmUpd.h 2 files changed, 4 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/39/50239/1 diff --git a/src/soc/amd/cezanne/romstage.c b/src/soc/amd/cezanne/romstage.c index f790def..0d0e953 100644 --- a/src/soc/amd/cezanne/romstage.c +++ b/src/soc/amd/cezanne/romstage.c @@ -8,6 +8,9 @@ void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version) { + FSP_M_CONFIG *mcfg = &mupd->FspmConfig; + + mcfg->pci_express_base_addr = CONFIG_MMCONF_BASE_ADDRESS; } asmlinkage void car_stage_entry(void) diff --git a/src/vendorcode/amd/fsp/cezanne/FspmUpd.h b/src/vendorcode/amd/fsp/cezanne/FspmUpd.h index 338133c..89f5fc7 100644 --- a/src/vendorcode/amd/fsp/cezanne/FspmUpd.h +++ b/src/vendorcode/amd/fsp/cezanne/FspmUpd.h @@ -12,6 +12,7 @@ /** Fsp M Configuration **/ typedef struct __packed { + /** Offset 0x0040**/ uint32_t pci_express_base_addr; uint16_t UpdTerminator; } FSP_M_CONFIG; -- To view, visit https://review.coreboot.org/c/coreboot/+/50239 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I81a812662f921d0bf8d436238d338b6a1fa6a9ee Gerrit-Change-Number: 50239 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

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Change in coreboot[master]: hatch: Modify genesis PcieClkSrc settings
by Furquan Shaikh (Code Review) 02 Feb '21

02 Feb '21

Attention is currently required from: Joe Tessler, Neill Corlett. Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50101 ) Change subject: hatch: Modify genesis PcieClkSrc settings ...................................................................... Patch Set 2: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/50101/comment/0da79e11_a7f85f5b PS2, Line 9: to work around issue with Longsys SSD Oops sorry missed your update. > This was required to support a specific SSD module on the M.2 slot that uses PCIe slots 11 & 12 as advertised for "NVMe hybrid storage devices". My understanding of hybrid storage devices is that there are two devices seen on two separate PCIe RPs, but they share the same CLKSRC. Thus, while configuring these RPs in devicetree, you need to set both as enabled, but configure CLKSRC for only one of those. And then FSP ensures that both root ports are configured to use the same SRC. I think it is hacky on FSPs part and is just a limitation of the API that FSP exposes. Anyways, in this case, I see that you dropped the CLKSRC part for RP11 and RP12 is marked as disabled. So, I am really not sure how RP11 clock is set up at all. > After chatting again with them, I confirmed this new SSD module is a raw PCIe drive (not SATA). Apparently the original settings only supported SATA drives. I don't think that is accurate. SATA does not really require the CLKSRC/CLKREQ programming. > Do you think this is sufficient / should be added to the commit message? Since this is limited to genesis, I am okay if you want to go ahead with this. But I don't think there is clear understanding of the problem or how the change is really helping. I would recommend ensuring the design is understood and then translating that into appropriate device tree configs. -- To view, visit https://review.coreboot.org/c/coreboot/+/50101 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I30c2179be9b9ddd50168a7f35be800e969800e10 Gerrit-Change-Number: 50101 Gerrit-PatchSet: 2 Gerrit-Owner: Neill Corlett <corlett(a)google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Joe Tessler <jrt(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Matthew Ziegelbaum <ziegs(a)google.com> Gerrit-Attention: Joe Tessler <jrt(a)google.com> Gerrit-Attention: Neill Corlett <corlett(a)google.com> Gerrit-Comment-Date: Tue, 02 Feb 2021 19:04:04 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Furquan Shaikh <furquan(a)google.com> Comment-In-Reply-To: Joe Tessler <jrt(a)google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/tigerlake: Add romstage common stage file
by build bot (Jenkins) (Code Review) 02 Feb '21

02 Feb '21

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39222 ) Change subject: soc/intel/tigerlake: Add romstage common stage file ...................................................................... Patch Set 5: (1 comment) File src/soc/intel/tigerlake/romstage/romstage.c: https://review.coreboot.org/c/coreboot/+/39222/comment/c467f26d_a58d0123 PS5, Line 25: void romstage_mb_post_mem_init() Bad function definition - void romstage_mb_post_mem_init() should probably be void romstage_mb_post_mem_init(void) -- To view, visit https://review.coreboot.org/c/coreboot/+/39222 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9480649aedd9f3aee1033b8f53dd0be03877e338 Gerrit-Change-Number: 39222 Gerrit-PatchSet: 5 Gerrit-Owner: Bernardo Perez Priego <bernardo.perez.priego(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-Reviewer: Thejaswani Putta <thejaswani.putta(a)intel.com> Gerrit-Reviewer: Varun Joshi <varun.joshi(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Tue, 02 Feb 2021 19:03:17 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/tigerlake: Add romstage common stage file
by Bernardo Perez Priego (Code Review) 02 Feb '21

02 Feb '21

Hello Bora Guvendik, build bot (Jenkins), Patrick Georgi, Martin Roth, Selma Bensaid, Varun Joshi, Thejaswani Putta, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/39222 to look at the new patch set (#5). Change subject: soc/intel/tigerlake: Add romstage common stage file ...................................................................... soc/intel/tigerlake: Add romstage common stage file Signed-off-by: Bernardo Perez Priego <bernardo.perez.priego(a)intel.com> Change-Id: I9480649aedd9f3aee1033b8f53dd0be03877e338 --- M src/soc/intel/tigerlake/Kconfig M src/soc/intel/tigerlake/Makefile.inc M src/soc/intel/tigerlake/include/soc/romstage.h M src/soc/intel/tigerlake/romstage/Makefile.inc M src/soc/intel/tigerlake/romstage/fsp_params.c D src/soc/intel/tigerlake/romstage/pch.c M src/soc/intel/tigerlake/romstage/romstage.c 7 files changed, 18 insertions(+), 144 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/22/39222/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/39222 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9480649aedd9f3aee1033b8f53dd0be03877e338 Gerrit-Change-Number: 39222 Gerrit-PatchSet: 5 Gerrit-Owner: Bernardo Perez Priego <bernardo.perez.priego(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-Reviewer: Thejaswani Putta <thejaswani.putta(a)intel.com> Gerrit-Reviewer: Varun Joshi <varun.joshi(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/cannonlake: Configure GPIOs again after FSP-S is done
by Furquan Shaikh (Code Review) 02 Feb '21

02 Feb '21

Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31250 ) Change subject: soc/intel/cannonlake: Configure GPIOs again after FSP-S is done ...................................................................... Patch Set 5: (1 comment) Patchset: PS5: > I have some insane idea \o/ My first thought was, why not set PadCfgLock, so FSP can't write the pad […] Ugh.. I think it would be better to have FSP<->coreboot work in a more synchronized fashion than having to actively prevent what the other is doing. Locking down the padcfg will lead to other side-effects as well -- payloads, OS would run into issues trying to reconfigure pads, which won't be acceptable. Are you seeing cases where the FSP is still configuring GPIOs it should not? -- To view, visit https://review.coreboot.org/c/coreboot/+/31250 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7787aa8f185f633627bcedc7f23504bf4a5250b4 Gerrit-Change-Number: 31250 Gerrit-PatchSet: 5 Gerrit-Owner: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Comment-Date: Tue, 02 Feb 2021 18:57:15 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Furquan Shaikh <furquan(a)google.com> Comment-In-Reply-To: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/xeon_sp: Skip Locking down TXT related registers
by Angel Pons (Code Review) 02 Feb '21

02 Feb '21

Attention is currently required from: Jonathan Zhang, Arthur Heymans, Patrick Rudolph. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50238 ) Change subject: soc/intel/xeon_sp: Skip Locking down TXT related registers ...................................................................... Patch Set 1: Code-Review+1 (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/50238/comment/1e405cb3_54b07146 PS1, Line 7: Locking Any particular reason to capitalize `Locking` ? -- To view, visit https://review.coreboot.org/c/coreboot/+/50238 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ieef25c02ec103eaef65d8b44467ccb9e6917bb6c Gerrit-Change-Number: 50238 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Tue, 02 Feb 2021 18:46:18 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/ocp/deltalake: Implement skipping TXT lockdown via VPD
by Angel Pons (Code Review) 02 Feb '21

02 Feb '21

Attention is currently required from: Anjaneya "Reddy" Chagam, Patrick Rudolph, Jonathan Zhang, Johnny Lin, Arthur Heymans, Morgan Jang. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50237 ) Change subject: mb/ocp/deltalake: Implement skipping TXT lockdown via VPD ...................................................................... Patch Set 1: (1 comment) File src/mainboard/ocp/deltalake/ramstage.c: https://review.coreboot.org/c/coreboot/+/50237/comment/69a0619c_59e1b5b8 PS1, Line 368: static bool fetched_vpd = 0; Do you really need to cache this? The function is only called once -- To view, visit https://review.coreboot.org/c/coreboot/+/50237 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic5daf96bdda9c36054c410b07b08bcd3482d777c Gerrit-Change-Number: 50237 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Anjaneya "Reddy" Chagam <anjaneya.chagam(a)intel.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Morgan Jang <Morgan_Jang(a)wiwynn.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Anjaneya "Reddy" Chagam <anjaneya.chagam(a)intel.com> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Morgan Jang <Morgan_Jang(a)wiwynn.com> Gerrit-Comment-Date: Tue, 02 Feb 2021 18:44:59 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: vc/intel/fsp/fsp2_0/alderlake: Update FSP header file version to 2037
by Tim Wawrzynczak (Code Review) 02 Feb '21

02 Feb '21

Attention is currently required from: Furquan Shaikh, Subrata Banik, Patrick Rudolph. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49382 ) Change subject: vc/intel/fsp/fsp2_0/alderlake: Update FSP header file version to 2037 ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/49382 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I808cf619f43e629c6150726f2aa29e732e05fc33 Gerrit-Change-Number: 49382 Gerrit-PatchSet: 2 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Tue, 02 Feb 2021 18:43:38 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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coreboot-gerrit February 2021