coreboot-gerrit February 2021

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Change in coreboot[master]: tests: Add lib/region_file-test test case
by Patrick Georgi (Code Review) 02 Feb '21

02 Feb '21

Attention is currently required from: Martin Roth, jacz(a)semihalf.com, Julius Werner, Jan Dabros. Patrick Georgi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49669 ) Change subject: tests: Add lib/region_file-test test case ...................................................................... Patch Set 4: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/49669 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic48e52a97b18d55fd983315f25dc972f472cc473 Gerrit-Change-Number: 49669 Gerrit-PatchSet: 4 Gerrit-Owner: jacz(a)semihalf.com Gerrit-Reviewer: Jan Dabros <jsd(a)semihalf.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Fagerburg <pfagerburg(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: jacz(a)semihalf.com Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Jan Dabros <jsd(a)semihalf.com> Gerrit-Comment-Date: Tue, 02 Feb 2021 18:05:22 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: tests: Add lib/region_file-test test case
by Patrick Georgi (Code Review) 02 Feb '21

02 Feb '21

Attention is currently required from: Martin Roth, jacz(a)semihalf.com, Julius Werner, Jan Dabros. Patrick Georgi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49669 ) Change subject: tests: Add lib/region_file-test test case ...................................................................... Patch Set 4: (1 comment) File tests/include/tests/lib/region_file_data.h: https://review.coreboot.org/c/coreboot/+/49669/comment/204f39a9_ab3fed55 PS3, Line 9: void array_dump(void *array, size_t length) > I agree with the statement that it looks slightly out of place, though I think it might be useful wh […] with spinning out I meant moving it outside this file because it can be more generally useful (e.g. for other data files using this format) -- To view, visit https://review.coreboot.org/c/coreboot/+/49669 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic48e52a97b18d55fd983315f25dc972f472cc473 Gerrit-Change-Number: 49669 Gerrit-PatchSet: 4 Gerrit-Owner: jacz(a)semihalf.com Gerrit-Reviewer: Jan Dabros <jsd(a)semihalf.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Fagerburg <pfagerburg(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: jacz(a)semihalf.com Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Jan Dabros <jsd(a)semihalf.com> Gerrit-Comment-Date: Tue, 02 Feb 2021 18:00:42 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Patrick Georgi <pgeorgi(a)google.com> Comment-In-Reply-To: jacz(a)semihalf.com Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/tigerlake: Drops 100ms delay in TBT PCIe root ports _PS0
by Furquan Shaikh (Code Review) 02 Feb '21

02 Feb '21

Attention is currently required from: John Zhao. Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50086 ) Change subject: soc/intel/tigerlake: Drops 100ms delay in TBT PCIe root ports _PS0 ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/50086 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic392f9af6cd739507a80a4ca3fd126088b513304 Gerrit-Change-Number: 50086 Gerrit-PatchSet: 2 Gerrit-Owner: John Zhao <john.zhao(a)intel.com> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Sukumar Ghorai <sukumar.ghorai(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: John Zhao <john.zhao(a)intel.com> Gerrit-Comment-Date: Tue, 02 Feb 2021 17:53:20 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/tigerlake: Drops 100ms delay in TBT PCIe root ports _PS0
by Sukumar Ghorai (Code Review) 02 Feb '21

02 Feb '21

Attention is currently required from: John Zhao. Sukumar Ghorai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50086 ) Change subject: soc/intel/tigerlake: Drops 100ms delay in TBT PCIe root ports _PS0 ...................................................................... Patch Set 2: Code-Review+1 (1 comment) Patchset: PS2: Verified. -- To view, visit https://review.coreboot.org/c/coreboot/+/50086 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic392f9af6cd739507a80a4ca3fd126088b513304 Gerrit-Change-Number: 50086 Gerrit-PatchSet: 2 Gerrit-Owner: John Zhao <john.zhao(a)intel.com> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Sukumar Ghorai <sukumar.ghorai(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: John Zhao <john.zhao(a)intel.com> Gerrit-Comment-Date: Tue, 02 Feb 2021 17:49:51 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/tigerlake: Drops 100ms delay in TBT PCIe root ports _PS0
by Tim Wawrzynczak (Code Review) 02 Feb '21

02 Feb '21

Attention is currently required from: John Zhao. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50086 ) Change subject: soc/intel/tigerlake: Drops 100ms delay in TBT PCIe root ports _PS0 ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/50086 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic392f9af6cd739507a80a4ca3fd126088b513304 Gerrit-Change-Number: 50086 Gerrit-PatchSet: 2 Gerrit-Owner: John Zhao <john.zhao(a)intel.com> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: John Zhao <john.zhao(a)intel.com> Gerrit-Comment-Date: Tue, 02 Feb 2021 17:38:44 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/cannonlake: Configure GPIOs again after FSP-S is done
by Michael Niewöhner (Code Review) 02 Feb '21

02 Feb '21

Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31250 ) Change subject: soc/intel/cannonlake: Configure GPIOs again after FSP-S is done ...................................................................... Patch Set 5: (1 comment) Patchset: PS5: > > I had used this diff: […] I have some insane idea \o/ My first thought was, why not set PadCfgLock, so FSP can't write the pad config anymore, but FSP unlocks it. However, unlocking it generates a "synchronous SMI#". Couldn't we add a SMI handler in coreboot to just set the lock again? :D -- To view, visit https://review.coreboot.org/c/coreboot/+/31250 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7787aa8f185f633627bcedc7f23504bf4a5250b4 Gerrit-Change-Number: 31250 Gerrit-PatchSet: 5 Gerrit-Owner: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Comment-Date: Tue, 02 Feb 2021 17:37:29 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Furquan Shaikh <furquan(a)google.com> Comment-In-Reply-To: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/emulation/qemu: Fix SMP boot
by Arthur Heymans (Code Review) 02 Feb '21

02 Feb '21

Attention is currently required from: Patrick Rudolph. Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50235 ) Change subject: mb/emulation/qemu: Fix SMP boot ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/50235 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib3d7c1a1a7a8633d4d434ccbd46cf92b0074b724 Gerrit-Change-Number: 50235 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Comment-Date: Tue, 02 Feb 2021 17:30:19 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/amd/picasso: Fix copy-paste error in macro definitions
by Angel Pons (Code Review) 02 Feb '21

02 Feb '21

Attention is currently required from: Jason Glenesk, Raul Rangel, Bao Zheng, Marshall Dawson, Felix Held. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50232 ) Change subject: soc/amd/picasso: Fix copy-paste error in macro definitions ...................................................................... Patch Set 2: (1 comment) File src/soc/amd/picasso/include/soc/data_fabric.h: https://review.coreboot.org/c/coreboot/+/50232/comment/f7a72a78_52700649 PS1, Line 68: DF_IND_CFG_ACC_FUN_MASK > this should be DF_IND_CFG_ACC_FUN_SHIFT and not the _MASK Oof, done -- To view, visit https://review.coreboot.org/c/coreboot/+/50232 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I78370e17d2396f77ab820771f93cf15957bcf674 Gerrit-Change-Number: 50232 Gerrit-PatchSet: 2 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Bao Zheng <zheng.bao(a)amd.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Bao Zheng <zheng.bao(a)amd.corp-partner.google.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Tue, 02 Feb 2021 17:27:09 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/emulation/qemu: Fix SMP boot
by Patrick Rudolph (Code Review) 02 Feb '21

02 Feb '21

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/50235 ) Change subject: mb/emulation/qemu: Fix SMP boot ...................................................................... mb/emulation/qemu: Fix SMP boot Fix booting with SMP enabled, when specifying more CPUs than supported by the code. Change-Id: Ib3d7c1a1a7a8633d4d434ccbd46cf92b0074b724 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/cpu/qemu-x86/Kconfig M src/mainboard/emulation/qemu-i440fx/northbridge.c 2 files changed, 8 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/35/50235/1 diff --git a/src/cpu/qemu-x86/Kconfig b/src/cpu/qemu-x86/Kconfig index 641cea8..a22d7f9 100644 --- a/src/cpu/qemu-x86/Kconfig +++ b/src/cpu/qemu-x86/Kconfig @@ -44,8 +44,8 @@ config MAX_CPUS int - default 4 if SMM_ASEG - default 32 + default 32 if SMM_TSEG + default 4 config CPU_QEMU_X86_64 bool "Experimental 64bit support" diff --git a/src/mainboard/emulation/qemu-i440fx/northbridge.c b/src/mainboard/emulation/qemu-i440fx/northbridge.c index f49d47da..80fba1d 100644 --- a/src/mainboard/emulation/qemu-i440fx/northbridge.c +++ b/src/mainboard/emulation/qemu-i440fx/northbridge.c @@ -271,6 +271,12 @@ if (max_cpus < 0) return; + /* + * Do not install more CPUs than supported by coreboot. + * This will cause a buffer overflow where fixed arrays of CONFIG_MAX_CPUS + * are used and might result in a boot failure. + */ + max_cpus = MIN(max_cpus, CONFIG_MAX_CPUS); /* * TODO: This only handles the simple "qemu -smp $nr" case -- To view, visit https://review.coreboot.org/c/coreboot/+/50235 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib3d7c1a1a7a8633d4d434ccbd46cf92b0074b724 Gerrit-Change-Number: 50235 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/tigerlake: Drops 100ms delay in TBT PCIe root ports _PS0
by Duncan Laurie (Code Review) 02 Feb '21

02 Feb '21

Attention is currently required from: John Zhao. Duncan Laurie has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50086 ) Change subject: soc/intel/tigerlake: Drops 100ms delay in TBT PCIe root ports _PS0 ...................................................................... Patch Set 2: Code-Review+2 This change is ready for review. -- To view, visit https://review.coreboot.org/c/coreboot/+/50086 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic392f9af6cd739507a80a4ca3fd126088b513304 Gerrit-Change-Number: 50086 Gerrit-PatchSet: 2 Gerrit-Owner: John Zhao <john.zhao(a)intel.com> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: John Zhao <john.zhao(a)intel.com> Gerrit-Comment-Date: Tue, 02 Feb 2021 17:22:30 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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coreboot-gerrit February 2021