coreboot-gerrit February 2021

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: soc/intel/*: drop UART pad configuration from common code
by Michael Niewöhner (Code Review) 02 Feb '21

02 Feb '21

Attention is currently required from: Lance Zhao, Nico Huber. Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48829 ) Change subject: soc/intel/*: drop UART pad configuration from common code ...................................................................... Patch Set 26: (1 comment) Patchset: PS26: > > And FSP will always program the GPIO pad base on uart selection base on FSP upd setting > > What UPDs are those? I thought we agreed in the past that FSP > shouldn't do any pad configuration? Shouldn't, but it does :/ see current discussion at CB:48340. I'll check if we can do anything for platforms without the new UPD -- To view, visit https://review.coreboot.org/c/coreboot/+/48829 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id03719eb8bd0414083148471ed05dea62a895126 Gerrit-Change-Number: 48829 Gerrit-PatchSet: 26 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Lance Zhao Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Lance Zhao Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Comment-Date: Tue, 02 Feb 2021 17:15:57 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Lance Zhao Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Comment-In-Reply-To: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/siemens/mc_apl1: do UART pad configuration at board-level
by Michael Niewöhner (Code Review) 02 Feb '21

02 Feb '21

Michael Niewöhner has submitted this change. ( https://review.coreboot.org/c/coreboot/+/49442 ) Change subject: mb/siemens/mc_apl1: do UART pad configuration at board-level ...................................................................... mb/siemens/mc_apl1: do UART pad configuration at board-level UART pad configuration should not be done in common code, because that may cause short circuits, when the user sets a wrong UART index. Thus, add the corresponding pads to the early UART gpio table for the board as a first step. Common UART pad config code then gets dropped in CB:48829. Also switch to `bootblock_mainboard_early_init` to configure the pads in early bootblock before console initialization, to make the console work as early as possible. The board does not do any other gpio configuration in bootblock, so this should not influence behaviour in a negative way (e.g. breaking overrides). Change-Id: Iac8a6e386b708ae5c4dbf0677bfe05f1358bf8fd Signed-off-by: Michael Niewöhner <foss(a)mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49442 Tested-by: siemens-bot Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Mario Scheithauer <mario.scheithauer(a)siemens.com> Reviewed-by: Uwe Poeche <uwe.poeche(a)siemens.com> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/mainboard/siemens/mc_apl1/bootblock.c M src/mainboard/siemens/mc_apl1/variants/baseboard/gpio.c 2 files changed, 4 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified siemens-bot: Verified Mario Scheithauer: Looks good to me, approved Angel Pons: Looks good to me, approved Uwe Poeche: Looks good to me, but someone else must approve diff --git a/src/mainboard/siemens/mc_apl1/bootblock.c b/src/mainboard/siemens/mc_apl1/bootblock.c index 01c8e93..a858f1b 100644 --- a/src/mainboard/siemens/mc_apl1/bootblock.c +++ b/src/mainboard/siemens/mc_apl1/bootblock.c @@ -4,7 +4,7 @@ #include <bootblock_common.h> #include <intelblocks/gpio.h> -void bootblock_mainboard_init(void) +void bootblock_mainboard_early_init(void) { const struct pad_config *pads; size_t num; diff --git a/src/mainboard/siemens/mc_apl1/variants/baseboard/gpio.c b/src/mainboard/siemens/mc_apl1/variants/baseboard/gpio.c index 2edd92e..6a3b859 100644 --- a/src/mainboard/siemens/mc_apl1/variants/baseboard/gpio.c +++ b/src/mainboard/siemens/mc_apl1/variants/baseboard/gpio.c @@ -356,6 +356,9 @@ /* GPIOs needed prior to ramstage. */ static const struct pad_config early_gpio_table[] = { + /* UART */ + PAD_CFG_NF(GPIO_46, NATIVE, DEEP, NF1), /* LPSS_UART2_RXD */ + PAD_CFG_NF_IOSSTATE(GPIO_47, NATIVE, DEEP, NF1, Tx1RxDCRx0), /* LPSS_UART2_TXD */ /* Debug tracing. */ PAD_CFG_GPI(GPIO_0, DN_20K, DEEP), /* TRACE_0_CLK_VNN */ -- To view, visit https://review.coreboot.org/c/coreboot/+/49442 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iac8a6e386b708ae5c4dbf0677bfe05f1358bf8fd Gerrit-Change-Number: 49442 Gerrit-PatchSet: 10 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Uwe Poeche <uwe.poeche(a)siemens.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: siemens-bot Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/intel/common: Add `struct gpio_pad_table` and helpers
by Michael Niewöhner (Code Review) 02 Feb '21

02 Feb '21

Attention is currently required from: Furquan Shaikh, Angel Pons, Subrata Banik, Patrick Rudolph. Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50176 ) Change subject: soc/intel/common: Add `struct gpio_pad_table` and helpers ...................................................................... Patch Set 1: (2 comments) File src/soc/intel/common/block/include/intelblocks/gpio.h: https://review.coreboot.org/c/coreboot/+/50176/comment/42db234e_bd341998 PS1, Line 78: (struct gpio_pad_table) > The cast is there on purpose to allow this usage: […] ack https://review.coreboot.org/c/coreboot/+/50176/comment/781a1922_def13e2a PS1, Line 81: ) > when the cast gets dropped. […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/50176 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If029bbafe186d36a971d91b3b6b9220616e04141 Gerrit-Change-Number: 50176 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Tue, 02 Feb 2021 17:11:00 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Comment-In-Reply-To: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-MessageType: comment

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Change in coreboot[master]: src: Remove unused <bootstate.h>
by Jonathan Zhang (Code Review) 02 Feb '21

02 Feb '21

Attention is currently required from: Anjaneya "Reddy" Chagam, Morgan Jang, Patrick Rudolph, HAOUAS Elyes. Jonathan Zhang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50203 ) Change subject: src: Remove unused <bootstate.h> ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/50203 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0d2ab4144970184f46e1d0e7a2464e94fa38aa63 Gerrit-Change-Number: 50203 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Anjaneya "Reddy" Chagam <anjaneya.chagam(a)intel.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Morgan Jang <Morgan_Jang(a)wiwynn.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Anjaneya "Reddy" Chagam <anjaneya.chagam(a)intel.com> Gerrit-Attention: Morgan Jang <Morgan_Jang(a)wiwynn.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Comment-Date: Tue, 02 Feb 2021 17:06:50 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/guybrush: First pass GPIO configuriation for Guybrush
by Mathew King (Code Review) 02 Feb '21

02 Feb '21

Attention is currently required from: Furquan Shaikh, EricR Lai. Mathew King has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50091 ) Change subject: mb/google/guybrush: First pass GPIO configuriation for Guybrush ...................................................................... Patch Set 5: (8 comments) File src/mainboard/google/guybrush/variants/baseboard/gpio.c: https://review.coreboot.org/c/coreboot/+/50091/comment/eda87de6_ce1394cb PS5, Line 17: PAD_NC(GPIO_3), > GSC_SOC_INT_L I was planning a second pass to fill these in. https://review.coreboot.org/c/coreboot/+/50091/comment/b1587f57_b3469ace PS5, Line 19: PAD_NC(GPIO_4), > SOC_PEN_DETECT_ODL Ack https://review.coreboot.org/c/coreboot/+/50091/comment/a56e4b2b_a7054324 PS5, Line 21: PAD_NC(GPIO_5), > EN_PP5000_EN Ack https://review.coreboot.org/c/coreboot/+/50091/comment/c1db3322_8c799074 PS5, Line 23: PAD_NC(GPIO_6), > EN_PP3300_WLAN Ack https://review.coreboot.org/c/coreboot/+/50091/comment/a385334f_86ce8ab8 PS5, Line 25: PAD_NC(GPIO_7), > EN_PP3300_TCHPAD Ack https://review.coreboot.org/c/coreboot/+/50091/comment/b79849a8_7566594e PS5, Line 27: PAD_NC(GPIO_8), > EN_PWR_WWAN_X Ack https://review.coreboot.org/c/coreboot/+/50091/comment/3d399b73_3ba015ac PS5, Line 29: PAD_NC(GPIO_9), > SOC_TCHPAD_INT_L Ack https://review.coreboot.org/c/coreboot/+/50091/comment/8cfc0fd5_cefa4b73 PS5, Line 33: PAD_NC(GPIO_11), > SOC_FP_RST_L Ack -- To view, visit https://review.coreboot.org/c/coreboot/+/50091 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia8211dbc3de09a61f264a0e5d44d1eac703b83c9 Gerrit-Change-Number: 50091 Gerrit-PatchSet: 5 Gerrit-Owner: Mathew King <mathewk(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-CC: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Comment-Date: Tue, 02 Feb 2021 17:04:34 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/guybrush: stubs to configure GPIOs
by Mathew King (Code Review) 02 Feb '21

02 Feb '21

Attention is currently required from: Martin Roth, Angel Pons, EricR Lai. Mathew King has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49954 ) Change subject: mb/google/guybrush: stubs to configure GPIOs ...................................................................... Patch Set 10: (1 comment) File src/mainboard/google/guybrush/variants/baseboard/include/baseboard/variants.h: https://review.coreboot.org/c/coreboot/+/49954/comment/c2ee4557_088828c3 PS9, Line 3: #ifndef __BASEBOARD_COMMON_VARIANTS_H__ > Why add common here? Nice catch, from earlier edit. -- To view, visit https://review.coreboot.org/c/coreboot/+/49954 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5afd2df396ba41f7d25fa7ff6879b7c1f82f438c Gerrit-Change-Number: 49954 Gerrit-PatchSet: 10 Gerrit-Owner: Mathew King <mathewk(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Comment-Date: Tue, 02 Feb 2021 17:03:06 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/tigerlake: Add CrashLog implementation for intel TGL
by Tim Wawrzynczak (Code Review) 02 Feb '21

02 Feb '21

Attention is currently required from: Francois Toguo Fotso, Martin Roth, Paul Menzel, Duncan Laurie, Tim Wawrzynczak, Patrick Rudolph. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49943 ) Change subject: soc/intel/tigerlake: Add CrashLog implementation for intel TGL ...................................................................... Patch Set 10: (4 comments) Patchset: PS7: > Tim, […] Gotcha, let's try and share as much as possible; if it makes sense to share most of it between TGL & ADL, then we can move it to src/soc/common/intel/block/crashlog for example File src/soc/intel/tigerlake/Kconfig: https://review.coreboot.org/c/coreboot/+/49943/comment/14ae18d7_7599d8f8 PS6, Line 266: config ACPI_BERT : bool "Enables ACPI BERT" : default y : help : Enables ACPI Boot Error Record Table generation. : : config SOC_INTEL_CRASHLOG : def_bool n : help : Enables CrashLog. : > Your rational is correct, but for practical purpose I think it is better to keep them separate for t […] You are correct; I have a suggestion then, how about moving the `acpi_soc_fill_bert` and `acpi_is_boot_error_src_present` function to a new file, e.g. soc/intel/tigerlake/acpi_bert.c, and then the Makefile can reflect this too: ``` +ramstage-$(CONFIG_SOC_INTEL_CRASHLOG) += acpi_bert.c ``` and then you can `select` ACPI_BERT in the Kconfig: ``` config SOC_INTEL_CRASHLOG def_bool n select ACPI_BERT help Enables CrashLog. ``` and Volteer only needs to select SOC_INTEL_CRASHLOG, and then ACPI_BERT comes for free File src/soc/intel/tigerlake/Makefile.inc: https://review.coreboot.org/c/coreboot/+/49943/comment/143e59ac_51a355f0 PS10, Line 49: y $(CONFIG_SOC_INTEL_CRASHLOG) File src/soc/intel/tigerlake/acpi.c: https://review.coreboot.org/c/coreboot/+/49943/comment/9510dac2_69dcdcd9 PS6, Line 367: if (crashlog_get_total_data_size() > bert_storage_remaining()) { : printk(BIOS_ERR, "Error: Crashlog entry would exceed " : "available region\n"); : return; : } > It is not expected, but I think the check is warranted. […] Understood. -- To view, visit https://review.coreboot.org/c/coreboot/+/49943 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie3763cebcd1178709cc8597710bf062a30901809 Gerrit-Change-Number: 49943 Gerrit-PatchSet: 10 Gerrit-Owner: Francois Toguo Fotso <francois.toguo.fotso(a)intel.com> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-CC: Raj Astekar <raj.astekar(a)intel.com> Gerrit-Attention: Francois Toguo Fotso <francois.toguo.fotso(a)intel.com> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Attention: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)google.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Tue, 02 Feb 2021 17:02:53 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Francois Toguo Fotso <francois.toguo.fotso(a)intel.com> Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: hatch: Modify genesis PcieClkSrc settings
by Joe Tessler (Code Review) 02 Feb '21

02 Feb '21

Attention is currently required from: Furquan Shaikh, Neill Corlett. Joe Tessler has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50101 ) Change subject: hatch: Modify genesis PcieClkSrc settings ...................................................................... Patch Set 2: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/50101/comment/74e07874_596e7347 PS2, Line 9: to work around issue with Longsys SSD > After chatting again with them, I confirmed this new SSD module is a raw PCIe drive (not SATA). […] Considering this resolved in case it blocks autosubmit. 😊 -- To view, visit https://review.coreboot.org/c/coreboot/+/50101 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I30c2179be9b9ddd50168a7f35be800e969800e10 Gerrit-Change-Number: 50101 Gerrit-PatchSet: 2 Gerrit-Owner: Neill Corlett <corlett(a)google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Joe Tessler <jrt(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Matthew Ziegelbaum <ziegs(a)google.com> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Neill Corlett <corlett(a)google.com> Gerrit-Comment-Date: Tue, 02 Feb 2021 17:01:56 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Furquan Shaikh <furquan(a)google.com> Comment-In-Reply-To: Joe Tessler <jrt(a)google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/amd: rename sb_init_acpi_ports to fch_init_acpi_ports
by Raul Rangel (Code Review) 02 Feb '21

02 Feb '21

Attention is currently required from: Jason Glenesk, Marshall Dawson, Felix Held. Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50209 ) Change subject: soc/amd: rename sb_init_acpi_ports to fch_init_acpi_ports ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/50209 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I19126da09f034f51b134f8d6ae2006f57fac1b0d Gerrit-Change-Number: 50209 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Tue, 02 Feb 2021 16:57:23 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/amd/cezanne: remove UART2/3 AOAC device offsets
by Raul Rangel (Code Review) 02 Feb '21

02 Feb '21

Attention is currently required from: Jason Glenesk, Marshall Dawson, Felix Held. Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50230 ) Change subject: soc/amd/cezanne: remove UART2/3 AOAC device offsets ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/50230 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I67755bd34df3a835cc39929bdc24f711d158b3a3 Gerrit-Change-Number: 50230 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Tue, 02 Feb 2021 16:55:14 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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coreboot-gerrit February 2021