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Change subject: soc/amd/picasso: Fix copy-paste error in macro definitions
......................................................................
Patch Set 1:
(1 comment)
File src/soc/amd/picasso/include/soc/data_fabric.h:
https://review.coreboot.org/c/coreboot/+/50232/comment/69c8321b_c651e4c0
PS1, Line 68: DF_IND_CFG_ACC_FUN_MASK
this should be DF_IND_CFG_ACC_FUN_SHIFT and not the _MASK
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Change subject: acpi: Add support for reporting CrashLog in BERT table
......................................................................
Patch Set 9: Code-Review+2
(3 comments)
Patchset:
PS9:
Thanks Francois!
File src/arch/x86/acpi_bert_storage.c:
https://review.coreboot.org/c/coreboot/+/49799/comment/cf4d30df_028b7cb5
PS7, Line 229: 2
> Is this defined somewhere already? If not, would you mind adding a `#define` for this?
Ack
https://review.coreboot.org/c/coreboot/+/49799/comment/1ee42f5c_f6b30fe1
PS7, Line 229: recort
> record
Ack
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Change subject: soc/amd/picasso/pcie_gpe: use PICM instead of PMOD in APCI code
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Patch Set 1: Code-Review+2
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Change subject: mb/google/volteer/var/voema: Enable EEPROM for OV2740
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Patch Set 1: Code-Review+2
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Change subject: soc/amd/common: Refactor single GPIO programming
......................................................................
Patch Set 14:
(1 comment)
File src/soc/amd/common/block/gpio_banks/gpio.c:
https://review.coreboot.org/c/coreboot/+/42691/comment/a92fa73b_e885bc40
PS14, Line 184: g
Can we name it gpio? I only like single character variables names for loop variables.
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Change subject: src: Remove unused <cbfs.h>
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Patch Set 7: Code-Review+2
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Change subject: doc/soc/intel/crashlog: add CrashLog Spec
......................................................................
Patch Set 1: Code-Review+1
(1 comment)
Patchset:
PS1:
Patrick, is uploading a PDF for Crashlog documentation here OK? Does it need to be in markdown?
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Change subject: soc/intel/*: drop UART pad configuration from common code
......................................................................
Patch Set 26:
(1 comment)
Patchset:
PS26:
> The advantage of current implementation is people porting coreboot to different hardware not need to care about the detail mux setting just as simple as which uart port is using is good enough.
That is true, but the disadvantage is that one risks short-circuits
if the setting is wrong. And if you look at the history of related
Kconfig files, you'll see that it was more often configured wrong
than right in the past. Oh, and the per-SoC tables were sometimes
wrong too.
Please always consider that not everybody is working for a major
vendor. If I break a board because of such misconfiguration, for
instance, I have to wait weeks, for a new one to arrive.
There are other ways to make it more simple for newer ports. IMO,
we should keep pad configuration in C code at the mainboard level
to not lose track of it again. But it doesn't have to be per main-
board pad tables. For instance, we could have per-topic/group pad
tables at the SoC level. If you have any good idea how to design
such code, please go ahead. I just needs to be less error-prone
than the old Kconfig / SoC code mess.
> And FSP will always program the GPIO pad base on uart selection base on FSP upd setting
What UPDs are those? I thought we agreed in the past that FSP
shouldn't do any pad configuration?
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