coreboot-gerrit February 2021

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Change in coreboot[master]: nb/intel/x/bootblock.c Revert include <arch/pci_io_cfg.h>
by Angel Pons (Code Review) 02 Feb '21

02 Feb '21

Attention is currently required from: Damien Zammit, Kyösti Mälkki, Patrick Rudolph. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50229 ) Change subject: nb/intel/x/bootblock.c Revert include <arch/pci_io_cfg.h> ...................................................................... Patch Set 2: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/50229/comment/1697aad9_1ecaa1a8 PS2, Line 20: to be an exception to this. Is this documented anywhere? -- To view, visit https://review.coreboot.org/c/coreboot/+/50229 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I562bf2cfd8c165338577a95c5c644cf5bea3a5c1 Gerrit-Change-Number: 50229 Gerrit-PatchSet: 2 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Damien Zammit Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Damien Zammit Gerrit-Attention: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Tue, 02 Feb 2021 15:15:52 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/amd/cezanne: remove UART2/3 AOAC device offsets
by Felix Held (Code Review) 02 Feb '21

02 Feb '21

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/50230 ) Change subject: soc/amd/cezanne: remove UART2/3 AOAC device offsets ...................................................................... soc/amd/cezanne: remove UART2/3 AOAC device offsets UART2 and UART3 don't exist on Cezanne which now has been verified, so remove the corresponding AOAC offsets. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I67755bd34df3a835cc39929bdc24f711d158b3a3 --- M src/soc/amd/cezanne/include/soc/southbridge.h 1 file changed, 0 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/30/50230/1 diff --git a/src/soc/amd/cezanne/include/soc/southbridge.h b/src/soc/amd/cezanne/include/soc/southbridge.h index 6949fa5..a38d706 100644 --- a/src/soc/amd/cezanne/include/soc/southbridge.h +++ b/src/soc/amd/cezanne/include/soc/southbridge.h @@ -22,9 +22,7 @@ #define FCH_AOAC_DEV_I2C5 10 #define FCH_AOAC_DEV_UART0 11 #define FCH_AOAC_DEV_UART1 12 -#define FCH_AOAC_DEV_UART2 16 #define FCH_AOAC_DEV_AMBA 17 -#define FCH_AOAC_DEV_UART3 26 #define FCH_AOAC_DEV_ESPI 27 /* IO 0xf0 NCP Error */ -- To view, visit https://review.coreboot.org/c/coreboot/+/50230 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I67755bd34df3a835cc39929bdc24f711d158b3a3 Gerrit-Change-Number: 50230 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

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Change in coreboot[master]: nb/intel/x/bootblock.c Revert include <arch/pci_io_cfg.h>"
by Kyösti Mälkki (Code Review) 02 Feb '21

02 Feb '21

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/50229 ) Change subject: nb/intel/x/bootblock.c Revert include <arch/pci_io_cfg.h>" ...................................................................... nb/intel/x/bootblock.c Revert include <arch/pci_io_cfg.h>" This reverts commits 77d3b655ed nb/intel/ironlake/bootblock.c: include <arch/pci_io_cfg.h> 487c1a24f5 nb/intel/i945/bootblock.c: include <arch/pci_io_cfg.h> 875c21f491 nb/intel/x4x/bootblock.c: include <arch/pci_io_cfg.h> c4d1b47ad9 nb/intel/gm45/bootblock.c: include <arch/pci_io_cfg.h> b96c358751 nb/intel/haswell/bootblock.c: include <arch/pci_io_cfg.h> 9cbf26d18e nb/intel/sandybridge/bootblock.c: include <arch/pci_io_cfg.h> It is intentional to use <device/pci_ops.h> whenever one needs to use PCI config access. The booblock.c files needing I/O config do not need to be an exception to this. Change-Id: I562bf2cfd8c165338577a95c5c644cf5bea3a5c1 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/northbridge/intel/gm45/bootblock.c M src/northbridge/intel/haswell/bootblock.c M src/northbridge/intel/i945/bootblock.c M src/northbridge/intel/ironlake/bootblock.c M src/northbridge/intel/sandybridge/bootblock.c M src/northbridge/intel/x4x/bootblock.c 6 files changed, 14 insertions(+), 18 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/29/50229/1 diff --git a/src/northbridge/intel/gm45/bootblock.c b/src/northbridge/intel/gm45/bootblock.c index e2cabdb..9c45f7e 100644 --- a/src/northbridge/intel/gm45/bootblock.c +++ b/src/northbridge/intel/gm45/bootblock.c @@ -1,8 +1,8 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <arch/bootblock.h> -#include <arch/pci_io_cfg.h> #include <assert.h> +#include <device/pci_ops.h> #include <types.h> #include "gm45.h" @@ -31,7 +31,7 @@ * The PCIEXBAR is assumed to live in the memory mapped IO space under * 4GiB. */ - const uint32_t reg32 = CONFIG_MMCONF_BASE_ADDRESS | encode_pciexbar_length() | 1; + const uint32_t reg = CONFIG_MMCONF_BASE_ADDRESS | encode_pciexbar_length() | 1; pci_io_write_config32(PCI_DEV(0, 0, 0), D0F0_PCIEXBAR_HI, 0); - pci_io_write_config32(PCI_DEV(0, 0, 0), D0F0_PCIEXBAR_LO, reg32); + pci_io_write_config32(PCI_DEV(0, 0, 0), D0F0_PCIEXBAR_LO, reg); } diff --git a/src/northbridge/intel/haswell/bootblock.c b/src/northbridge/intel/haswell/bootblock.c index 0bb8ae2..64e2258 100644 --- a/src/northbridge/intel/haswell/bootblock.c +++ b/src/northbridge/intel/haswell/bootblock.c @@ -1,10 +1,9 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <arch/bootblock.h> -#include <arch/pci_io_cfg.h> #include <assert.h> +#include <device/pci_ops.h> #include <types.h> - #include "haswell.h" static uint32_t encode_pciexbar_length(void) @@ -29,7 +28,7 @@ * * The PCIEXBAR is assumed to live in the memory mapped IO space under 4GiB. */ - const uint32_t reg32 = CONFIG_MMCONF_BASE_ADDRESS | encode_pciexbar_length() | 1; + const uint32_t reg = CONFIG_MMCONF_BASE_ADDRESS | encode_pciexbar_length() | 1; pci_io_write_config32(HOST_BRIDGE, PCIEXBAR + 4, 0); - pci_io_write_config32(HOST_BRIDGE, PCIEXBAR, reg32); + pci_io_write_config32(HOST_BRIDGE, PCIEXBAR, reg); } diff --git a/src/northbridge/intel/i945/bootblock.c b/src/northbridge/intel/i945/bootblock.c index edb9a8d..f4b4628 100644 --- a/src/northbridge/intel/i945/bootblock.c +++ b/src/northbridge/intel/i945/bootblock.c @@ -1,10 +1,9 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <arch/bootblock.h> -#include <arch/pci_io_cfg.h> #include <assert.h> +#include <device/pci_ops.h> #include <types.h> - #include "i945.h" static uint32_t encode_pciexbar_length(void) @@ -28,6 +27,6 @@ * * The PCIEXBAR is assumed to live in the memory mapped IO space under 4GiB. */ - const uint32_t reg32 = CONFIG_MMCONF_BASE_ADDRESS | encode_pciexbar_length() | 1; - pci_io_write_config32(HOST_BRIDGE, PCIEXBAR, reg32); + const uint32_t reg = CONFIG_MMCONF_BASE_ADDRESS | encode_pciexbar_length() | 1; + pci_io_write_config32(HOST_BRIDGE, PCIEXBAR, reg); } diff --git a/src/northbridge/intel/ironlake/bootblock.c b/src/northbridge/intel/ironlake/bootblock.c index 02b63a6..4b174cb 100644 --- a/src/northbridge/intel/ironlake/bootblock.c +++ b/src/northbridge/intel/ironlake/bootblock.c @@ -1,10 +1,9 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <arch/bootblock.h> -#include <arch/pci_io_cfg.h> #include <assert.h> +#include <device/pci_ops.h> #include <types.h> - #include "ironlake.h" static uint32_t encode_pciexbar_length(void) diff --git a/src/northbridge/intel/sandybridge/bootblock.c b/src/northbridge/intel/sandybridge/bootblock.c index 92f9aee..529f4f8 100644 --- a/src/northbridge/intel/sandybridge/bootblock.c +++ b/src/northbridge/intel/sandybridge/bootblock.c @@ -1,10 +1,9 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <arch/bootblock.h> -#include <arch/pci_io_cfg.h> #include <assert.h> +#include <device/pci_ops.h> #include <types.h> - #include "sandybridge.h" static uint32_t encode_pciexbar_length(void) @@ -29,7 +28,7 @@ * * The PCIEXBAR is assumed to live in the memory mapped IO space under 4GiB. */ - const uint32_t reg32 = CONFIG_MMCONF_BASE_ADDRESS | encode_pciexbar_length() | 1; + const uint32_t reg = CONFIG_MMCONF_BASE_ADDRESS | encode_pciexbar_length() | 1; pci_io_write_config32(HOST_BRIDGE, PCIEXBAR + 4, 0); - pci_io_write_config32(HOST_BRIDGE, PCIEXBAR, reg32); + pci_io_write_config32(HOST_BRIDGE, PCIEXBAR, reg); } diff --git a/src/northbridge/intel/x4x/bootblock.c b/src/northbridge/intel/x4x/bootblock.c index aedcdd9..f15d181 100644 --- a/src/northbridge/intel/x4x/bootblock.c +++ b/src/northbridge/intel/x4x/bootblock.c @@ -2,8 +2,8 @@ #include <arch/bootblock.h> #include <arch/mmio.h> -#include <arch/pci_io_cfg.h> #include <assert.h> +#include <device/pci_ops.h> #include <types.h> #include "x4x.h" -- To view, visit https://review.coreboot.org/c/coreboot/+/50229 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I562bf2cfd8c165338577a95c5c644cf5bea3a5c1 Gerrit-Change-Number: 50229 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/amd/picasso: clean up and re-sort UPD table
by EricR Lai (Code Review) 02 Feb '21

02 Feb '21

Attention is currently required from: Frank Wu, Jason Glenesk, Raul Rangel, Martin Roth, Marshall Dawson, Chris Wang, chris wang, Felix Held. EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50212 ) Change subject: soc/amd/picasso: clean up and re-sort UPD table ...................................................................... Patch Set 3: Code-Review+1 (1 comment) File src/mainboard/google/zork/variants/vilboz/overridetree.cb: https://review.coreboot.org/c/coreboot/+/50212/comment/6ebdab9a_3695038f PS3, Line 34: .margin_deemph = 0x00CC, > is it intended that some of the values get changed here? also in coreboot typically the lower case h […] oh, you are right. Didn't notice this, should be lower case. -- To view, visit https://review.coreboot.org/c/coreboot/+/50212 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I655af08e2f86398d088e30d330f49e71cf7e1275 Gerrit-Change-Number: 50212 Gerrit-PatchSet: 3 Gerrit-Owner: chris wang <Chris.Wang(a)amd.com> Gerrit-Reviewer: Chris Wang <chris.wang(a)amd.corp-partner.google.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Frank Wu <frank_wu(a)compal.corp-partner.google.com> Gerrit-CC: John Su <john_su(a)compal.corp-partner.google.com> Gerrit-Attention: Frank Wu <frank_wu(a)compal.corp-partner.google.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Chris Wang <chris.wang(a)amd.corp-partner.google.com> Gerrit-Attention: chris wang <Chris.Wang(a)amd.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Tue, 02 Feb 2021 15:13:34 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/amd/picasso: clean up and re-sort UPD table
by Felix Held (Code Review) 02 Feb '21

02 Feb '21

Attention is currently required from: Frank Wu, Jason Glenesk, Raul Rangel, Martin Roth, Marshall Dawson, Chris Wang, chris wang, EricR Lai. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50212 ) Change subject: soc/amd/picasso: clean up and re-sort UPD table ...................................................................... Patch Set 3: Code-Review+1 (1 comment) File src/mainboard/google/zork/variants/vilboz/overridetree.cb: https://review.coreboot.org/c/coreboot/+/50212/comment/68e2b12c_572a889d PS3, Line 34: .margin_deemph = 0x00CC, is it intended that some of the values get changed here? also in coreboot typically the lower case hex chars are used -- To view, visit https://review.coreboot.org/c/coreboot/+/50212 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I655af08e2f86398d088e30d330f49e71cf7e1275 Gerrit-Change-Number: 50212 Gerrit-PatchSet: 3 Gerrit-Owner: chris wang <Chris.Wang(a)amd.com> Gerrit-Reviewer: Chris Wang <chris.wang(a)amd.corp-partner.google.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Frank Wu <frank_wu(a)compal.corp-partner.google.com> Gerrit-CC: John Su <john_su(a)compal.corp-partner.google.com> Gerrit-Attention: Frank Wu <frank_wu(a)compal.corp-partner.google.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Chris Wang <chris.wang(a)amd.corp-partner.google.com> Gerrit-Attention: chris wang <Chris.Wang(a)amd.com> Gerrit-Attention: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Comment-Date: Tue, 02 Feb 2021 15:03:59 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: nb/intel/ironlake/bootblock.c: include <arch/pci_io_cfg.h>
by Kyösti Mälkki (Code Review) 02 Feb '21

02 Feb '21

Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49538 ) Change subject: nb/intel/ironlake/bootblock.c: include <arch/pci_io_cfg.h> ...................................................................... Patch Set 4: (1 comment) Patchset: PS4: Well.. I think I requested Elyes twice to start a document what includes we are intentionally chain-loading and <arch/pci_io_cfg.h> would have been on my list. -- To view, visit https://review.coreboot.org/c/coreboot/+/49538 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ide960d7957e8a95961ec3722ad7478926a84c544 Gerrit-Change-Number: 49538 Gerrit-PatchSet: 4 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-CC: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Comment-Date: Tue, 02 Feb 2021 15:03:07 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/volteer/variant/copano: support regular/numpad touchpad
by Zhuohao Lee (Code Review) 02 Feb '21

02 Feb '21

Attention is currently required from: Nick Vaccaro, Zhuohao Lee. Zhuohao Lee has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50129 ) Change subject: mb/google/volteer/variant/copano: support regular/numpad touchpad ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: > I was hoping one of the other reviewers will +2 this given that they are more familiar with the devi […] Thanks Furquan and Marco for +2. Please let me know if you still have concern about this patch. -- To view, visit https://review.coreboot.org/c/coreboot/+/50129 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic5d61f19fd385600cfdcdd045dab1e61b06e4663 Gerrit-Change-Number: 50129 Gerrit-PatchSet: 1 Gerrit-Owner: Zhuohao Lee <zhuohao(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Marco Chen <marcochen(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Attention: Zhuohao Lee <zhuohao(a)chromium.org> Gerrit-Comment-Date: Tue, 02 Feb 2021 14:59:56 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Furquan Shaikh <furquan(a)google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: drivers/intel/fsp2_0: Add support for MP PPI services2 APIs
by Aamir Bohra (Code Review) 02 Feb '21

02 Feb '21

Attention is currently required from: Furquan Shaikh, Martin Roth, Meera Ravindranath, Aamir Bohra, Tim Wawrzynczak, Andrey Petrov, Patrick Rudolph. Hello build bot (Jenkins), Furquan Shaikh, Patrick Georgi, Martin Roth, Subrata Banik, Meera Ravindranath, Tim Wawrzynczak, Andrey Petrov, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/49474 to look at the new patch set (#6). Change subject: drivers/intel/fsp2_0: Add support for MP PPI services2 APIs ...................................................................... drivers/intel/fsp2_0: Add support for MP PPI services2 APIs Add support for MP services 2 PPIs, which is slight modification over MP services 1 PPIs. A new API StartupAllCPUs have been added to allow running a task on BSP and all APs. Also the EFI_PEI_SERVICES parameter has been removed from all MP PPI APIs. Change-Id: Id74baf17fb90147d229c78be90268fdc3ec1badc Signed-off-by: Aamir Bohra <aamir.bohra(a)intel.com> --- M src/drivers/intel/fsp2_0/Kconfig M src/drivers/intel/fsp2_0/include/fsp/ppi/mp_service_ppi.h M src/drivers/intel/fsp2_0/ppi/Kconfig M src/drivers/intel/fsp2_0/ppi/Makefile.inc A src/drivers/intel/fsp2_0/ppi/mp_service1.c A src/drivers/intel/fsp2_0/ppi/mp_service2.c M src/drivers/intel/fsp2_0/ppi/mp_service_ppi.c M src/include/efi/efi_datatype.h M src/soc/intel/common/block/cpu/Kconfig A src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/Ppi/MpServices2.h A src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/Ppi/MpServices2.h 11 files changed, 826 insertions(+), 55 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/49474/6 -- To view, visit https://review.coreboot.org/c/coreboot/+/49474 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id74baf17fb90147d229c78be90268fdc3ec1badc Gerrit-Change-Number: 49474 Gerrit-PatchSet: 6 Gerrit-Owner: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-CC: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Attention: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)google.com> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/amd: rename sb_init_acpi_ports to fch_init_acpi_ports
by Felix Held (Code Review) 02 Feb '21

02 Feb '21

Attention is currently required from: Jason Glenesk, Raul Rangel, Marshall Dawson. Hello build bot (Jenkins), Jason Glenesk, Raul Rangel, Marshall Dawson, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/50209 to look at the new patch set (#2). Change subject: soc/amd: rename sb_init_acpi_ports to fch_init_acpi_ports ...................................................................... soc/amd: rename sb_init_acpi_ports to fch_init_acpi_ports There's no dedicated south bridge any more and now we have integrated FCHs in the SoCs. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I19126da09f034f51b134f8d6ae2006f57fac1b0d --- M src/soc/amd/picasso/fch.c M src/soc/amd/stoneyridge/southbridge.c 2 files changed, 4 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/09/50209/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/50209 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I19126da09f034f51b134f8d6ae2006f57fac1b0d Gerrit-Change-Number: 50209 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/baytrail,braswell: Drop TOLM from GNVS
by Kyösti Mälkki (Code Review) 02 Feb '21

02 Feb '21

Kyösti Mälkki has submitted this change. ( https://review.coreboot.org/c/coreboot/+/50121 ) Change subject: soc/intel/baytrail,braswell: Drop TOLM from GNVS ...................................................................... soc/intel/baytrail,braswell: Drop TOLM from GNVS It's a static value that is neither referenced from SMI handler nor needs to be updated on S3 resume path. Change-Id: Ife6611a11e5627d39d59e0e93af9aa2d87885601 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50121 Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/intel/baytrail/acpi.c M src/soc/intel/baytrail/acpi/globalnvs.asl M src/soc/intel/baytrail/acpi/southcluster.asl M src/soc/intel/baytrail/northcluster.c M src/soc/intel/braswell/acpi.c M src/soc/intel/braswell/acpi/globalnvs.asl M src/soc/intel/braswell/acpi/southcluster.asl M src/soc/intel/braswell/northcluster.c 8 files changed, 30 insertions(+), 12 deletions(-) Approvals: build bot (Jenkins): Verified Angel Pons: Looks good to me, approved diff --git a/src/soc/intel/baytrail/acpi.c b/src/soc/intel/baytrail/acpi.c index d379beb..5433fdc 100644 --- a/src/soc/intel/baytrail/acpi.c +++ b/src/soc/intel/baytrail/acpi.c @@ -60,9 +60,6 @@ { /* Set unknown wake source */ gnvs->pm1i = -1; - - /* Top of Low Memory (start of resource allocation) */ - gnvs->tolm = nc_read_top_of_low_memory(); } int acpi_sci_irq(void) diff --git a/src/soc/intel/baytrail/acpi/globalnvs.asl b/src/soc/intel/baytrail/acpi/globalnvs.asl index 3d2b3dc..cffb224 100644 --- a/src/soc/intel/baytrail/acpi/globalnvs.asl +++ b/src/soc/intel/baytrail/acpi/globalnvs.asl @@ -40,7 +40,7 @@ /* Base addresses */ Offset (0x30), , 32, /* 0x30 - CBMEM TOC */ - TOLM, 32, /* 0x34 - Top of Low Memory */ + , 32, /* 0x34 - Top of Low Memory */ CBMC, 32, /* 0x38 - coreboot mem console pointer */ } diff --git a/src/soc/intel/baytrail/acpi/southcluster.asl b/src/soc/intel/baytrail/acpi/southcluster.asl index 75f2486..ab27344 100644 --- a/src/soc/intel/baytrail/acpi/southcluster.asl +++ b/src/soc/intel/baytrail/acpi/southcluster.asl @@ -30,6 +30,8 @@ } } +External (\TOLM, IntObj) + Name(_HID,EISAID("PNP0A08")) /* PCIe */ Name(_CID,EISAID("PNP0A03")) /* PCI */ diff --git a/src/soc/intel/baytrail/northcluster.c b/src/soc/intel/baytrail/northcluster.c index d221009..310ce4d 100644 --- a/src/soc/intel/baytrail/northcluster.c +++ b/src/soc/intel/baytrail/northcluster.c @@ -1,15 +1,16 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include <acpi/acpi.h> +#include <acpi/acpigen.h> #include <device/device.h> #include <device/pci.h> #include <device/pci_ids.h> -#include <vendorcode/google/chromeos/chromeos.h> -#include <acpi/acpi.h> #include <stdint.h> #include <soc/iomap.h> #include <soc/iosf.h> #include <soc/pci_devs.h> #include <soc/ramstage.h> +#include <vendorcode/google/chromeos/chromeos.h> /* * Host Memory Map: @@ -123,9 +124,18 @@ chromeos_reserve_ram_oops(dev, index++); } +static void nc_generate_ssdt(const struct device *dev) +{ + generate_cpu_entries(dev); + + acpigen_write_scope("\\"); + acpigen_write_name_dword("TOLM", nc_read_top_of_low_memory()); + acpigen_pop_len(); +} + static struct device_operations nc_ops = { .read_resources = nc_read_resources, - .acpi_fill_ssdt = generate_cpu_entries, + .acpi_fill_ssdt = nc_generate_ssdt, .ops_pci = &soc_pci_ops, }; diff --git a/src/soc/intel/braswell/acpi.c b/src/soc/intel/braswell/acpi.c index 70fd993..dbb8835 100644 --- a/src/soc/intel/braswell/acpi.c +++ b/src/soc/intel/braswell/acpi.c @@ -64,9 +64,6 @@ /* Set unknown wake source */ gnvs->pm1i = -1; - /* Top of Low Memory (start of resource allocation) */ - gnvs->tolm = nc_read_top_of_low_memory(); - /* Fill in the Wi-Fi Region ID */ if (CONFIG(HAVE_REGULATORY_DOMAIN)) gnvs->cid1 = wifi_regulatory_domain(); diff --git a/src/soc/intel/braswell/acpi/globalnvs.asl b/src/soc/intel/braswell/acpi/globalnvs.asl index 22af61b..9a43671 100644 --- a/src/soc/intel/braswell/acpi/globalnvs.asl +++ b/src/soc/intel/braswell/acpi/globalnvs.asl @@ -42,7 +42,7 @@ /* Base addresses */ Offset (0x30), , 32, /* 0x30 - CBMEM TOC */ - TOLM, 32, /* 0x34 - Top of Low Memory */ + , 32, /* 0x34 - Top of Low Memory */ CBMC, 32, /* 0x38 - coreboot mem console pointer */ } diff --git a/src/soc/intel/braswell/acpi/southcluster.asl b/src/soc/intel/braswell/acpi/southcluster.asl index 8fa95ef..64bff12 100644 --- a/src/soc/intel/braswell/acpi/southcluster.asl +++ b/src/soc/intel/braswell/acpi/southcluster.asl @@ -30,6 +30,8 @@ } } +External (\TOLM, IntObj) + Name(_HID,EISAID("PNP0A08")) /* PCIe */ Name(_CID,EISAID("PNP0A03")) /* PCI */ diff --git a/src/soc/intel/braswell/northcluster.c b/src/soc/intel/braswell/northcluster.c index 0b47e2f..0ef58b2 100644 --- a/src/soc/intel/braswell/northcluster.c +++ b/src/soc/intel/braswell/northcluster.c @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <acpi/acpi.h> +#include <acpi/acpigen.h> #include <cbmem.h> #include <cpu/x86/smm.h> #include <device/device.h> @@ -149,9 +150,18 @@ chromeos_reserve_ram_oops(dev, index++); } +static void nc_generate_ssdt(const struct device *dev) +{ + generate_cpu_entries(dev); + + acpigen_write_scope("\\"); + acpigen_write_name_dword("TOLM", nc_read_top_of_low_memory()); + acpigen_pop_len(); +} + static struct device_operations nc_ops = { - .acpi_fill_ssdt = generate_cpu_entries, .read_resources = nc_read_resources, + .acpi_fill_ssdt = nc_generate_ssdt, .ops_pci = &soc_pci_ops, }; -- To view, visit https://review.coreboot.org/c/coreboot/+/50121 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ife6611a11e5627d39d59e0e93af9aa2d87885601 Gerrit-Change-Number: 50121 Gerrit-PatchSet: 5 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: merged

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coreboot-gerrit February 2021