coreboot-gerrit February 2021

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: soc/intel/baytrail,braswell: Sync PCI memory region in ASL
by Kyösti Mälkki (Code Review) 02 Feb '21

02 Feb '21

Kyösti Mälkki has submitted this change. ( https://review.coreboot.org/c/coreboot/+/50192 ) Change subject: soc/intel/baytrail,braswell: Sync PCI memory region in ASL ...................................................................... soc/intel/baytrail,braswell: Sync PCI memory region in ASL Baytrail had (only) occurence of DwordMemory vs DWordMemory. Braswell one had bogus comments about the PCI memory range. The actual region details are dynamically filled in _CRS. Change-Id: I8d1bf45c6e5520c0b7643602843c665bfb81f9da Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50192 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/soc/intel/baytrail/acpi/southcluster.asl M src/soc/intel/braswell/acpi/southcluster.asl 2 files changed, 4 insertions(+), 4 deletions(-) Approvals: build bot (Jenkins): Verified Angel Pons: Looks good to me, approved diff --git a/src/soc/intel/baytrail/acpi/southcluster.asl b/src/soc/intel/baytrail/acpi/southcluster.asl index 8c715d3..75f2486 100644 --- a/src/soc/intel/baytrail/acpi/southcluster.asl +++ b/src/soc/intel/baytrail/acpi/southcluster.asl @@ -143,7 +143,7 @@ 0x00000000,,, LMEM) /* PCI Memory Region (Top of memory-CONFIG_MMCONF_BASE_ADDRESS) */ - DwordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,,, PMEM) diff --git a/src/soc/intel/braswell/acpi/southcluster.asl b/src/soc/intel/braswell/acpi/southcluster.asl index d74647e..8fa95ef 100644 --- a/src/soc/intel/braswell/acpi/southcluster.asl +++ b/src/soc/intel/braswell/acpi/southcluster.asl @@ -144,11 +144,11 @@ 0x00000000, 0x20000000, 0x201FFFFF, 0x00000000, 0x00200000,,, LMEM) - /* PCI Memory Region (Top of memory-0xfeafffff) */ + /* PCI Memory Region (Top of memory-CONFIG_MMCONF_BASE_ADDRESS) */ DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite, - 0x00000000, 0xfea00000, 0xfeafffff, 0x00000000, - 0x00100000,,, PMEM) + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000,,, PMEM) /* TPM Area (0xfed40000-0xfed44fff) */ DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, -- To view, visit https://review.coreboot.org/c/coreboot/+/50192 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8d1bf45c6e5520c0b7643602843c665bfb81f9da Gerrit-Change-Number: 50192 Gerrit-PatchSet: 2 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: merged

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Change in coreboot[master]: drivers/intel/fsp2_0: Integrate FirmwareVersionInfo.h
by Nico Huber (Code Review) 02 Feb '21

02 Feb '21

Attention is currently required from: Maulik V Vaghela, Paul Menzel, Subrata Banik, Ronak Kanabar, Aamir Bohra. Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45905 ) Change subject: drivers/intel/fsp2_0: Integrate FirmwareVersionInfo.h ...................................................................... Patch Set 12: (1 comment) File src/drivers/intel/fsp2_0/Kconfig.debug_blob: https://review.coreboot.org/c/coreboot/+/45905/comment/a39793da_80597c31 PS5, Line 46: using new header 'FirmwareVersionInfo.h'. > hi, i am confused here about the automatic detection how you are proposing here. can you please help me understand method you are suggesting You can let Make check for the presence of a header file and then add compilation options for the .c file. The latter can be tricky because one has to construct the object file's path. I guess something like this could work: ifneq($(wildcard $(CONFIG_FSP_HEADER_PATH)/FirmwareVersionInfoHob.h),) ramstage-y += version_info.c $(call src-to-obj,$(dir)/version_info.c): CPPFLAGS_common += -include $(CONFIG_FSP_HEADER_PATH)/FirmwareVersionInfoHob.h -DFSP_VERSION_INFO_1 else ifneq($(wildcard $(CONFIG_FSP_HEADER_PATH)/FirmwareVersionInfo.h),) ramstage-y += version_info.c $(call src-to-obj,$(dir)/version_info.c): CPPFLAGS_common += -include $(CONFIG_FSP_HEADER_PATH)/FirmwareVersionInfo.h -DFSP_VERSION_INFO_2 endif -- To view, visit https://review.coreboot.org/c/coreboot/+/45905 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I50f7cae9ed4fac60f91d86bdd3e884956627e4b5 Gerrit-Change-Number: 45905 Gerrit-PatchSet: 12 Gerrit-Owner: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Patrick Rudolph Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Attention: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Comment-Date: Tue, 02 Feb 2021 14:13:38 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Comment-In-Reply-To: Paul Menzel <paulepanter(a)users.sourceforge.net> Comment-In-Reply-To: Subrata Banik <subrata.banik(a)intel.com> Comment-In-Reply-To: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/zork/var/shuboz: Modify touchpad setting for Jelboz
by Kane Chen (Code Review) 02 Feb '21

02 Feb '21

Attention is currently required from: Martin Roth, Bhanu Prakash Maiya, Paul Menzel, Eric Peers. Hello build bot (Jenkins), Martin Roth, Bhanu Prakash Maiya, Eric Peers, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/49742 to look at the new patch set (#13). Change subject: mb/google/zork/var/shuboz: Modify touchpad setting for Jelboz ...................................................................... mb/google/zork/var/shuboz: Modify touchpad setting for Jelboz Since Jelboz support number pad, due to one single coreboot for both Jelboz and Shuboz, modify "overridetree.cb" setting to number pad support for Jelboz. BUG=b:174964012 BRANCH=master TEST=emerge-zork coreboot chromeos-bootimage Signed-off-by: Kane Chen <kane_chen(a)pegatron.corp-partner.google.com> Change-Id: Ie0219419834b34b6eac589f28d3604f5f1b65679 --- M src/mainboard/google/zork/variants/shuboz/overridetree.cb 1 file changed, 8 insertions(+), 7 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/42/49742/13 -- To view, visit https://review.coreboot.org/c/coreboot/+/49742 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie0219419834b34b6eac589f28d3604f5f1b65679 Gerrit-Change-Number: 49742 Gerrit-PatchSet: 13 Gerrit-Owner: Kane Chen <kane_chen(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Bhanu Prakash Maiya <bhanumaiya(a)google.com> Gerrit-Reviewer: Eric Peers <epeers(a)google.com> Gerrit-Reviewer: Kane Chen <kane_chen(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com> Gerrit-CC: Hank Lin <hank2_lin(a)pegatron.corp-partner.google.com> Gerrit-CC: Ken Lu <ken_lu(a)pegatron.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-CC: Randy I-Fan Wang <ifanw(a)google.com> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Bhanu Prakash Maiya <bhanumaiya(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Attention: Eric Peers <epeers(a)google.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/google/zork/var/shuboz: Modify touchscreen for Jelboz
by Kane Chen (Code Review) 02 Feb '21

02 Feb '21

Kane Chen has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/50228 ) Change subject: mb/google/zork/var/shuboz: Modify touchscreen for Jelboz ...................................................................... mb/google/zork/var/shuboz: Modify touchscreen for Jelboz Modify GPIO_140 delay time and add "disable_gpio_export_in_crs" to follow IC spec setting. BUG=b:174447201 BRANCH=master TEST=emerge-zork coreboot chromeos-bootimage Signed-off-by: Kane Chen <kane_chen(a)pegatron.corp-partner.google.com> Change-Id: I36a7055b7be0963479f8a0f4dc49c92bc8fbdc9d --- M src/mainboard/google/zork/variants/shuboz/overridetree.cb 1 file changed, 2 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/28/50228/1 diff --git a/src/mainboard/google/zork/variants/shuboz/overridetree.cb b/src/mainboard/google/zork/variants/shuboz/overridetree.cb index 7160899..e53b6a7 100644 --- a/src/mainboard/google/zork/variants/shuboz/overridetree.cb +++ b/src/mainboard/google/zork/variants/shuboz/overridetree.cb @@ -54,8 +54,9 @@ register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_32)" register "enable_delay_ms" = "1" register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPIO_140)" - register "reset_delay_ms" = "20" + register "reset_delay_ms" = "300" register "has_power_resource" = "1" + register "disable_gpio_export_in_crs" = "1" device i2c 10 on end end chip drivers/i2c/generic -- To view, visit https://review.coreboot.org/c/coreboot/+/50228 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I36a7055b7be0963479f8a0f4dc49c92bc8fbdc9d Gerrit-Change-Number: 50228 Gerrit-PatchSet: 1 Gerrit-Owner: Kane Chen <kane_chen(a)pegatron.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: treewide [Kconfig]: Remove useless comment
by Nico Huber (Code Review) 02 Feb '21

02 Feb '21

Nico Huber has submitted this change. ( https://review.coreboot.org/c/coreboot/+/50185 ) Change subject: treewide [Kconfig]: Remove useless comment ...................................................................... treewide [Kconfig]: Remove useless comment Change-Id: I3dafffa61f4fe6089fd11ef6579626aff8088df5 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50185 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> --- M payloads/external/U-Boot/Kconfig M payloads/libpayload/arch/arm/Kconfig M payloads/libpayload/arch/arm64/Kconfig M payloads/libpayload/arch/x86/Kconfig M src/cpu/intel/slot_1/Kconfig M src/cpu/intel/socket_441/Kconfig M src/cpu/intel/socket_LGA775/Kconfig M src/cpu/intel/socket_m/Kconfig M src/cpu/intel/socket_mPGA604/Kconfig M src/mainboard/amd/padmelon/Kconfig M src/mainboard/google/veyron/Kconfig M src/northbridge/intel/e7505/Kconfig M src/northbridge/intel/gm45/Kconfig M src/northbridge/intel/i945/Kconfig M src/northbridge/intel/pineview/Kconfig M src/northbridge/intel/x4x/Kconfig M src/southbridge/amd/agesa/hudson/Kconfig M src/southbridge/amd/pi/hudson/Kconfig M src/southbridge/intel/bd82x6x/Kconfig M src/southbridge/intel/ibexpeak/Kconfig M src/southbridge/intel/lynxpoint/Kconfig 21 files changed, 21 insertions(+), 21 deletions(-) Approvals: build bot (Jenkins): Verified Angel Pons: Looks good to me, approved diff --git a/payloads/external/U-Boot/Kconfig b/payloads/external/U-Boot/Kconfig index a2bc512..9e51ae1 100644 --- a/payloads/external/U-Boot/Kconfig +++ b/payloads/external/U-Boot/Kconfig @@ -1,6 +1,6 @@ if PAYLOAD_UBOOT -config PAYLOAD_SPECIFIC_OPTIONS # dummy +config PAYLOAD_SPECIFIC_OPTIONS def_bool y select PAYLOAD_IS_FLAT_BINARY diff --git a/payloads/libpayload/arch/arm/Kconfig b/payloads/libpayload/arch/arm/Kconfig index b5a2be5..acaf167 100644 --- a/payloads/libpayload/arch/arm/Kconfig +++ b/payloads/libpayload/arch/arm/Kconfig @@ -28,7 +28,7 @@ if ARCH_ARM -config ARCH_SPECIFIC_OPTIONS # dummy +config ARCH_SPECIFIC_OPTIONS def_bool y select LITTLE_ENDIAN diff --git a/payloads/libpayload/arch/arm64/Kconfig b/payloads/libpayload/arch/arm64/Kconfig index 439d27b..18f3770 100644 --- a/payloads/libpayload/arch/arm64/Kconfig +++ b/payloads/libpayload/arch/arm64/Kconfig @@ -28,7 +28,7 @@ if ARCH_ARM64 -config ARCH_SPECIFIC_OPTIONS # dummy +config ARCH_SPECIFIC_OPTIONS def_bool y select LITTLE_ENDIAN diff --git a/payloads/libpayload/arch/x86/Kconfig b/payloads/libpayload/arch/x86/Kconfig index 05cf58b..f590d58 100644 --- a/payloads/libpayload/arch/x86/Kconfig +++ b/payloads/libpayload/arch/x86/Kconfig @@ -28,7 +28,7 @@ if ARCH_X86 -config ARCH_SPECIFIC_OPTIONS # dummy +config ARCH_SPECIFIC_OPTIONS def_bool y select LITTLE_ENDIAN select IO_ADDRESS_SPACE diff --git a/src/cpu/intel/slot_1/Kconfig b/src/cpu/intel/slot_1/Kconfig index aafe110..cc24833 100644 --- a/src/cpu/intel/slot_1/Kconfig +++ b/src/cpu/intel/slot_1/Kconfig @@ -5,7 +5,7 @@ if CPU_INTEL_SLOT_1 -config SLOT_SPECIFIC_OPTIONS # dummy +config SLOT_SPECIFIC_OPTIONS def_bool y select CPU_INTEL_MODEL_65X select CPU_INTEL_MODEL_67X diff --git a/src/cpu/intel/socket_441/Kconfig b/src/cpu/intel/socket_441/Kconfig index 1b930de..5b6ae7f 100644 --- a/src/cpu/intel/socket_441/Kconfig +++ b/src/cpu/intel/socket_441/Kconfig @@ -3,7 +3,7 @@ if CPU_INTEL_SOCKET_441 -config SOCKET_SPECIFIC_OPTIONS # dummy +config SOCKET_SPECIFIC_OPTIONS def_bool y select CPU_INTEL_MODEL_106CX select MMX diff --git a/src/cpu/intel/socket_LGA775/Kconfig b/src/cpu/intel/socket_LGA775/Kconfig index 3ce106a..0848d26 100644 --- a/src/cpu/intel/socket_LGA775/Kconfig +++ b/src/cpu/intel/socket_LGA775/Kconfig @@ -3,7 +3,7 @@ if CPU_INTEL_SOCKET_LGA775 -config SOCKET_SPECIFIC_OPTIONS # dummy +config SOCKET_SPECIFIC_OPTIONS def_bool y select CPU_INTEL_MODEL_6FX select CPU_INTEL_MODEL_F3X diff --git a/src/cpu/intel/socket_m/Kconfig b/src/cpu/intel/socket_m/Kconfig index 32eedb6..50eb7e3 100644 --- a/src/cpu/intel/socket_m/Kconfig +++ b/src/cpu/intel/socket_m/Kconfig @@ -3,7 +3,7 @@ if CPU_INTEL_SOCKET_M -config SOCKET_SPECIFIC_OPTIONS # dummy +config SOCKET_SPECIFIC_OPTIONS def_bool y select CPU_INTEL_MODEL_6EX select CPU_INTEL_MODEL_6FX diff --git a/src/cpu/intel/socket_mPGA604/Kconfig b/src/cpu/intel/socket_mPGA604/Kconfig index 176ae9e..7b08699 100644 --- a/src/cpu/intel/socket_mPGA604/Kconfig +++ b/src/cpu/intel/socket_mPGA604/Kconfig @@ -3,7 +3,7 @@ if CPU_INTEL_SOCKET_MPGA604 -config SOCKET_SPECIFIC_OPTIONS # dummy +config SOCKET_SPECIFIC_OPTIONS def_bool y select CPU_INTEL_MODEL_F2X select MMX diff --git a/src/mainboard/amd/padmelon/Kconfig b/src/mainboard/amd/padmelon/Kconfig index 894df57..48df9ca 100644 --- a/src/mainboard/amd/padmelon/Kconfig +++ b/src/mainboard/amd/padmelon/Kconfig @@ -2,7 +2,7 @@ if BOARD_AMD_PADMELON -config BOARD_SPECIFIC_OPTIONS # dummy +config BOARD_SPECIFIC_OPTIONS def_bool y select SOC_AMD_STONEYRIDGE select AMD_APU_PKG_FP4 diff --git a/src/mainboard/google/veyron/Kconfig b/src/mainboard/google/veyron/Kconfig index 1d3496c..97444d8 100644 --- a/src/mainboard/google/veyron/Kconfig +++ b/src/mainboard/google/veyron/Kconfig @@ -1,6 +1,6 @@ ## SPDX-License-Identifier: GPL-2.0-only -config BOARD_GOOGLE_VEYRON # dummy option to be selected by variant boards +config BOARD_GOOGLE_VEYRON def_bool n if BOARD_GOOGLE_VEYRON diff --git a/src/northbridge/intel/e7505/Kconfig b/src/northbridge/intel/e7505/Kconfig index e07691a..d222e2e 100644 --- a/src/northbridge/intel/e7505/Kconfig +++ b/src/northbridge/intel/e7505/Kconfig @@ -5,7 +5,7 @@ if NORTHBRIDGE_INTEL_E7505 -config NORTHBRIDGE_SPECIFIC_OPTIONS # dummy +config NORTHBRIDGE_SPECIFIC_OPTIONS def_bool y select NO_MMCONF_SUPPORT select HAVE_DEBUG_RAM_SETUP diff --git a/src/northbridge/intel/gm45/Kconfig b/src/northbridge/intel/gm45/Kconfig index 256b088..58942f0 100644 --- a/src/northbridge/intel/gm45/Kconfig +++ b/src/northbridge/intel/gm45/Kconfig @@ -5,7 +5,7 @@ if NORTHBRIDGE_INTEL_GM45 -config NORTHBRIDGE_SPECIFIC_OPTIONS # dummy +config NORTHBRIDGE_SPECIFIC_OPTIONS def_bool y select HAVE_DEBUG_RAM_SETUP select VGA diff --git a/src/northbridge/intel/i945/Kconfig b/src/northbridge/intel/i945/Kconfig index 456193a..23369e7 100644 --- a/src/northbridge/intel/i945/Kconfig +++ b/src/northbridge/intel/i945/Kconfig @@ -5,7 +5,7 @@ if NORTHBRIDGE_INTEL_I945 -config NORTHBRIDGE_SPECIFIC_OPTIONS # dummy +config NORTHBRIDGE_SPECIFIC_OPTIONS def_bool y select HAVE_DEBUG_RAM_SETUP select VGA diff --git a/src/northbridge/intel/pineview/Kconfig b/src/northbridge/intel/pineview/Kconfig index b1863ef..ad134f2 100644 --- a/src/northbridge/intel/pineview/Kconfig +++ b/src/northbridge/intel/pineview/Kconfig @@ -5,7 +5,7 @@ if NORTHBRIDGE_INTEL_PINEVIEW -config NORTHBRIDGE_SPECIFIC_OPTIONS # dummy +config NORTHBRIDGE_SPECIFIC_OPTIONS def_bool y select HAVE_DEBUG_RAM_SETUP select VGA diff --git a/src/northbridge/intel/x4x/Kconfig b/src/northbridge/intel/x4x/Kconfig index 32e85d3..711340d 100644 --- a/src/northbridge/intel/x4x/Kconfig +++ b/src/northbridge/intel/x4x/Kconfig @@ -5,7 +5,7 @@ if NORTHBRIDGE_INTEL_X4X -config NORTHBRIDGE_SPECIFIC_OPTIONS # dummy +config NORTHBRIDGE_SPECIFIC_OPTIONS def_bool y select HAVE_DEBUG_RAM_SETUP select VGA diff --git a/src/southbridge/amd/agesa/hudson/Kconfig b/src/southbridge/amd/agesa/hudson/Kconfig index d0fbc49..06162775 100644 --- a/src/southbridge/amd/agesa/hudson/Kconfig +++ b/src/southbridge/amd/agesa/hudson/Kconfig @@ -8,7 +8,7 @@ if SOUTHBRIDGE_AMD_AGESA_HUDSON || SOUTHBRIDGE_AMD_AGESA_YANGTZE -config SOUTHBRIDGE_SPECIFIC_OPTIONS # dummy +config SOUTHBRIDGE_SPECIFIC_OPTIONS def_bool y select IOAPIC select HAVE_USBDEBUG_OPTIONS diff --git a/src/southbridge/amd/pi/hudson/Kconfig b/src/southbridge/amd/pi/hudson/Kconfig index 6280f3a..b3b844f 100644 --- a/src/southbridge/amd/pi/hudson/Kconfig +++ b/src/southbridge/amd/pi/hudson/Kconfig @@ -11,7 +11,7 @@ if SOUTHBRIDGE_AMD_PI_AVALON || SOUTHBRIDGE_AMD_PI_BOLTON || SOUTHBRIDGE_AMD_PI_KERN -config SOUTHBRIDGE_SPECIFIC_OPTIONS # dummy +config SOUTHBRIDGE_SPECIFIC_OPTIONS def_bool y select IOAPIC select HAVE_USBDEBUG_OPTIONS diff --git a/src/southbridge/intel/bd82x6x/Kconfig b/src/southbridge/intel/bd82x6x/Kconfig index 06ac5c6..21816e5 100644 --- a/src/southbridge/intel/bd82x6x/Kconfig +++ b/src/southbridge/intel/bd82x6x/Kconfig @@ -8,7 +8,7 @@ if SOUTHBRIDGE_INTEL_BD82X6X || SOUTHBRIDGE_INTEL_C216 -config SOUTH_BRIDGE_OPTIONS # dummy +config SOUTH_BRIDGE_OPTIONS def_bool y select ACPI_INTEL_HARDWARE_SLEEP_VALUES select ACPI_SOC_NVS diff --git a/src/southbridge/intel/ibexpeak/Kconfig b/src/southbridge/intel/ibexpeak/Kconfig index cea0efe..f172bf1 100644 --- a/src/southbridge/intel/ibexpeak/Kconfig +++ b/src/southbridge/intel/ibexpeak/Kconfig @@ -5,7 +5,7 @@ if SOUTHBRIDGE_INTEL_IBEXPEAK -config SOUTH_BRIDGE_OPTIONS # dummy +config SOUTH_BRIDGE_OPTIONS def_bool y select ACPI_INTEL_HARDWARE_SLEEP_VALUES select ACPI_SOC_NVS diff --git a/src/southbridge/intel/lynxpoint/Kconfig b/src/southbridge/intel/lynxpoint/Kconfig index 7ad3c00..a9a2f5b 100644 --- a/src/southbridge/intel/lynxpoint/Kconfig +++ b/src/southbridge/intel/lynxpoint/Kconfig @@ -5,7 +5,7 @@ if SOUTHBRIDGE_INTEL_LYNXPOINT -config SOUTH_BRIDGE_OPTIONS # dummy +config SOUTH_BRIDGE_OPTIONS def_bool y select ACPI_INTEL_HARDWARE_SLEEP_VALUES select ACPI_SOC_NVS -- To view, visit https://review.coreboot.org/c/coreboot/+/50185 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3dafffa61f4fe6089fd11ef6579626aff8088df5 Gerrit-Change-Number: 50185 Gerrit-PatchSet: 2 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Damien Zammit Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: amdfwtool:cezanne: Add entry of PSP_BOOTLOADER_AB (0x73)
by Bao Zheng (Code Review) 02 Feb '21

02 Feb '21

Attention is currently required from: Zheng Bao. Hello Zheng Bao, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/50227 to review the following change. Change subject: amdfwtool:cezanne: Add entry of PSP_BOOTLOADER_AB (0x73) ...................................................................... amdfwtool:cezanne: Add entry of PSP_BOOTLOADER_AB (0x73) Change-Id: Ie3577b403c1de7f20b6d5bcf9e1a5d47450266fe Signed-off-by: Zheng Bao <fishbaozi(a)gmail.com> --- M src/soc/amd/cezanne/fw.cfg M util/amdfwtool/amdfwtool.c M util/amdfwtool/amdfwtool.h M util/amdfwtool/data_parse.c 4 files changed, 6 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/27/50227/1 diff --git a/src/soc/amd/cezanne/fw.cfg b/src/soc/amd/cezanne/fw.cfg index 189bc9d..277707d 100644 --- a/src/soc/amd/cezanne/fw.cfg +++ b/src/soc/amd/cezanne/fw.cfg @@ -29,6 +29,7 @@ KEYDB_TOS_FILE TypeId0x51_KeyDbTos_CZN.sbin DMCUERAMDCN21_FILE TypeId0x58_DmcuEramDcn21.sbin DMCUINTVECTORSDCN21_FILE TypeId0x59_DmcuIntvectorsDcn21.sbin +PSPBTLDR_AB_FILE TypeId0x73_PspBootLoader_AB_CZN.sbin # BDT PSP_PMUI_FILE1 TypeId0x64_Appb_CZN_1D_Lpddr4_Imem.csbin diff --git a/util/amdfwtool/amdfwtool.c b/util/amdfwtool/amdfwtool.c index 23890d0..36db786 100644 --- a/util/amdfwtool/amdfwtool.c +++ b/util/amdfwtool/amdfwtool.c @@ -261,6 +261,7 @@ { .type = AMD_FW_DMCU_ERAM, .level = PSP_LVL2 }, { .type = AMD_FW_DMCU_ISR, .level = PSP_LVL2 }, { .type = AMD_RPMC_NVRAM, .level = PSP_LVL2 }, + { .type = AMD_FW_PSP_BOOTLOADER_AB, .level = PSP_LVL2 }, { .type = AMD_ABL0, .level = PSP_BOTH }, { .type = AMD_ABL1, .level = PSP_BOTH }, { .type = AMD_ABL2, .level = PSP_BOTH }, diff --git a/util/amdfwtool/amdfwtool.h b/util/amdfwtool/amdfwtool.h index fcad948..b59c9cc 100644 --- a/util/amdfwtool/amdfwtool.h +++ b/util/amdfwtool/amdfwtool.h @@ -47,6 +47,7 @@ AMD_RPMC_NVRAM = 0x54, AMD_FW_DMCU_ERAM = 0x58, AMD_FW_DMCU_ISR = 0x59, + AMD_FW_PSP_BOOTLOADER_AB = 0x73, AMD_FW_IMC = 0x200, /* Large enough to be larger than the top BHD entry type. */ AMD_FW_GEC, AMD_FW_XHCI, diff --git a/util/amdfwtool/data_parse.c b/util/amdfwtool/data_parse.c index 1e83490..8a6306f 100644 --- a/util/amdfwtool/data_parse.c +++ b/util/amdfwtool/data_parse.c @@ -244,6 +244,9 @@ } else if (strcmp(fw_name, "RPMC_FILE") == 0) { fw_type = AMD_RPMC_NVRAM; subprog = 0; + } else if (strcmp(fw_name, "PSPBTLDR_AB_FILE") == 0) { + fw_type = AMD_FW_PSP_BOOTLOADER_AB; + subprog = 0; } else { fw_type = AMD_FW_INVALID; /* TODO: Add more */ -- To view, visit https://review.coreboot.org/c/coreboot/+/50227 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie3577b403c1de7f20b6d5bcf9e1a5d47450266fe Gerrit-Change-Number: 50227 Gerrit-PatchSet: 1 Gerrit-Owner: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Zheng Bao Gerrit-Attention: Zheng Bao Gerrit-MessageType: newchange

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Change in coreboot[master]: WIP: soc/mediatek/mt8192: modify i2c ext_conf
by build bot (Jenkins) (Code Review) 02 Feb '21

02 Feb '21

Attention is currently required from: Hung-Te Lin. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50224 ) Change subject: WIP: soc/mediatek/mt8192: modify i2c ext_conf ...................................................................... Patch Set 1: (1 comment) File src/soc/mediatek/common/i2c.c: https://review.coreboot.org/c/coreboot/+/50224/comment/038e402e_f9c7bb63 PS1, Line 195: printk(BIOS_ERR, "[mtk_debug][i2c%d][addr0x%x] ext_conf(0x%x)\n", bus, addr, read32(&regs->ext_conf)); line over 96 characters -- To view, visit https://review.coreboot.org/c/coreboot/+/50224 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0dbcda495ec6f7a8adc51d674dffffef6999745c Gerrit-Change-Number: 50224 Gerrit-PatchSet: 1 Gerrit-Owner: Jg Daolongzhu <jg_daolongzhu(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Comment-Date: Tue, 02 Feb 2021 12:35:20 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: drivers/intel/fsp2_0: Integrate FirmwareVersionInfo.h
by Ronak Kanabar (Code Review) 02 Feb '21

02 Feb '21

Attention is currently required from: Nico Huber, Maulik V Vaghela, Paul Menzel, Subrata Banik, Aamir Bohra. Ronak Kanabar has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45905 ) Change subject: drivers/intel/fsp2_0: Integrate FirmwareVersionInfo.h ...................................................................... Patch Set 12: (2 comments) File src/drivers/intel/fsp2_0/hand_off_block.c: https://review.coreboot.org/c/coreboot/+/45905/comment/e33d7206_0da4d6a1 PS12, Line 212: #if CONFIG(DISPLAY_FSP_VERSION_INFO) || CONFIG(DISPLAY_FSP_VERSION_INFO_2) > do we really need a guard here? if someone/some platform will not select any of the config. below code will prompt compilation error. code from line number 241 https://review.coreboot.org/c/coreboot/+/45905/comment/9cb5af09_819bcded PS12, Line 226: #elif > just #if CONFIG(DISPLAY_FSP_VERSION_INFO_2) won't work ? both can work #endif #if CONFIG(DISPLAY_FSP_VERSION_INFO_2) or #elif CONFIG(DISPLAY_FSP_VERSION_INFO_2) so i went for elif do you think we should use only #if ? -- To view, visit https://review.coreboot.org/c/coreboot/+/45905 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I50f7cae9ed4fac60f91d86bdd3e884956627e4b5 Gerrit-Change-Number: 45905 Gerrit-PatchSet: 12 Gerrit-Owner: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Patrick Rudolph Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Comment-Date: Tue, 02 Feb 2021 12:33:07 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subrata.banik(a)intel.com> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/alderlake: select MP PPI services v2 support
by Subrata Banik (Code Review) 02 Feb '21

02 Feb '21

Attention is currently required from: Aamir Bohra, Patrick Rudolph. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50226 ) Change subject: soc/intel/alderlake: select MP PPI services v2 support ...................................................................... Patch Set 1: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/50226 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5c1ef6c5dde359b57412854f6e42fa7acbb1172f Gerrit-Change-Number: 50226 Gerrit-PatchSet: 1 Gerrit-Owner: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Tue, 02 Feb 2021 12:28:41 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: drivers/intel/fsp2_0: Add support for MP PPI services2 APIs
by Subrata Banik (Code Review) 02 Feb '21

02 Feb '21

Attention is currently required from: Furquan Shaikh, Martin Roth, Meera Ravindranath, Aamir Bohra, Tim Wawrzynczak, Andrey Petrov, Patrick Rudolph. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49474 ) Change subject: drivers/intel/fsp2_0: Add support for MP PPI services2 APIs ...................................................................... Patch Set 5: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/49474 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id74baf17fb90147d229c78be90268fdc3ec1badc Gerrit-Change-Number: 49474 Gerrit-PatchSet: 5 Gerrit-Owner: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-CC: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Attention: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)google.com> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Tue, 02 Feb 2021 12:28:28 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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coreboot-gerrit February 2021