coreboot-gerrit February 2021

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Change in coreboot[master]: mb/intel/adlrvp/bootblock.c: Remove unused includes
by HAOUAS Elyes (Code Review) 02 Feb '21

02 Feb '21

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/50222 ) Change subject: mb/intel/adlrvp/bootblock.c: Remove unused includes ...................................................................... mb/intel/adlrvp/bootblock.c: Remove unused includes Change-Id: I73234da6e77f83c6aeb5c40cf6ffdb3cccc4074c Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/mainboard/intel/adlrvp/bootblock.c 1 file changed, 0 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/22/50222/1 diff --git a/src/mainboard/intel/adlrvp/bootblock.c b/src/mainboard/intel/adlrvp/bootblock.c index 95f7497..211fcf9 100644 --- a/src/mainboard/intel/adlrvp/bootblock.c +++ b/src/mainboard/intel/adlrvp/bootblock.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <baseboard/gpio.h> #include <baseboard/variants.h> #include <bootblock_common.h> -- To view, visit https://review.coreboot.org/c/coreboot/+/50222 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I73234da6e77f83c6aeb5c40cf6ffdb3cccc4074c Gerrit-Change-Number: 50222 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/gizmosphere/gizmo2/bootblock.c: Remove unused includes
by HAOUAS Elyes (Code Review) 02 Feb '21

02 Feb '21

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/50221 ) Change subject: mb/gizmosphere/gizmo2/bootblock.c: Remove unused includes ...................................................................... mb/gizmosphere/gizmo2/bootblock.c: Remove unused includes Change-Id: Ibdc94e59ffa345670bbed246e94b02a7148a1971 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/mainboard/gizmosphere/gizmo2/bootblock.c 1 file changed, 0 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/21/50221/1 diff --git a/src/mainboard/gizmosphere/gizmo2/bootblock.c b/src/mainboard/gizmosphere/gizmo2/bootblock.c index 3fe9351..ccd8ec1 100644 --- a/src/mainboard/gizmosphere/gizmo2/bootblock.c +++ b/src/mainboard/gizmosphere/gizmo2/bootblock.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <amdblocks/acpimmio.h> #include <bootblock_common.h> void bootblock_mainboard_early_init(void) -- To view, visit https://review.coreboot.org/c/coreboot/+/50221 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibdc94e59ffa345670bbed246e94b02a7148a1971 Gerrit-Change-Number: 50221 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/emulation/qemu-q35/bootblock.c: Remove unused includes
by HAOUAS Elyes (Code Review) 02 Feb '21

02 Feb '21

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/50220 ) Change subject: mb/emulation/qemu-q35/bootblock.c: Remove unused includes ...................................................................... mb/emulation/qemu-q35/bootblock.c: Remove unused includes Change-Id: I568c7260f838c03c285f2afc0e20794c06a47645 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/mainboard/emulation/qemu-q35/bootblock.c 1 file changed, 0 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/20/50220/1 diff --git a/src/mainboard/emulation/qemu-q35/bootblock.c b/src/mainboard/emulation/qemu-q35/bootblock.c index cdca27a..cbf6ef9 100644 --- a/src/mainboard/emulation/qemu-q35/bootblock.c +++ b/src/mainboard/emulation/qemu-q35/bootblock.c @@ -4,7 +4,6 @@ #include <bootblock_common.h> #include <southbridge/intel/common/early_spi.h> #include <southbridge/intel/i82801ix/i82801ix.h> -#include <console/console.h> #include "q35.h" -- To view, visit https://review.coreboot.org/c/coreboot/+/50220 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I568c7260f838c03c285f2afc0e20794c06a47645 Gerrit-Change-Number: 50220 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/clevo/cml-u/bootblock.c: Remove unused includes
by HAOUAS Elyes (Code Review) 02 Feb '21

02 Feb '21

Attention is currently required from: Felix Singer, Michael Niewöhner. HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/50219 ) Change subject: mb/clevo/cml-u/bootblock.c: Remove unused includes ...................................................................... mb/clevo/cml-u/bootblock.c: Remove unused includes Change-Id: I048e906306bf77a941b5f731ade15292fa944390 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/mainboard/clevo/cml-u/bootblock.c 1 file changed, 0 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/19/50219/1 diff --git a/src/mainboard/clevo/cml-u/bootblock.c b/src/mainboard/clevo/cml-u/bootblock.c index 0b5965a..b351fbd 100644 --- a/src/mainboard/clevo/cml-u/bootblock.c +++ b/src/mainboard/clevo/cml-u/bootblock.c @@ -1,7 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <bootblock_common.h> -#include <gpio.h> #include <variant/gpio.h> void bootblock_mainboard_early_init(void) -- To view, visit https://review.coreboot.org/c/coreboot/+/50219 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I048e906306bf77a941b5f731ade15292fa944390 Gerrit-Change-Number: 50219 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Attention: Felix Singer <felixsinger(a)posteo.net> Gerrit-Attention: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/amd/{parmer,thatcher}/bootblock.c: Remove unused includes
by HAOUAS Elyes (Code Review) 02 Feb '21

02 Feb '21

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/50218 ) Change subject: mb/amd/{parmer,thatcher}/bootblock.c: Remove unused includes ...................................................................... mb/amd/{parmer,thatcher}/bootblock.c: Remove unused includes Change-Id: I4d5520649addc671527e75f9090ea45a83b5db9b Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/mainboard/amd/parmer/bootblock.c M src/mainboard/amd/thatcher/bootblock.c 2 files changed, 0 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/18/50218/1 diff --git a/src/mainboard/amd/parmer/bootblock.c b/src/mainboard/amd/parmer/bootblock.c index 29f7abb..ccd8ec1 100644 --- a/src/mainboard/amd/parmer/bootblock.c +++ b/src/mainboard/amd/parmer/bootblock.c @@ -1,7 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <bootblock_common.h> -#include <device/pci_ops.h> void bootblock_mainboard_early_init(void) { diff --git a/src/mainboard/amd/thatcher/bootblock.c b/src/mainboard/amd/thatcher/bootblock.c index 468c938..e01131d 100644 --- a/src/mainboard/amd/thatcher/bootblock.c +++ b/src/mainboard/amd/thatcher/bootblock.c @@ -2,7 +2,6 @@ #include <amdblocks/acpimmio.h> #include <bootblock_common.h> -#include <device/pci_ops.h> #include <console/console.h> #include <superio/smsc/lpc47n217/lpc47n217.h> -- To view, visit https://review.coreboot.org/c/coreboot/+/50218 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4d5520649addc671527e75f9090ea45a83b5db9b Gerrit-Change-Number: 50218 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/alderlake: Add support for external clock buffer
by Subrata Banik (Code Review) 02 Feb '21

02 Feb '21

Attention is currently required from: Furquan Shaikh, Tim Wawrzynczak, Angel Pons, Patrick Rudolph, EricR Lai. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50162 ) Change subject: soc/intel/alderlake: Add support for external clock buffer ...................................................................... Patch Set 1: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/50162/comment/54f4bf04_f495bdfd PS1, Line 9: 3 CLKSRC using external clock buffer. : CLKSRC 6 provides feed clock to discrete buffer for further : distribution to platform. > Hmmm... […] Thanks Angel, your understanding is very valid. This part is assume closed. The only puzzle that i have looks like disabling CLKSRC7:9 is causing device not detecting on RP7. Need to understand -- To view, visit https://review.coreboot.org/c/coreboot/+/50162 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If49d756ed47d577fd839516d4e707563700453d2 Gerrit-Change-Number: 50162 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Comment-Date: Tue, 02 Feb 2021 11:34:26 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Furquan Shaikh <furquan(a)google.com> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Comment-In-Reply-To: Subrata Banik <subrata.banik(a)intel.com> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/volteer/variants/drobit: Configure USB2 port for Type-C
by Wayne3 Wang (Code Review) 02 Feb '21

02 Feb '21

Attention is currently required from: Hank Lin, Ken Lu. Wayne3 Wang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50217 ) Change subject: mb/google/volteer/variants/drobit: Configure USB2 port for Type-C ...................................................................... Patch Set 1: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/50217 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9e962f8cd76e1986700821168594c50bc21553e9 Gerrit-Change-Number: 50217 Gerrit-PatchSet: 1 Gerrit-Owner: Wayne3 Wang <wayne3_wang(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Hank Lin <hank2_lin(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Ken Lu <ken_lu(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Wayne3 Wang <wayne3_wang(a)pegatron.corp-partner.google.com> Gerrit-CC: Alex1 Kao <alex1_kao(a)pegatron.corp-partner.google.com> Gerrit-CC: Ariel Chang <ariel_chang(a)pegatron.corp-partner.google.com> Gerrit-CC: Hao Chou <hao_chou(a)pegatron.corp-partner.google.com> Gerrit-CC: Kirk Wang <kirk_wang(a)pegatron.corp-partner.google.com> Gerrit-CC: Paul2 Huang <paul2_huang(a)pegatron.corp-partner.google.com> Gerrit-Attention: Hank Lin <hank2_lin(a)pegatron.corp-partner.google.com> Gerrit-Attention: Ken Lu <ken_lu(a)pegatron.corp-partner.google.com> Gerrit-Comment-Date: Tue, 02 Feb 2021 11:15:29 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: sb,soc/intel: Add wake source fields in GNVS
by Angel Pons (Code Review) 02 Feb '21

02 Feb '21

Attention is currently required from: Lance Zhao, Kyösti Mälkki, Patrick Rudolph. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50193 ) Change subject: sb,soc/intel: Add wake source fields in GNVS ...................................................................... Patch Set 2: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/50193 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6d31d39ac1017cd6fdf0ac66b418d1fbb1edf8e0 Gerrit-Change-Number: 50193 Gerrit-PatchSet: 2 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Lance Zhao Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Lance Zhao Gerrit-Attention: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Tue, 02 Feb 2021 11:12:34 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/amd/picasso: clean up and re-sort UPD table
by chris wang (Code Review) 02 Feb '21

02 Feb '21

Attention is currently required from: Frank Wu, Jason Glenesk, Raul Rangel, Martin Roth, Marshall Dawson, Chris Wang, EricR Lai, Felix Held. chris wang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50212 ) Change subject: soc/amd/picasso: clean up and re-sort UPD table ...................................................................... Patch Set 3: (1 comment) Patchset: PS3: > Is there AMD private CL to match up? @Eric No PSP change. @Frank Please refer to below https://chrome-internal-review.googlesource.com/c/chromeos/third_party/amd-… -- To view, visit https://review.coreboot.org/c/coreboot/+/50212 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I655af08e2f86398d088e30d330f49e71cf7e1275 Gerrit-Change-Number: 50212 Gerrit-PatchSet: 3 Gerrit-Owner: chris wang <Chris.Wang(a)amd.com> Gerrit-Reviewer: Chris Wang <chris.wang(a)amd.corp-partner.google.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Frank Wu <frank_wu(a)compal.corp-partner.google.com> Gerrit-CC: John Su <john_su(a)compal.corp-partner.google.com> Gerrit-Attention: Frank Wu <frank_wu(a)compal.corp-partner.google.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Chris Wang <chris.wang(a)amd.corp-partner.google.com> Gerrit-Attention: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Tue, 02 Feb 2021 11:12:11 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Frank Wu <frank_wu(a)compal.corp-partner.google.com> Comment-In-Reply-To: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/volteer/variants/drobit: Configure USB2 port for Type-C
by Wayne3 Wang (Code Review) 02 Feb '21

02 Feb '21

Wayne3 Wang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/50217 ) Change subject: mb/google/volteer/variants/drobit: Configure USB2 port for Type-C ...................................................................... mb/google/volteer/variants/drobit: Configure USB2 port for Type-C USB2 ports assigned to type-C connector need to be configured properly by the USB2_PORT_TYPE_C. and also modify the description of USB port. BUG=b:177480902 BRANCH=firmware-volteer-13672.B TEST=emerge-volteer coreboot chromeos-bootimage build Pass And check the typeC port function is normal by manual. Signed-off-by: Wayne3_Wang <Wayne3_Wang(a)pegatron.corp-partner.google.com> Change-Id: I9e962f8cd76e1986700821168594c50bc21553e9 --- M src/mainboard/google/volteer/variants/drobit/overridetree.cb 1 file changed, 7 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/17/50217/1 diff --git a/src/mainboard/google/volteer/variants/drobit/overridetree.cb b/src/mainboard/google/volteer/variants/drobit/overridetree.cb index 17143b8..608535e 100644 --- a/src/mainboard/google/volteer/variants/drobit/overridetree.cb +++ b/src/mainboard/google/volteer/variants/drobit/overridetree.cb @@ -21,6 +21,9 @@ .tdp_pl4 = 105, }" + register "usb2_ports[3]" = "USB2_PORT_TYPE_C(OC0)" # Type-C port 1 + register "usb2_ports[8]" = "USB2_PORT_TYPE_C(OC3)" # Type-C port 0 + #+-------------------+---------------------------+ #| Field | Value | #+-------------------+---------------------------+ @@ -178,7 +181,7 @@ device ref tcss_usb3_port1 on end end chip drivers/usb/acpi - register "desc" = ""USB3 Type-C Port C1 (DB)"" + register "desc" = ""USB3 Type-C Port C1 (MLB)"" register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" register "group" = "ACPI_PLD_GROUP(2, 2)" device ref tcss_usb3_port2 on @@ -192,13 +195,13 @@ chip drivers/usb/acpi device ref xhci_root_hub on chip drivers/usb/acpi - register "desc" = ""USB2 Type-A Port A0 (MLB)"" + register "desc" = ""USB2 Type-A Port A0 (DB)"" register "type" = "UPC_TYPE_A" register "group" = "ACPI_PLD_GROUP(1, 1)" device ref usb2_port1 on end end chip drivers/usb/acpi - register "desc" = ""USB2 Type-C Port C1 (DB)"" + register "desc" = ""USB2 Type-C Port C1 (MLB)"" register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" register "group" = "ACPI_PLD_GROUP(2, 1)" device ref usb2_port4 on @@ -223,7 +226,7 @@ device ref usb2_port10 on end end chip drivers/usb/acpi - register "desc" = ""USB3 Type-A Port A0 (MLB)"" + register "desc" = ""USB3 Type-A Port A0 (DB)"" register "type" = "UPC_TYPE_USB3_A" register "group" = "ACPI_PLD_GROUP(1, 2)" device ref usb3_port1 on end -- To view, visit https://review.coreboot.org/c/coreboot/+/50217 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9e962f8cd76e1986700821168594c50bc21553e9 Gerrit-Change-Number: 50217 Gerrit-PatchSet: 1 Gerrit-Owner: Wayne3 Wang <wayne3_wang(a)pegatron.corp-partner.google.com> Gerrit-MessageType: newchange

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coreboot-gerrit February 2021