coreboot-gerrit February 2021

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: mb/siemens/mc_apl1: do UART pad configuration at board-level
by Angel Pons (Code Review) 02 Feb '21

02 Feb '21

Attention is currently required from: Nico Huber, Tim Wawrzynczak, Michael Niewöhner. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49442 ) Change subject: mb/siemens/mc_apl1: do UART pad configuration at board-level ...................................................................... Patch Set 9: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/49442 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iac8a6e386b708ae5c4dbf0677bfe05f1358bf8fd Gerrit-Change-Number: 49442 Gerrit-PatchSet: 9 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Uwe Poeche <uwe.poeche(a)siemens.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: siemens-bot Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Comment-Date: Tue, 02 Feb 2021 11:10:30 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: device: correct code style
by Angel Pons (Code Review) 02 Feb '21

02 Feb '21

Attention is currently required from: Frans Hendriks. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49963 ) Change subject: device: correct code style ...................................................................... Patch Set 3: Code-Review+2 (2 comments) File src/device/i2c_bus.c: https://review.coreboot.org/c/coreboot/+/49963/comment/44389fd9_59db03b3 PS1, Line 84: dev_path(busdev)); > *poke* Oh, CB:50190 https://review.coreboot.org/c/coreboot/+/49963/comment/51beaf15_31e11e7a PS1, Line 147: dev_path(busdev)); > *poke* Oh, CB:50190 -- To view, visit https://review.coreboot.org/c/coreboot/+/49963 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I780251d946d5bea97658476d61d25555ec768dfc Gerrit-Change-Number: 49963 Gerrit-PatchSet: 3 Gerrit-Owner: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Attention: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Comment-Date: Tue, 02 Feb 2021 11:09:58 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

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Change in coreboot[master]: device/i2c_bus.c: Correct code style
by Angel Pons (Code Review) 02 Feb '21

02 Feb '21

Attention is currently required from: Frans Hendriks, Wim Vervoorn. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50190 ) Change subject: device/i2c_bus.c: Correct code style ...................................................................... Patch Set 1: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/50190/comment/4aba40bc_ce850db0 PS1, Line 13: line feeds unnecessary newlines -- To view, visit https://review.coreboot.org/c/coreboot/+/50190 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I78ce97b0ce1587119a71893c867c2dd062552a31 Gerrit-Change-Number: 50190 Gerrit-PatchSet: 1 Gerrit-Owner: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Wim Vervoorn <wvervoorn(a)eltan.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Attention: Wim Vervoorn <wvervoorn(a)eltan.com> Gerrit-Comment-Date: Tue, 02 Feb 2021 11:09:36 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: device/i2c_bus.c: Correct code style
by Angel Pons (Code Review) 02 Feb '21

02 Feb '21

Attention is currently required from: Frans Hendriks, Wim Vervoorn. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50190 ) Change subject: device/i2c_bus.c: Correct code style ...................................................................... Patch Set 1: Code-Review+1 (1 comment) File src/device/i2c_bus.c: https://review.coreboot.org/c/coreboot/+/50190/comment/be6bccb4_3241e511 PS1, Line 30: dev_path(dev)); nit: Should be on the previous line. -- To view, visit https://review.coreboot.org/c/coreboot/+/50190 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I78ce97b0ce1587119a71893c867c2dd062552a31 Gerrit-Change-Number: 50190 Gerrit-PatchSet: 1 Gerrit-Owner: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Wim Vervoorn <wvervoorn(a)eltan.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Attention: Wim Vervoorn <wvervoorn(a)eltan.com> Gerrit-Comment-Date: Tue, 02 Feb 2021 11:09:20 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: device: correct code style
by Angel Pons (Code Review) 02 Feb '21

02 Feb '21

Attention is currently required from: Frans Hendriks. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49963 ) Change subject: device: correct code style ...................................................................... Patch Set 3: (2 comments) File src/device/i2c_bus.c: https://review.coreboot.org/c/coreboot/+/49963/comment/211e3aa3_c8c61ded PS1, Line 84: dev_path(busdev)); > Nit: fits on previous line. *poke* https://review.coreboot.org/c/coreboot/+/49963/comment/d29bf1d6_db8f2701 PS1, Line 147: dev_path(busdev)); > Nit: fits on previous line. *poke* -- To view, visit https://review.coreboot.org/c/coreboot/+/49963 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I780251d946d5bea97658476d61d25555ec768dfc Gerrit-Change-Number: 49963 Gerrit-PatchSet: 3 Gerrit-Owner: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Attention: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Comment-Date: Tue, 02 Feb 2021 11:08:22 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

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Change in coreboot[master]: device/device.c: Print done at end of assign_resources()
by Angel Pons (Code Review) 02 Feb '21

02 Feb '21

Attention is currently required from: Frans Hendriks, Wim Vervoorn. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50189 ) Change subject: device/device.c: Print done at end of assign_resources() ...................................................................... Patch Set 1: Code-Review+2 (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/50189/comment/9bd5899a_73c5b4d2 PS1, Line 9: report log the https://review.coreboot.org/c/coreboot/+/50189/comment/4de6a6b0_e93dd290 PS1, Line 10: nit: empty line not needed -- To view, visit https://review.coreboot.org/c/coreboot/+/50189 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I66a64c7473a65206c3a4c4396c8c8ecba1eb1a57 Gerrit-Change-Number: 50189 Gerrit-PatchSet: 1 Gerrit-Owner: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Wim Vervoorn <wvervoorn(a)eltan.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Attention: Wim Vervoorn <wvervoorn(a)eltan.com> Gerrit-Comment-Date: Tue, 02 Feb 2021 11:07:06 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/guybrush: First pass GPIO configuriation for Guybrush
by Angel Pons (Code Review) 02 Feb '21

02 Feb '21

Attention is currently required from: Furquan Shaikh, Mathew King. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50091 ) Change subject: mb/google/guybrush: First pass GPIO configuriation for Guybrush ...................................................................... Patch Set 5: (2 comments) File src/mainboard/google/guybrush/variants/baseboard/gpio.c: https://review.coreboot.org/c/coreboot/+/50091/comment/79df96de_be69f872 PS5, Line 10: /* PWR_BTN_L */ > Yes they will be updated when I do my next GPIO pass and will match the net names when enabled. Aaah! Makes sense, then. Would placing the (future) net names in the same line as the GPIO config be easier to read? PAD_NF(GPIO_1, SYS_RESET_L, PULL_NONE), /* SYS_RESET_L */ PAD_NF(GPIO_2, WAKE_L, PULL_NONE), /* WAKE_L */ PAD_NC(GPIO_3), /* AGPIO3 */ PAD_NC(GPIO_4), /* AGPIO4 */ https://review.coreboot.org/c/coreboot/+/50091/comment/574331ed_65d0da42 PS5, Line 80: /* AGPIO69 */ : PAD_NC(GPIO_69), : /* EGPIO70 */ : PAD_NC(GPIO_70), > This is how AMD refers to these gpios. […] Understood, thanks! -- To view, visit https://review.coreboot.org/c/coreboot/+/50091 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia8211dbc3de09a61f264a0e5d44d1eac703b83c9 Gerrit-Change-Number: 50091 Gerrit-PatchSet: 5 Gerrit-Owner: Mathew King <mathewk(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-CC: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Mathew King <mathewk(a)chromium.org> Gerrit-Comment-Date: Tue, 02 Feb 2021 11:02:13 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Mathew King <mathewk(a)chromium.org> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

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Change in coreboot[master]: vc/intel/fsp/fsp2_0/alderlake: Update FSP header file version to 2037
by Angel Pons (Code Review) 02 Feb '21

02 Feb '21

Attention is currently required from: Furquan Shaikh, Tim Wawrzynczak, Subrata Banik, Patrick Rudolph. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49382 ) Change subject: vc/intel/fsp/fsp2_0/alderlake: Update FSP header file version to 2037 ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/49382 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I808cf619f43e629c6150726f2aa29e732e05fc33 Gerrit-Change-Number: 49382 Gerrit-PatchSet: 2 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Tue, 02 Feb 2021 10:55:09 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/intel/shadowmountain: Add bootblock and verstage code
by Angel Pons (Code Review) 02 Feb '21

02 Feb '21

Attention is currently required from: V Sowmya, Martin Roth, Tim Wawrzynczak, Sugnan Prabhu S, Balaji Manigandan, Aamir Bohra. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49479 ) Change subject: mb/intel/shadowmountain: Add bootblock and verstage code ...................................................................... Patch Set 6: (1 comment) File src/mainboard/intel/shadowmountain/Kconfig: https://review.coreboot.org/c/coreboot/+/49479/comment/f5f8ca7a_4a064b6b PS5, Line 24: default y > @Angel, I tried building for !chromeos also (https://review.coreboot. […] Selecting it is even worse: now CHROMEOS can never be disabled... -- To view, visit https://review.coreboot.org/c/coreboot/+/49479 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5f805baf42203306ff10e91a258d9117dd986c4a Gerrit-Change-Number: 49479 Gerrit-PatchSet: 6 Gerrit-Owner: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Sugnan Prabhu S <sugnan.prabhu.s(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Attention: V Sowmya <v.sowmya(a)intel.com> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Sugnan Prabhu S <sugnan.prabhu.s(a)intel.com> Gerrit-Attention: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Attention: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Comment-Date: Tue, 02 Feb 2021 10:46:30 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: V Sowmya <v.sowmya(a)intel.com> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/alderlake: Add support for external clock buffer
by Angel Pons (Code Review) 02 Feb '21

02 Feb '21

Attention is currently required from: Furquan Shaikh, Tim Wawrzynczak, Subrata Banik, Patrick Rudolph, EricR Lai. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50162 ) Change subject: soc/intel/alderlake: Add support for external clock buffer ...................................................................... Patch Set 1: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/50162/comment/2a741d67_84680289 PS1, Line 9: 3 CLKSRC using external clock buffer. : CLKSRC 6 provides feed clock to discrete buffer for further : distribution to platform. > @Furquan, you can looks into 2 things […] Hmmm... If I understand correctly, these SRCCLK_OE#7-9 signals are outputs from ADL-P and are routed to input pins on the external clock buffer chip. And these signals allow the ADL-P iSClk to control the CLKSRC outputs on the external clock chip. Thus, we can think of the external clock buffer chip as an extension of the PCH iSClk, and we have to tell FSP about it. If the previous paragraph is true, then we can simply treat the CLKSRCs from the external clock buffer chip as if they came out of the PCH. I would adapt the Kconfig options as follows: config PCIE_GEN3_EXTERNAL_CLOCK_BUFFER def_bool n depends on !SOC_INTEL_ALDERLAKE_PCH_M help Mainboard has an external PCIe Gen3 clock chip for ADL-P. SRC 6 provides feed clock to discrete buffer for further distribution to platform. config MAX_PCIE_CLOCK_SRC int default 10 if PCIE_GEN3_EXTERNAL_CLOCK_BUFFER default 6 if SOC_INTEL_ALDERLAKE_PCH_M default 7 config MAX_PCIE_CLOCK_REQ int default 10 if PCIE_GEN3_EXTERNAL_CLOCK_BUFFER default 6 if SOC_INTEL_ALDERLAKE_PCH_M default 7 -- To view, visit https://review.coreboot.org/c/coreboot/+/50162 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If49d756ed47d577fd839516d4e707563700453d2 Gerrit-Change-Number: 50162 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Comment-Date: Tue, 02 Feb 2021 10:45:18 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Furquan Shaikh <furquan(a)google.com> Comment-In-Reply-To: Subrata Banik <subrata.banik(a)intel.com> Gerrit-MessageType: comment

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coreboot-gerrit February 2021