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Change subject: soc/amd/common: Drop ACPIMMIO bank for SMBus device PCI config
......................................................................
Patch Set 9:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/42685/comment/3ad80935_00ae537b
PS9, Line 12: we execute had control over the UART configuration...
Felix, can you write a suitable commit message?
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Change subject: soc/amd/common: Refactor single GPIO programming
......................................................................
Patch Set 14: Code-Review+1
(1 comment)
File src/soc/amd/common/block/gpio_banks/gpio.c:
https://review.coreboot.org/c/coreboot/+/42691/comment/c843939f_c34af16c
PS14, Line 184: g
> There's a bunch of abandoned stuff and Felix noted he might want some of that restored. […]
I agree, this is something we can change afterwards
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Change subject: soc/intel/cannonlake: Configure GPIOs again after FSP-S is done
......................................................................
Patch Set 5:
(1 comment)
Patchset:
PS5:
> Ugh.. I think it would be better to have FSP<->coreboot work in a more synchronized fashion than having to actively prevent what the other is doing.
Well, tell that Intel... I too don't like to have to hack around FSP but Intel doesn't really care in many cases it seems.
> Locking down the padcfg will lead to other side-effects as well -- payloads, OS would run into issues trying to reconfigure pads, which won't be acceptable.
Padcfg gets locked down by FSP anyways before any payload / OS starts.
> Are you seeing cases where the FSP is still configuring GPIOs it should not?
Well, as already mentioned, see CB:45211. All these UPDs will change pad config.
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Change subject: soc/amd/common: Refactor single GPIO programming
......................................................................
Patch Set 14:
(2 comments)
File src/soc/amd/common/block/gpio_banks/gpio.c:
https://review.coreboot.org/c/coreboot/+/42691/comment/56b2a59f_44a2e333
PS5, Line 214: GPIO_SPECIAL_FLAG
> That's the original uncommented code.
Ack
File src/soc/amd/common/block/gpio_banks/gpio.c:
https://review.coreboot.org/c/coreboot/+/42691/comment/3b60e7ed_ad427f4d
PS14, Line 184: g
> Can we name it gpio? I only like single character variables names for loop variables.
There's a bunch of abandoned stuff and Felix noted he might want some of that restored. I am not going to go thru the manual rebase trouble to change this. Feel free to do it afterwards.
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Change subject: mb/clevo/cml-u/bootblock.c: Remove unused includes
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Patch Set 1: Code-Review+2
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Change subject: mb/amd/{parmer,thatcher}/bootblock.c: Remove unused includes
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Patch Set 1: Code-Review+2
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Change subject: soc/amd/cezanne: pass MMCONF base address to FSP via UPD
......................................................................
Patch Set 1:
(1 comment)
Patchset:
PS1:
> Any reason not to just copy all the fields over to the header file? The struct will not match in FS […]
i try to only add the fields that we really need for now and where I'm reasonably sure that those won't change. since the code will only access the first field and leave the rest of the UPD unchanged, it's ok that only the beginning matches. sure it's not pretty, but just adding the struct from picasso seems less clean to me and will leave us with mismatching fsp and coreboot upd layouts as soon as we're making inompatible changes, which will happen due to moving the dxio descriptors from the fsp-s upds to the fsp-m upds
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Change subject: soc/amd/picasso: Fix copy-paste error in macro definitions
......................................................................
Patch Set 2:
(1 comment)
Patchset:
PS2:
> I'll wait with the +2 until Jason had a chance to have a look as well, but this fix looks correct to […]
I didn't notice it myself, Coverity did 😄
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Change subject: drivers/i2c: sx9310: Use open source variables
......................................................................
Patch Set 1:
(2 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/50210/comment/2aa82f8f_caf9b636
PS1, Line 60:
Signed=off-by line is missing
File 3rdparty/amd_blobs:
PS1:
You will have to do something like this to get rid of the blobs in the commit:
git submodule update --init --checkout
Then rebase your changes.
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Change subject: soc/amd/cezanne: pass MMCONF base address to FSP via UPD
......................................................................
Patch Set 1:
(1 comment)
Patchset:
PS1:
Any reason not to just copy all the fields over to the header file? The struct will not match in FSP if they do not have the same layout.
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