coreboot-gerrit February 2021

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: soc/amd/picasso: clean up and re-sort UPD table
by Felix Held (Code Review) 02 Feb '21

02 Feb '21

Attention is currently required from: Frank Wu, Jason Glenesk, Raul Rangel, Martin Roth, Marshall Dawson, Chris Wang, chris wang, EricR Lai. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50212 ) Change subject: soc/amd/picasso: clean up and re-sort UPD table ...................................................................... Patch Set 6: (1 comment) File src/mainboard/google/zork/variants/vilboz/overridetree.cb: https://review.coreboot.org/c/coreboot/+/50212/comment/c1ce3b99_96abd93a PS3, Line 34: .margin_deemph = 0x00CC, > that should be typo. […] ok -- To view, visit https://review.coreboot.org/c/coreboot/+/50212 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I655af08e2f86398d088e30d330f49e71cf7e1275 Gerrit-Change-Number: 50212 Gerrit-PatchSet: 6 Gerrit-Owner: chris wang <Chris.Wang(a)amd.com> Gerrit-Reviewer: Chris Wang <chris.wang(a)amd.corp-partner.google.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Frank Wu <frank_wu(a)compal.corp-partner.google.com> Gerrit-CC: John Su <john_su(a)compal.corp-partner.google.com> Gerrit-Attention: Frank Wu <frank_wu(a)compal.corp-partner.google.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Chris Wang <chris.wang(a)amd.corp-partner.google.com> Gerrit-Attention: chris wang <Chris.Wang(a)amd.com> Gerrit-Attention: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Comment-Date: Tue, 02 Feb 2021 23:48:46 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: chris wang <Chris.Wang(a)amd.com> Comment-In-Reply-To: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Comment-In-Reply-To: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/amd/picasso/pcie_gpe: use PICM instead of PMOD in APCI code
by Felix Held (Code Review) 02 Feb '21

02 Feb '21

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/50207 ) Change subject: soc/amd/picasso/pcie_gpe: use PICM instead of PMOD in APCI code ...................................................................... soc/amd/picasso/pcie_gpe: use PICM instead of PMOD in APCI code commit 3f2467032e3e40cd456d2d9fe5120a60283784aa changed this in the APCI code itself, but the change in the ACPI byte code generation in pcie_gpp.c was missed and this patch fixes that. TEST=Fixes the regression on Mandolin. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I60de29581296101947336f70343d6206af97e307 Reviewed-on: https://review.coreboot.org/c/coreboot/+/50207 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Reviewed-by: Raul Rangel <rrangel(a)chromium.org> --- M src/soc/amd/picasso/pcie_gpp.c 1 file changed, 3 insertions(+), 3 deletions(-) Approvals: build bot (Jenkins): Verified Kyösti Mälkki: Looks good to me, approved Raul Rangel: Looks good to me, approved diff --git a/src/soc/amd/picasso/pcie_gpp.c b/src/soc/amd/picasso/pcie_gpp.c index 3101eb4..00b32a0 100644 --- a/src/soc/amd/picasso/pcie_gpp.c +++ b/src/soc/amd/picasso/pcie_gpp.c @@ -127,9 +127,9 @@ acpigen_write_method("_PRT", 0); - /* If (PMOD) */ + /* If (PICM) */ acpigen_write_if(); - acpigen_emit_namestring("PMOD"); + acpigen_emit_namestring("PICM"); /* Return (Package{...}) */ acpigen_emit_byte(RETURN_OP); @@ -192,7 +192,7 @@ * * Method (_PRT, 0, NotSerialized) // _PRT: PCI Routing Table * { - * If (PMOD) + * If (PICM) * { * Return (Package (0x04) * { -- To view, visit https://review.coreboot.org/c/coreboot/+/50207 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I60de29581296101947336f70343d6206af97e307 Gerrit-Change-Number: 50207 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/amd/common: Drop ACPIMMIO bank for SMBus device PCI config
by Felix Held (Code Review) 02 Feb '21

02 Feb '21

Attention is currently required from: Raul Rangel, Kyösti Mälkki. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42685 ) Change subject: soc/amd/common: Drop ACPIMMIO bank for SMBus device PCI config ...................................................................... Patch Set 9: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/42685/comment/9a08fc07_1afd150e PS9, Line 12: we execute had control over the UART configuration... > Felix, can you write a suitable commit message? I'll try to look into it. we might still need the ~1.8MHz option for early linux console (normal linux console uses the right base clock, but the early console assumes the legacy base clock value) and in that case it might be useful to keep this around. i'm not sure what the best approach would be here and i'm not sure when i have time to really get to the bottom of this issue -- To view, visit https://review.coreboot.org/c/coreboot/+/42685 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5c8ce8de0a6ab0ed41e7e8a5980d0f0510aaa993 Gerrit-Change-Number: 42685 Gerrit-PatchSet: 9 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-CC: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Comment-Date: Tue, 02 Feb 2021 23:45:00 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: comment

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Change in coreboot[master]: amd/common/block/acpi/pm_state: fix comparison in get_index_bit
by Raul Rangel (Code Review) 02 Feb '21

02 Feb '21

Attention is currently required from: Jason Glenesk, Marshall Dawson, Felix Held. Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50243 ) Change subject: amd/common/block/acpi/pm_state: fix comparison in get_index_bit ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/50243 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6ca341841bad62abcb4ea26a350c539813a29de7 Gerrit-Change-Number: 50243 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Tue, 02 Feb 2021 23:42:57 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/amd/picasso: set GPE0_LIMIT to 32 and move definitions to registers
by Raul Rangel (Code Review) 02 Feb '21

02 Feb '21

Attention is currently required from: Jason Glenesk, Marshall Dawson, Felix Held. Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50244 ) Change subject: soc/amd/picasso: set GPE0_LIMIT to 32 and move definitions to registers ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/50244 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia156e64e7a69764776f3af7597b680b8ddd4e650 Gerrit-Change-Number: 50244 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Tue, 02 Feb 2021 23:42:51 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/amd/picasso: set GPE0_LIMIT to 32 and move definitions to registers
by Felix Held (Code Review) 02 Feb '21

02 Feb '21

Attention is currently required from: Jason Glenesk, Raul Rangel, Marshall Dawson. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50244 ) Change subject: soc/amd/picasso: set GPE0_LIMIT to 32 and move definitions to registers ...................................................................... Patch Set 2: (1 comment) File src/soc/amd/picasso/include/soc/southbridge.h: https://review.coreboot.org/c/coreboot/+/50244/comment/fdfde38a_1a20018a PS2, Line 79: 32 > Where in the datasheet did you find this? see FCH::PM::EventStat and FCH::PM::EventEnable in the PPR #55570. No idea where the 28 is from; it just got copied over from Stoneyridge -- To view, visit https://review.coreboot.org/c/coreboot/+/50244 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia156e64e7a69764776f3af7597b680b8ddd4e650 Gerrit-Change-Number: 50244 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Comment-Date: Tue, 02 Feb 2021 23:37:23 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Raul Rangel <rrangel(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: amdfwtool:cezanne: Add entry of PSP_BOOTLOADER_AB (0x73)
by Felix Held (Code Review) 02 Feb '21

02 Feb '21

Attention is currently required from: Bao Zheng, Jason Glenesk, Raul Rangel, Marshall Dawson, Zheng Bao. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50227 ) Change subject: amdfwtool:cezanne: Add entry of PSP_BOOTLOADER_AB (0x73) ...................................................................... Patch Set 1: Code-Review+2 (1 comment) Patchset: PS1: looks good to me and i verified that both Majolica and Mandolin still work -- To view, visit https://review.coreboot.org/c/coreboot/+/50227 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie3577b403c1de7f20b6d5bcf9e1a5d47450266fe Gerrit-Change-Number: 50227 Gerrit-PatchSet: 1 Gerrit-Owner: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Zheng Bao Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Zheng Bao Gerrit-Comment-Date: Tue, 02 Feb 2021 23:30:25 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/amd/picasso: set GPE0_LIMIT to 32 and move definitions to registers
by Raul Rangel (Code Review) 02 Feb '21

02 Feb '21

Attention is currently required from: Jason Glenesk, Marshall Dawson, Felix Held. Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50244 ) Change subject: soc/amd/picasso: set GPE0_LIMIT to 32 and move definitions to registers ...................................................................... Patch Set 2: (1 comment) File src/soc/amd/picasso/include/soc/southbridge.h: https://review.coreboot.org/c/coreboot/+/50244/comment/9837d277_0f6d9833 PS2, Line 79: 32 Where in the datasheet did you find this? -- To view, visit https://review.coreboot.org/c/coreboot/+/50244 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia156e64e7a69764776f3af7597b680b8ddd4e650 Gerrit-Change-Number: 50244 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Tue, 02 Feb 2021 23:05:55 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: vendorcode/amd/fsp/cezanne: add UPD structs from FSP build
by Justin Frodsham (Code Review) 02 Feb '21

02 Feb '21

Attention is currently required from: Raul Rangel, Justin Frodsham, Felix Held. Justin Frodsham has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50242 ) Change subject: vendorcode/amd/fsp/cezanne: add UPD structs from FSP build ...................................................................... Patch Set 1: (1 comment) File src/vendorcode/amd/fsp/cezanne/FspmUpd.h: https://review.coreboot.org/c/coreboot/+/50242/comment/1c2c9782_d9b3ca1e PS1, Line 19: /** Offset 0x0050**/ uint32_t serial_port_baudrate; : /** Offset 0x0054**/ uint32_t serial_port_refclk; > I'm assuming FSP-M is reconfiguring the UART? Could we make it not do that? This is a WIP, if we don't line up the structures, we can't get very far in post. We will be pruning all this down. -- To view, visit https://review.coreboot.org/c/coreboot/+/50242 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icade1d7bcab7b85cdd25c4114590eb23b914edcd Gerrit-Change-Number: 50242 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Justin Frodsham <justin.frodsham(a)amd.corp-partner.google.com> Gerrit-Reviewer: Justin Frodsham <justin.frodsham(a)protonmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Justin Frodsham <justin.frodsham(a)protonmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Tue, 02 Feb 2021 22:57:17 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Raul Rangel <rrangel(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/amd/picasso/include/soc/southbridge: remove PM_USB_ENABLE defines
by Felix Held (Code Review) 02 Feb '21

02 Feb '21

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/50205 ) Change subject: soc/amd/picasso/include/soc/southbridge: remove PM_USB_ENABLE defines ...................................................................... soc/amd/picasso/include/soc/southbridge: remove PM_USB_ENABLE defines This define was copied over from Stoneyridge, but isn't present on Picasso and newer. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: Ideb144c4bff441cf043a647b3f44a65691038eba Reviewed-on: https://review.coreboot.org/c/coreboot/+/50205 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Raul Rangel <rrangel(a)chromium.org> --- M src/soc/amd/picasso/include/soc/southbridge.h 1 file changed, 0 insertions(+), 2 deletions(-) Approvals: build bot (Jenkins): Verified Raul Rangel: Looks good to me, approved diff --git a/src/soc/amd/picasso/include/soc/southbridge.h b/src/soc/amd/picasso/include/soc/southbridge.h index f7edaad..d45c3b0 100644 --- a/src/soc/amd/picasso/include/soc/southbridge.h +++ b/src/soc/amd/picasso/include/soc/southbridge.h @@ -74,8 +74,6 @@ #define PM_LPC_AB_NO_BYPASS_EN BIT(2) #define PM_LPC_A20_EN BIT(1) #define PM_LPC_ENABLE BIT(0) -#define PM_USB_ENABLE 0xef -#define PM_USB_ALL_CONTROLLERS 0x7f /* FCH MISC Registers 0xfed80e00 */ #define GPP_CLK_CNTRL 0x00 -- To view, visit https://review.coreboot.org/c/coreboot/+/50205 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ideb144c4bff441cf043a647b3f44a65691038eba Gerrit-Change-Number: 50205 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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coreboot-gerrit February 2021