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Change subject: mb/google/volteer: update thermal table for Eldrid
......................................................................
Patch Set 2:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/50111/comment/fa3540cb_ecbc7784
PS1, Line 14: Signed-off-by: Nick Chen <nick_xr_chen(a)wistron.corp-partner.google.com>
> Missing "TEST=" field.
Done
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Change subject: Fix tsc_freq_mhz() on some platforms
......................................................................
Patch Set 1:
(2 comments)
File src/soc/intel/common/block/timer/timer.c:
https://review.coreboot.org/c/coreboot/+/49232/comment/21383516_624d0212
PS1, Line 57: if (cpuid_get_max_func() < 0x15)
: return 0;
Drop this since the caller now performs this check?
https://review.coreboot.org/c/coreboot/+/49232/comment/798bf29d_8b33b6f4
PS1, Line 113: platform_info = rdmsr(MSR_PLATFORM_INFO);
: return CONFIG_CPU_BCLK_MHZ * ((platform_info.lo >> 8) & 0xff);
Is this true for all x86 models? Or does there need to be a model check? Some older models I think reported using MSR_IA32_PERF_STATUS? Not sure if we care about those here?
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Change subject: mb/google/volteer: update thermal table for Eldrid
......................................................................
Patch Set 1: Code-Review+1
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/50111/comment/2c2b0657_e398defc
PS1, Line 14: Signed-off-by: Nick Chen <nick_xr_chen(a)wistron.corp-partner.google.com>
Missing "TEST=" field.
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Change subject: mb/google/volteer: update thermal table for Eldrid
......................................................................
Patch Set 1:
(1 comment)
File src/mainboard/google/volteer/variants/eldrid/overridetree.cb:
https://review.coreboot.org/c/coreboot/+/50111/comment/9b13e501_f692d93f
PS1, Line 104: 60.8
> This will turn into `60` (it's an unsigned int type), did you mean 60?
I mean 60.8 but turn into 60 is ok.
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Change subject: mb/ocp/deltalake: Implement skipping TXT lockdown via VPD
......................................................................
Patch Set 1:
(1 comment)
File src/mainboard/ocp/deltalake/ramstage.c:
https://review.coreboot.org/c/coreboot/+/50237/comment/6ad1ff1c_123ddcd9
PS1, Line 368: static bool fetched_vpd = 0;
> Do you really need to cache this? The function is only called once
The follow-up patch does ;)
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Change subject: mb/google/volteer/var/voema: Enable EEPROM for OV2740
......................................................................
Patch Set 1:
(1 comment)
Patchset:
PS1:
Thanks Tim and Jim.
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Change subject: include/cbfs.h: Add comment for chain-includes of commonlib
......................................................................
Patch Set 4:
(1 comment)
Patchset:
PS4:
> I mean, FWI
(stupid Gerrit submitting half-written comments after I already clicked Cancel...)
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Change subject: include/cbfs.h: Add comment for chain-includes of commonlib
......................................................................
Patch Set 4:
(2 comments)
Patchset:
PS4:
> I am tempted to -2 works on indirect includes until something appears under Documentation/.
I've drafted an addition to the coding style as CB:50247 (it currently doesn't say anything about includes, FWIW), let me know what you think.
PS4:
I mean, FWI
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Hello Patrick Georgi, Martin Roth, Kyösti Mälkki, HAOUAS Elyes,
I'd like you to do a code review. Please visit
https://review.coreboot.org/c/coreboot/+/50247
to review the following change.
Change subject: Documentation: Codify some guidelines for headers and chain-including
......................................................................
Documentation: Codify some guidelines for headers and chain-including
There has been some repeated discussion about how header includes should
be formatted, specifically on the topic of chain-including. The coding
style currently doesn't say anything about the topic but clearly people
have some basic assumptions. This patch tries to codify some common
ground rules that are supposed to reflect the existing practice.
Signed-off-by: Julius Werner <jwerner(a)chromium.org>
Change-Id: Ibbcde306a814f52b3a41b58c7a33bdd99b0187e0
---
M Documentation/coding_style.md
1 file changed, 39 insertions(+), 10 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/47/50247/1
diff --git a/Documentation/coding_style.md b/Documentation/coding_style.md
index ac0de4e..ca45096 100644
--- a/Documentation/coding_style.md
+++ b/Documentation/coding_style.md
@@ -834,22 +834,51 @@
out-of-range result. Typical examples would be functions that return
pointers; they use NULL or the ERR_PTR mechanism to report failure.
-Don't re-invent the kernel macros
-----------------------------------
+Headers and includes
+---------------
-The header file include/linux/kernel.h contains a number of macros that
-you should use, rather than explicitly coding some variant of them
-yourself. For example, if you need to calculate the length of an array,
-take advantage of the macro
+Headers should always be included at the top of the file, preferrably in
+alphabetical order. Includes should always use the `#include <file.h>`
+notation, except for rare cases where a file in the same directory that
+is not part of a normal include path gets included (e.g. local headers
+in mainboard directories), which should use `#include "file.h"`. Headers
+that can be included from both assembly files and .c files should keep
+all C code wrapped in `#ifndef __ASSEMBLER__` blocks, including includes
+to other headers that don't follow that provision.
+
+Files should generally include every header they need a definition from
+directly (and not include any unnecessary extra headers). Excepted from
+this are certain headers that intentionally chain-include other headers
+which logically belong to them and are just factored out into a separate
+location for implementation or organizatory reasons. This could be
+because part of the definitions is generic and part SoC-specific (e.g.
+`<gpio.h>` chain-including `<soc/gpio.h>`), architecture-specific (e.g.
+`<device/mmio.h>` chain-including `<arch/mmio.h>`), separated out into
+commonlib[/bsd] for sharing/license reasons (e.g. `<cbfs.h>`
+chain-including `<commonlib/bsd/cbfs_serialized.h>`) or just split out
+to make organizing subunits of a larger header easier. This can also
+happen when certain definitions need to be in a specific header for
+legacy POSIX reasons but we would like to logically group them together
+(e.g. `uintptr_t` is in `<stdint.h>` and `size_t` in `<stddef.h>`, but
+it's nicer to be able to just include `<types.h>` and get all the common
+type and helper function stuff we need everywhere).
+
+The headers `<kconfig.h>`, `<rules.h>` and `<commonlib/bsd/compiler.h>`
+are always automatically included in all compilation units by the build
+system and should not be included manually.
+
+Don't re-invent common macros
+-----------------------------
+
+The header file `src/commonlib/bsd/include/commonlib/bsd/helpers.h`
+contains a number of macros that you should use, rather than explicitly
+coding some variant of them yourself. For example, if you need to
+calculate the length of an array, take advantage of the macro
```c
#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
```
-There are also min() and max() macros that do strict type checking if
-you need them. Feel free to peruse that header file to see what else is
-already defined that you shouldn't reproduce in your code.
-
Editor modelines and other cruft
--------------------------------
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Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50239 )
Change subject: soc/amd/cezanne: populate some FSP-M UPDs
......................................................................
Patch Set 2:
(1 comment)
File src/soc/amd/cezanne/romstage.c:
https://review.coreboot.org/c/coreboot/+/50239/comment/9ff890b5_2e96b62b
PS2, Line 19: 1
> Cezanne doesn't support a stride of 1 though. […]
ah, DRIVERS_UART_8250MEM and DRIVERS_UART_8250MEM_32 only get selected together, so this is indeed for the support of legacy i/o mapped uarts
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