coreboot-gerrit February 2021

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Change in coreboot[master]: soc/intel/skylake: Convert to ASL 2.0 syntax
by HAOUAS Elyes (Code Review) 10 Feb '21

10 Feb '21

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46242 ) Change subject: soc/intel/skylake: Convert to ASL 2.0 syntax ...................................................................... soc/intel/skylake: Convert to ASL 2.0 syntax Change-Id: Iea915b60d8ec9a1a7a2aa5926b0277cae58113a6 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/soc/intel/skylake/acpi/dptf/charger.asl M src/soc/intel/skylake/acpi/dptf/cpu.asl M src/soc/intel/skylake/acpi/dptf/dptf.asl M src/soc/intel/skylake/acpi/dptf/fan.asl M src/soc/intel/skylake/acpi/dptf/thermal.asl M src/soc/intel/skylake/acpi/globalnvs.asl M src/soc/intel/skylake/acpi/irqlinks.asl M src/soc/intel/skylake/acpi/pch.asl M src/soc/intel/skylake/acpi/pch_hda.asl M src/soc/intel/skylake/acpi/scs.asl M src/soc/intel/skylake/acpi/xhci.asl 11 files changed, 134 insertions(+), 138 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/42/46242/1 diff --git a/src/soc/intel/skylake/acpi/dptf/charger.asl b/src/soc/intel/skylake/acpi/dptf/charger.asl index fca9590..97c8355 100644 --- a/src/soc/intel/skylake/acpi/dptf/charger.asl +++ b/src/soc/intel/skylake/acpi/dptf/charger.asl @@ -9,7 +9,7 @@ Method (_STA) { - If (LEqual (\DPTE, One)) { + If (\DPTE == 1) { Return (0xF) } Else { Return (0x0) @@ -26,11 +26,11 @@ Method (PPPC) { /* Convert size of PPSS table to index */ - Store (SizeOf (\_SB.CHPS), Local0) - Decrement (Local0) + Local0 = SizeOf (\_SB.CHPS) + Local0-- /* Check if charging is disabled (AC removed) */ - If (LEqual (\_SB.PCI0.LPCB.EC0.ACEX, Zero)) { + If (\_SB.PCI0.LPCB.EC0.ACEX == 0) { /* Return last power state */ Return (Local0) } Else { @@ -45,8 +45,7 @@ Method (SPPC, 1) { /* Retrieve Control (index 4) for specified PPSS level */ - Store (DeRefOf (Index (DeRefOf (Index - (\_SB.CHPS, ToInteger (Arg0))), 4)), Local0) + Local0 = DeRefOf (DeRefOf (\_SB.CHPS [ToInteger (Arg0)]) [4]) /* Pass Control value to EC to limit charging */ \_SB.PCI0.LPCB.EC0.CHGS (Local0) diff --git a/src/soc/intel/skylake/acpi/dptf/cpu.asl b/src/soc/intel/skylake/acpi/dptf/cpu.asl index 9931f6c..181b01a 100644 --- a/src/soc/intel/skylake/acpi/dptf/cpu.asl +++ b/src/soc/intel/skylake/acpi/dptf/cpu.asl @@ -17,7 +17,7 @@ Method (_STA) { - If (LEqual (\DPTE, One)) { + If (\DPTE == 1) { Return (0xF) } Else { Return (0x0) @@ -35,7 +35,7 @@ Method (SPPC, 1) { - Store (Arg0, \PPCM) + \PPCM = Arg0 /* Notify OS to re-read _PPC limit on each CPU */ \PPCN () @@ -60,8 +60,8 @@ If (CondRefOf (\_SB.MPDL)) { Return (\_SB.MPDL) } ElseIf (CondRefOf (\_SB.CP00._PSS)) { - Store (SizeOf (\_SB.CP00._PSS), Local0) - Decrement (Local0) + Local0 = SizeOf (\_SB.CP00._PSS) + Local0-- Return (Local0) } Else { Return (0) diff --git a/src/soc/intel/skylake/acpi/dptf/dptf.asl b/src/soc/intel/skylake/acpi/dptf/dptf.asl index 8852e0a..e72437a 100644 --- a/src/soc/intel/skylake/acpi/dptf/dptf.asl +++ b/src/soc/intel/skylake/acpi/dptf/dptf.asl @@ -24,7 +24,7 @@ Method (_STA) { - If (LEqual (\DPTE, One)) { + If (\DPTE == 1) { Return (0xF) } Else { Return (0x0) @@ -41,7 +41,7 @@ Method (_OSC, 4, Serialized) { /* Check for Passive Policy UUID */ - If (LEqual (DeRefOf (Index (IDSP, 0)), Arg0)) { + If (DeRefOf (IDSP [0]) == Arg0) { /* Initialize Thermal Devices */ ^TINI () @@ -73,10 +73,10 @@ /* Convert from Degrees C to 1/10 Kelvin for ACPI */ Method (CTOK, 1) { /* 10th of Degrees C */ - Multiply (Arg0, 10, Local0) + Local0 = Arg0 * 10 /* Convert to Kelvin */ - Add (Local0, 2732, Local0) + Local0 += 2732 Return (Local0) } diff --git a/src/soc/intel/skylake/acpi/dptf/fan.asl b/src/soc/intel/skylake/acpi/dptf/fan.asl index 6d60c63..eb75ba9 100644 --- a/src/soc/intel/skylake/acpi/dptf/fan.asl +++ b/src/soc/intel/skylake/acpi/dptf/fan.asl @@ -32,19 +32,19 @@ Method (_FST, 0, Serialized,,PkgObj) { /* Fill in TFST with current control. */ - Store (\_SB.PCI0.LPCB.EC0.FAND, Index (TFST, 1)) + TFST [1] = \_SB.PCI0.LPCB.EC0.FAND Return (TFST) } /* _FSL: Fan Speed Level */ Method (_FSL, 1, Serialized) { - Store (Arg0, \_SB.PCI0.LPCB.EC0.FAND) + \_SB.PCI0.LPCB.EC0.FAND = Arg0 } Method (_STA) { - If (LEqual (\DPTE, One)) + If (\DPTE == 1) { Return (0xF) } Else { diff --git a/src/soc/intel/skylake/acpi/dptf/thermal.asl b/src/soc/intel/skylake/acpi/dptf/thermal.asl index 3aead2b..95912a4 100644 --- a/src/soc/intel/skylake/acpi/dptf/thermal.asl +++ b/src/soc/intel/skylake/acpi/dptf/thermal.asl @@ -8,22 +8,22 @@ { #ifdef DPTF_TSR0_SENSOR_ID - If (LEqual (ToInteger (Arg0), DPTF_TSR0_SENSOR_ID)) { + If (ToInteger (Arg0) == DPTF_TSR0_SENSOR_ID) { Notify (^TSR0, 0x90) } #endif #ifdef DPTF_TSR1_SENSOR_ID - If (LEqual (ToInteger (Arg0), DPTF_TSR1_SENSOR_ID)) { + If (ToInteger (Arg0) == DPTF_TSR1_SENSOR_ID) { Notify (^TSR1, 0x90) } #endif #ifdef DPTF_TSR2_SENSOR_ID - If (LEqual (ToInteger (Arg0), DPTF_TSR2_SENSOR_ID)) { + If (ToInteger (Arg0) == DPTF_TSR2_SENSOR_ID) { Notify (^TSR2, 0x90) } #endif #ifdef DPTF_TSR3_SENSOR_ID - If (LEqual (ToInteger (Arg0), DPTF_TSR3_SENSOR_ID)) { + If (ToInteger (Arg0) == DPTF_TSR3_SENSOR_ID) { Notify (^TSR3, 0x90) } #endif @@ -78,7 +78,7 @@ Method (DTRP, 2, Serialized) { If (CondRefOf (\_SB.PCI0.LPCB.EC0.RCDP)) { - If (LEqual (\_SB.PCI0.LPCB.EC0.RCDP, One)) { + If (\_SB.PCI0.LPCB.EC0.RCDP == 1) { Return (CTOK (Arg0)) } } @@ -106,7 +106,7 @@ Method (_STA) { - If (LEqual (\DPTE, One)) { + If (\DPTE == 1) { Return (0xF) } Else { Return (0x0) @@ -215,7 +215,7 @@ Method (_STA) { - If (LEqual (\DPTE, One)) { + If (\DPTE == 1) { Return (0xF) } Else { Return (0x0) @@ -312,7 +312,7 @@ Method (_STA) { - If (LEqual (\DPTE, One)) { + If (\DPTE == 1) { Return (0xF) } Else { Return (0x0) @@ -376,7 +376,7 @@ Method (_STA) { - If (LEqual (\DPTE, One)) { + If (\DPTE == 1) { Return (0xF) } Else { Return (0x0) diff --git a/src/soc/intel/skylake/acpi/globalnvs.asl b/src/soc/intel/skylake/acpi/globalnvs.asl index abcde94..de1c026 100644 --- a/src/soc/intel/skylake/acpi/globalnvs.asl +++ b/src/soc/intel/skylake/acpi/globalnvs.asl @@ -66,23 +66,23 @@ /* Set flag to enable USB charging in S3 */ Method (S3UE) { - Store (One, \S3U0) + \S3U0 = 1 } /* Set flag to disable USB charging in S3 */ Method (S3UD) { - Store (Zero, \S3U0) + \S3U0 = 0 } /* Set flag to enable USB charging in S5 */ Method (S5UE) { - Store (One, \S5U0) + \S5U0 = 1 } /* Set flag to disable USB charging in S5 */ Method (S5UD) { - Store (Zero, \S5U0) + \S5U0 = 0 } diff --git a/src/soc/intel/skylake/acpi/irqlinks.asl b/src/soc/intel/skylake/acpi/irqlinks.asl index da82523..31fea42 100644 --- a/src/soc/intel/skylake/acpi/irqlinks.asl +++ b/src/soc/intel/skylake/acpi/irqlinks.asl @@ -10,9 +10,8 @@ * https://bugs.acpica.org/show_bug.cgi?id=1201 */ OperationRegion (ITSS, SystemMemory, - Add (PCR_ITSS_PIRQA_ROUT, - Add (CONFIG_PCR_BASE_ADDRESS, - ShiftLeft (PID_ITSS, PCR_PORTID_SHIFT))), 8) + PCR_ITSS_PIRQA_ROUT + CONFIG_PCR_BASE_ADDRESS + (PID_ITSS << PCR_PORTID_SHIFT), + 8) Field (ITSS, ByteAcc, NoLock, Preserve) { PIRA, 8, /* PIRQA Routing Control */ @@ -46,10 +45,10 @@ IRQ (Level, ActiveLow, Shared) {} }) CreateWordField (RTLA, 1, IRQ0) - Store (Zero, IRQ0) + IRQ0 = 0 /* Set the bit from PIRQ Routing Register */ - ShiftLeft (1, And (^^PIRA, ^^IREM), IRQ0) + IRQ0 = 1 << (^^PIRA & ^^IREM) Return (RTLA) } @@ -58,13 +57,13 @@ { CreateWordField (Arg0, 1, IRQ0) FindSetRightBit (IRQ0, Local0) - Decrement (Local0) - Store (Local0, ^^PIRA) + Local0-- + ^^PIRA = Local0 } Method (_STA, 0, Serialized) { - If (And (^^PIRA, ^^IREN)) { + If (^^PIRA & ^^IREN) { Return (0x9) } Else { Return (0xb) @@ -73,7 +72,7 @@ Method (_DIS, 0, Serialized) { - Or (^^PIRA, ^^IREN, ^^PIRA) + ^^PIRA |= ^^IREN } } @@ -95,10 +94,10 @@ IRQ (Level, ActiveLow, Shared) {} }) CreateWordField (RTLA, 1, IRQ0) - Store (Zero, IRQ0) + IRQ0 = 0 /* Set the bit from PIRQ Routing Register */ - ShiftLeft (1, And (^^PIRB, ^^IREM), IRQ0) + IRQ0 = 1 << (^^PIRB & ^^IREM) Return (RTLA) } @@ -107,13 +106,13 @@ { CreateWordField (Arg0, 1, IRQ0) FindSetRightBit (IRQ0, Local0) - Decrement (Local0) - Store (Local0, ^^PIRB) + Local0-- + ^^PIRB = Local0 } Method (_STA, 0, Serialized) { - If (And (^^PIRB, ^^IREN)) { + If (^^PIRB & ^^IREN) { Return (0x9) } Else { Return (0xb) @@ -122,7 +121,7 @@ Method (_DIS, 0, Serialized) { - Or (^^PIRB, ^^IREN, ^^PIRB) + ^^PIRB |= ^^IREN } } @@ -144,10 +143,10 @@ IRQ (Level, ActiveLow, Shared) {} }) CreateWordField (RTLA, 1, IRQ0) - Store (Zero, IRQ0) + IRQ0 = 0 /* Set the bit from PIRQ Routing Register */ - ShiftLeft (1, And (^^PIRC, ^^IREM), IRQ0) + IRQ0 = 1 << (^^PIRC & ^^IREM) Return (RTLA) } @@ -156,13 +155,13 @@ { CreateWordField (Arg0, 1, IRQ0) FindSetRightBit (IRQ0, Local0) - Decrement (Local0) - Store (Local0, ^^PIRC) + Local0-- + ^^PIRC = Local0 } Method (_STA, 0, Serialized) { - If (And (^^PIRC, ^^IREN)) { + If (^^PIRC & ^^IREN) { Return (0x9) } Else { Return (0xb) @@ -171,7 +170,7 @@ Method (_DIS, 0, Serialized) { - Or (^^PIRC, ^^IREN, ^^PIRC) + ^^PIRC |= ^^IREN } } @@ -193,10 +192,10 @@ IRQ (Level, ActiveLow, Shared) {} }) CreateWordField (RTLA, 1, IRQ0) - Store (Zero, IRQ0) + IRQ0 = 0 /* Set the bit from PIRQ Routing Register */ - ShiftLeft (1, And (^^PIRD, ^^IREM), IRQ0) + IRQ0 = 1 << (^^PIRD & ^^IREM) Return (RTLA) } @@ -205,13 +204,13 @@ { CreateWordField (Arg0, 1, IRQ0) FindSetRightBit (IRQ0, Local0) - Decrement (Local0) - Store (Local0, ^^PIRD) + Local0-- + ^^PIRD = Local0 } Method (_STA, 0, Serialized) { - If (And (^^PIRD, ^^IREN)) { + If (^^PIRD & ^^IREN) { Return (0x9) } Else { Return (0xb) @@ -220,7 +219,7 @@ Method (_DIS, 0, Serialized) { - Or (^^PIRD, ^^IREN, ^^PIRD) + ^^PIRD |= ^^IREN } } @@ -242,10 +241,10 @@ IRQ (Level, ActiveLow, Shared) {} }) CreateWordField (RTLA, 1, IRQ0) - Store (Zero, IRQ0) + IRQ0 = 0 /* Set the bit from PIRQ Routing Register */ - ShiftLeft (1, And (^^PIRE, ^^IREM), IRQ0) + IRQ0 = 1 << (^^PIRE & ^^IREM) Return (RTLA) } @@ -254,13 +253,13 @@ { CreateWordField (Arg0, 1, IRQ0) FindSetRightBit (IRQ0, Local0) - Decrement (Local0) - Store (Local0, ^^PIRE) + Local0-- + ^^PIRE = Local0 } Method (_STA, 0, Serialized) { - If (And (^^PIRE, ^^IREN)) { + If (^^PIRE & ^^IREN) { Return (0x9) } Else { Return (0xb) @@ -269,7 +268,7 @@ Method (_DIS, 0, Serialized) { - Or (^^PIRE, ^^IREN, ^^PIRE) + ^^PIRE |= ^^IREN } } @@ -291,10 +290,10 @@ IRQ (Level, ActiveLow, Shared) {} }) CreateWordField (RTLA, 1, IRQ0) - Store (Zero, IRQ0) + IRQ0 = 0 /* Set the bit from PIRQ Routing Register */ - ShiftLeft (1, And (^^PIRF, ^^IREM), IRQ0) + IRQ0 = 1 << (^^PIRF & ^^IREM) Return (RTLA) } @@ -303,13 +302,13 @@ { CreateWordField (Arg0, 1, IRQ0) FindSetRightBit (IRQ0, Local0) - Decrement (Local0) - Store (Local0, ^^PIRF) + Local0-- + ^^PIRF = Local0 } Method (_STA, 0, Serialized) { - If (And (^^PIRF, ^^IREN)) { + If (^^PIRF & ^^IREN) { Return (0x9) } Else { Return (0xb) @@ -318,7 +317,7 @@ Method (_DIS, 0, Serialized) { - Or (^^PIRF, ^^IREN, ^^PIRF) + ^^PIRF |= ^^IREN } } @@ -340,10 +339,10 @@ IRQ (Level, ActiveLow, Shared) {} }) CreateWordField (RTLA, 1, IRQ0) - Store (Zero, IRQ0) + IRQ0 = 0 /* Set the bit from PIRQ Routing Register */ - ShiftLeft (1, And (^^PIRG, ^^IREM), IRQ0) + IRQ0 = 1 << (^^PIRG & ^^IREM) Return (RTLA) } @@ -352,13 +351,13 @@ { CreateWordField (Arg0, 1, IRQ0) FindSetRightBit (IRQ0, Local0) - Decrement (Local0) - Store (Local0, ^^PIRG) + Local0-- + ^^PIRG = Local0 } Method (_STA, 0, Serialized) { - If (And (^^PIRG, ^^IREN)) { + If (^^PIRG & ^^IREN) { Return (0x9) } Else { Return (0xb) @@ -367,7 +366,7 @@ Method (_DIS, 0, Serialized) { - Or (^^PIRG, ^^IREN, ^^PIRG) + ^^PIRG |= ^^IREN } } @@ -389,10 +388,10 @@ IRQ (Level, ActiveLow, Shared) {} }) CreateWordField (RTLA, 1, IRQ0) - Store (Zero, IRQ0) + IRQ0 = 0 /* Set the bit from PIRQ Routing Register */ - ShiftLeft (1, And (^^PIRH, ^^IREM), IRQ0) + IRQ0 = 1 << (^^PIRH & ^^IREM) Return (RTLA) } @@ -401,13 +400,13 @@ { CreateWordField (Arg0, 1, IRQ0) FindSetRightBit (IRQ0, Local0) - Decrement (Local0) - Store (Local0, ^^PIRH) + Local0-- + ^^PIRH = Local0 } Method (_STA, 0, Serialized) { - If (And (^^PIRH, ^^IREN)) { + If (^^PIRH & ^^IREN) { Return (0x9) } Else { Return (0xb) @@ -416,6 +415,6 @@ Method (_DIS, 0, Serialized) { - Or (^^PIRH, ^^IREN, ^^PIRH) + ^^PIRH |= ^^IREN } } diff --git a/src/soc/intel/skylake/acpi/pch.asl b/src/soc/intel/skylake/acpi/pch.asl index 6eea5bb..e088ca1 100644 --- a/src/soc/intel/skylake/acpi/pch.asl +++ b/src/soc/intel/skylake/acpi/pch.asl @@ -47,7 +47,7 @@ Method (_OSC, 4) { /* Check for proper GUID */ - If (LEqual (Arg0, ToUUID ("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) + If (Arg0 == ToUUID ("33DB4D5B-1FF7-401C-9657-7441C03DD766")) { /* Let OS control everything */ Return (Arg3) @@ -56,7 +56,7 @@ { /* Unrecognized UUID */ CreateDWordField (Arg3, 0, CDW1) - Or (CDW1, 4, CDW1) + CDW1 |= 4 Return (Arg3) } } diff --git a/src/soc/intel/skylake/acpi/pch_hda.asl b/src/soc/intel/skylake/acpi/pch_hda.asl index 04e974f..3de64b7 100644 --- a/src/soc/intel/skylake/acpi/pch_hda.asl +++ b/src/soc/intel/skylake/acpi/pch_hda.asl @@ -26,19 +26,17 @@ */ Method (_DSM, 4) { - If (LEqual (Arg0, ^UUID)) { + If (Arg0 == ^UUID) { /* * Function 0: Function Support Query * Returns a bitmask of functions supported. */ - If (LEqual (Arg2, Zero)) { + If (Arg2 == 0) { /* * NHLT Query only supported for revision 1 and * if NHLT address and length are set in NVS. */ - If (LAnd (LEqual (Arg1, One), - LAnd (LNotEqual (NHLA, Zero), - LNotEqual (NHLL, Zero)))) { + If ((Arg1 == 1) && (NHLA != 0) && (NHLL != 0)) { Return (Buffer (One) { 0x03 }) } Else { Return (Buffer (One) { 0x01 }) @@ -52,14 +50,14 @@ * * Returns a pointer to NHLT table in memory. */ - If (LEqual (Arg2, One)) { + If (Arg2 == 1) { CreateQWordField (NBUF, ^NHLT._MIN, NBAS) CreateQWordField (NBUF, ^NHLT._MAX, NMAS) CreateQWordField (NBUF, ^NHLT._LEN, NLEN) - Store (NHLA, NBAS) - Store (NHLA, NMAS) - Store (NHLL, NLEN) + NBAS = NHLA + NMAS = NHLA + NLEN = NHLL Return (NBUF) } diff --git a/src/soc/intel/skylake/acpi/scs.asl b/src/soc/intel/skylake/acpi/scs.asl index 356a7e0..2b88706 100644 --- a/src/soc/intel/skylake/acpi/scs.asl +++ b/src/soc/intel/skylake/acpi/scs.asl @@ -27,13 +27,13 @@ */ Method (_DSM, 4) { - If (LEqual (Arg0, ^UUID)) { + If (Arg0 == ^UUID) { /* * Function 9: Device Readiness Durations * Returns a package of five integers covering * various device related delay in PCIe Base Spec. */ - If (LEqual (Arg2, 9)) { + If ((Arg2 == 9) { /* * Function 9 support for revision 3. * ECN link for function definitions @@ -41,7 +41,7 @@ * specification_documents/ * ECN_fw_latency_optimization_final.pdf] */ - If (LEqual (Arg1, 3)) { + If (Arg1 == 3) { /* * Integer 0: FW reset time. * Integer 1: FW data link up time. @@ -64,7 +64,7 @@ Method (_PS0, 0, Serialized) { /* Disable Power Gate */ - Store (0, ^PGEN) + ^PGEN = 0 /* Clear bits 31, 6, 2, 0 */ ^^PCRA (PID_SCS, 0x600, 0x7FFFFFBA) @@ -74,18 +74,18 @@ ^^PCRO (PID_SCS, 0x600, 0x80000045) /* Set Power State to D0 */ - And (PMCR, 0xFFFC, PMCR) - Store (PMCR, ^TEMP) + PMCR &= 0xFFFC + ^TEMP = PMCR } Method (_PS3, 0, Serialized) { /* Enable Power Gate */ - Store (1, ^PGEN) + ^PGEN = 1 /* Set Power State to D3 */ - Or (PMCR, 0x0003, PMCR) - Store (PMCR, ^TEMP) + PMCR |= 0x0003 + ^TEMP = PMCR } Device (CARD) @@ -126,7 +126,7 @@ ^^PCRA (PID_GPIOCOM3, 0x4f4, 0xFFFFEFFF) /* Disable Power Gate */ - Store (0, ^PGEN) + ^PGEN = 0 /* Clear bits 8, 7, 2, 0 */ ^^PCRA (PID_SCS, 0x600, 0xFFFFFE7A) @@ -136,18 +136,18 @@ ^^PCRO (PID_SCS, 0x600, 0x00000185) /* Set Power State to D0 */ - And (PMCR, 0xFFFC, PMCR) - Store (PMCR, ^TEMP) + PMCR &= 0xFFFC + ^TEMP = PMCR } Method (_PS3, 0, Serialized) { /* Enable Power Gate */ - Store (1, ^PGEN) + ^PGEN = 1 /* Set Power State to D3 */ - Or (PMCR, 0x0003, PMCR) - Store (PMCR, ^TEMP) + PMCR |= 0x0003 + ^TEMP = PMCR /* Enable 20K pull-down on CLK, CMD and DAT lines */ ^^PCRO (PID_GPIOCOM3, 0x4c4, 0x00001000) diff --git a/src/soc/intel/skylake/acpi/xhci.asl b/src/soc/intel/skylake/acpi/xhci.asl index 2f5d8b2..b891b2f 100644 --- a/src/soc/intel/skylake/acpi/xhci.asl +++ b/src/soc/intel/skylake/acpi/xhci.asl @@ -118,37 +118,37 @@ Method (_PS0, 0, Serialized) { - If (!LEqual (^DVID, 0xFFFF)) { - If (!LOr (LEqual (^XMEM, 0xFFFF), LEqual (^XMEM, 0x0000))) { + If (^DVID != 0xFFFF) { + If (!((^XMEM == 0xFFFF) || (^XMEM == 0x0000))) { /* Disable d3hot and SS link trunk clock gating */ - Store(Zero, ^D3HE) - Store(Zero, ^STGE) + ^D3HE = 0 + ^STGE = 0 /* If device is in D3, set back to D0 */ - If (LEqual (^D0D3, 3)) { - Store (Zero, Local0) - Store (Local0, ^D0D3) - Store (^D0D3, Local0) + If (^D0D3 == 3) { + Local0 = 0 + ^D0D3 = Local0 + Local0 = ^D0D3 } /* Disable USB2 PHY SUS Well Power Gating */ - Store (Zero, ^UPSW) + ^UPSW = 0 /* * Apply USB2 PHPY Power Gating workaround if needed. */ If (^^PMC.UWAB) { /* Write to MTPMC to have PMC disable power gating */ - Store (1, ^^PMC.MPMC) + ^^PMC.MPMC = 1 /* Wait for PCH_PM_STS.MSG_FULL_STS to be 0 */ - Store (10, Local0) + Local0 = 10 While (^^PMC.PMFS) { - If (LNot (Local0)) { + If (!Local0) { Break } - Decrement (Local0) + Local0-- Sleep (10) } } @@ -158,33 +158,33 @@ Method (_PS3, 0, Serialized) { - If (!LEqual (^DVID, 0xFFFF)) { - If (!LOr (LEqual (^XMEM, 0xFFFF), LEqual (^XMEM, 0x0000))) { + If (^DVID != 0xFFFF) { + If (!((^XMEM == 0xFFFF) || (^XMEM == 0x0000))) { /* Clear PME Status */ - Store (1, ^PMES) + ^PMES = 1 /* Enable PME */ - Store (1, ^PMEE) + ^PMEE= 1 /* If device is in D3, set back to D0 */ - If (LEqual (^D0D3, 3)) { - Store (Zero, Local0) - Store (Local0, ^D0D3) - Store (^D0D3, Local0) + If (^D0D3 == 3) { + Local0 = 0 + ^D0D3 = Local0 + Local0 = ^D0D3 } /* Enable USB2 PHY SUS Well Power Gating in D0/D0i2/D0i3/D3 */ - Store (3, ^UPSW) + ^UPSW = 3 /* Enable d3hot and SS link trunk clock gating */ - Store(One, ^D3HE) - Store(One, ^STGE) + ^D3HE = 1 + ^STGE = 1 /* Now put device in D3 */ - Store (3, Local0) - Store (Local0, ^D0D3) - Store (^D0D3, Local0) + Local0 = 3 + ^D0D3 = Local0 + Local0 = ^D0D3 /* * Apply USB2 PHPY Power Gating workaround if needed. @@ -193,15 +193,15 @@ */ If (^^PMC.UWAB) { /* Write to MTPMC to have PMC enable power gating */ - Store (3, ^^PMC.MPMC) + ^^PMC.MPMC = 3 /* Wait for PCH_PM_STS.MSG_FULL_STS to be 0 */ - Store (10, Local0) + Local0 = 10 While (^^PMC.PMFS) { - If (LNot (Local0)) { + If (!Local0) { Break } - Decrement (Local0) + Local0-- Sleep (10) } } -- To view, visit https://review.coreboot.org/c/coreboot/+/46242 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iea915b60d8ec9a1a7a2aa5926b0277cae58113a6 Gerrit-Change-Number: 46242 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

4 6

Change in coreboot[master]: sb/intel/x/lpc.c: Drop commented-out `gpio_init` call
by Angel Pons (Code Review) 10 Feb '21

10 Feb '21

Attention is currently required from: Patrick Rudolph. Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/50491 ) Change subject: sb/intel/x/lpc.c: Drop commented-out `gpio_init` call ...................................................................... sb/intel/x/lpc.c: Drop commented-out `gpio_init` call Change-Id: I4255c63f87e8243237204ac86eb85e34b5aaa225 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/southbridge/intel/bd82x6x/lpc.c M src/southbridge/intel/i82801gx/lpc.c M src/southbridge/intel/ibexpeak/lpc.c 3 files changed, 0 insertions(+), 9 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/91/50491/1 diff --git a/src/southbridge/intel/bd82x6x/lpc.c b/src/southbridge/intel/bd82x6x/lpc.c index 8bdaa5a..7f648a9 100644 --- a/src/southbridge/intel/bd82x6x/lpc.c +++ b/src/southbridge/intel/bd82x6x/lpc.c @@ -529,9 +529,6 @@ printk(BIOS_ERR, "Unknown Chipset: 0x%04x\n", dev->device); } - /* Set the state of the GPIO lines. */ - //gpio_init(dev); - /* Initialize the real time clock. */ sb_rtc_init(); diff --git a/src/southbridge/intel/i82801gx/lpc.c b/src/southbridge/intel/i82801gx/lpc.c index a8bc7e3..a44bbf9 100644 --- a/src/southbridge/intel/i82801gx/lpc.c +++ b/src/southbridge/intel/i82801gx/lpc.c @@ -335,9 +335,6 @@ /* Configure Cx state registers */ i82801gx_configure_cstates(dev); - /* Set the state of the GPIO lines. */ - //gpio_init(dev); - /* Initialize the real time clock. */ i82801gx_rtc_init(dev); diff --git a/src/southbridge/intel/ibexpeak/lpc.c b/src/southbridge/intel/ibexpeak/lpc.c index 0a96473..3309283 100644 --- a/src/southbridge/intel/ibexpeak/lpc.c +++ b/src/southbridge/intel/ibexpeak/lpc.c @@ -431,9 +431,6 @@ /* Initialize power management */ mobile5_pm_init(dev); - /* Set the state of the GPIO lines. */ - //gpio_init(dev); - /* Initialize the real time clock. */ pch_rtc_init(dev); -- To view, visit https://review.coreboot.org/c/coreboot/+/50491 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4255c63f87e8243237204ac86eb85e34b5aaa225 Gerrit-Change-Number: 50491 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: [Just for x86_64 build test] (LGA775 & i945)
by Nico Huber (Code Review) 10 Feb '21

10 Feb '21

Attention is currently required from: Patrick Rudolph. Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49792 ) Change subject: [Just for x86_64 build test] (LGA775 & i945) ...................................................................... Patch Set 6: (1 comment) File src/northbridge/intel/common/fixed_bars.h: https://review.coreboot.org/c/coreboot/+/49792/comment/eaa60ee2_913f1088 PS6, Line 17: /* but not here , why? */ The compiler doesn't seem to complain when the macros are only used with constants as arguments (but not variables). -- To view, visit https://review.coreboot.org/c/coreboot/+/49792 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8e398c690006ae0dff9a53a61da501e3d4deeeb1 Gerrit-Change-Number: 49792 Gerrit-PatchSet: 6 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Wed, 10 Feb 2021 17:46:47 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/intel/wtm2: Convert to ASL 2.0 syntax
by HAOUAS Elyes (Code Review) 10 Feb '21

10 Feb '21

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46186 ) Change subject: mb/intel/wtm2: Convert to ASL 2.0 syntax ...................................................................... mb/intel/wtm2: Convert to ASL 2.0 syntax Change-Id: Id68623cfb57e889e60d66cd465612336cd8298ca Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/mainboard/intel/wtm2/acpi/thermal.asl 1 file changed, 22 insertions(+), 22 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/86/46186/1 diff --git a/src/mainboard/intel/wtm2/acpi/thermal.asl b/src/mainboard/intel/wtm2/acpi/thermal.asl index cb56e97..fe3961e 100644 --- a/src/mainboard/intel/wtm2/acpi/thermal.asl +++ b/src/mainboard/intel/wtm2/acpi/thermal.asl @@ -22,10 +22,10 @@ // Convert from Degrees C to 1/10 Kelvin for ACPI Method (CTOK, 1) { // 10th of Degrees C - Multiply (Arg0, 10, Local0) + Local0 = Arg0 * 10 // Convert to Kelvin - Add (Local0, 2732, Local0) + Local0 += 2732 Return (Local0) } @@ -54,7 +54,7 @@ } Method (_AC0) { - If (LLessEqual (\FLVL, 0)) { + If (\FLVL <= 0) { Return (CTOK (FAN0_THRESHOLD_OFF)) } Else { Return (CTOK (FAN0_THRESHOLD_ON)) @@ -62,7 +62,7 @@ } Method (_AC1) { - If (LLessEqual (\FLVL, 1)) { + If (\FLVL <= 1) { Return (CTOK (FAN1_THRESHOLD_OFF)) } Else { Return (CTOK (FAN1_THRESHOLD_ON)) @@ -70,7 +70,7 @@ } Method (_AC2) { - If (LLessEqual (\FLVL, 2)) { + If (\FLVL <= 2) { Return (CTOK (FAN2_THRESHOLD_OFF)) } Else { Return (CTOK (FAN2_THRESHOLD_ON)) @@ -78,7 +78,7 @@ } Method (_AC3) { - If (LLessEqual (\FLVL, 3)) { + If (\FLVL <= 3) { Return (CTOK (FAN3_THRESHOLD_OFF)) } Else { Return (CTOK (FAN3_THRESHOLD_ON)) @@ -86,7 +86,7 @@ } Method (_AC4) { - If (LLessEqual (\FLVL, 4)) { + If (\FLVL <= 4) { Return (CTOK (FAN4_THRESHOLD_OFF)) } Else { Return (CTOK (FAN4_THRESHOLD_ON)) @@ -102,18 +102,18 @@ PowerResource (FNP0, 0, 0) { Method (_STA) { - If (LLessEqual (\FLVL, 0)) { + If (\FLVL <= 0) { Return (One) } Else { Return (Zero) } } Method (_ON) { - Store (0, \FLVL) + \FLVL = 0 Notify (\_TZ.THRM, 0x81) } Method (_OFF) { - Store (1, \FLVL) + \FLVL = 1 Notify (\_TZ.THRM, 0x81) } } @@ -121,18 +121,18 @@ PowerResource (FNP1, 0, 0) { Method (_STA) { - If (LLessEqual (\FLVL, 1)) { + If (\FLVL <= 1) { Return (One) } Else { Return (Zero) } } Method (_ON) { - Store (1, \FLVL) + \FLVL = 1 Notify (\_TZ.THRM, 0x81) } Method (_OFF) { - Store (2, \FLVL) + \FLVL = 2 Notify (\_TZ.THRM, 0x81) } } @@ -140,18 +140,18 @@ PowerResource (FNP2, 0, 0) { Method (_STA) { - If (LLessEqual (\FLVL, 2)) { + If (\FLVL <= 2) { Return (One) } Else { Return (Zero) } } Method (_ON) { - Store (2, \FLVL) + \FLVL = 2 Notify (\_TZ.THRM, 0x81) } Method (_OFF) { - Store (3, \FLVL) + \FLVL = 3 Notify (\_TZ.THRM, 0x81) } } @@ -159,18 +159,18 @@ PowerResource (FNP3, 0, 0) { Method (_STA) { - If (LLessEqual (\FLVL, 3)) { + If (\FLVL <= 3) { Return (One) } Else { Return (Zero) } } Method (_ON) { - Store (3, \FLVL) + \FLVL = 3 Notify (\_TZ.THRM, 0x81) } Method (_OFF) { - Store (4, \FLVL) + \FLVL = 4 Notify (\_TZ.THRM, 0x81) } } @@ -178,18 +178,18 @@ PowerResource (FNP4, 0, 0) { Method (_STA) { - If (LLessEqual (\FLVL, 4)) { + If (\FLVL <= 4) { Return (One) } Else { Return (Zero) } } Method (_ON) { - Store (4, \FLVL) + \FLVL = 4 Notify (\_TZ.THRM, 0x81) } Method (_OFF) { - Store (4, \FLVL) + \FLVL = 4 Notify (\_TZ.THRM, 0x81) } } -- To view, visit https://review.coreboot.org/c/coreboot/+/46186 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id68623cfb57e889e60d66cd465612336cd8298ca Gerrit-Change-Number: 46186 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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Change in coreboot[master]: drivers/i2c/hid: Enforce level triggered IRQ mode
by Angel Pons (Code Review) 10 Feb '21

10 Feb '21

Attention is currently required from: Furquan Shaikh, Tim Wawrzynczak, Michael Niewöhner, Karthik Ramasubramanian. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50442 ) Change subject: drivers/i2c/hid: Enforce level triggered IRQ mode ...................................................................... Patch Set 3: (1 comment) File src/drivers/i2c/hid/hid.c: https://review.coreboot.org/c/coreboot/+/50442/comment/246ba7b3_9ff94c93 PS3, Line 82: dev->enabled = 0; > > It's the vendor's fault for making defective hardware. […] I agree with Tim that we don't need to disable the device: updating the devicetree to use level-triggered IRQs should be enough. -- To view, visit https://review.coreboot.org/c/coreboot/+/50442 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3245a9de6e88cd83528823251083e62288192f0d Gerrit-Change-Number: 50442 Gerrit-PatchSet: 3 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Wed, 10 Feb 2021 17:45:36 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Comment-In-Reply-To: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/skylake/acpi: Add PEP table
by Michael Niewöhner (Code Review) 10 Feb '21

10 Feb '21

Michael Niewöhner has submitted this change. ( https://review.coreboot.org/c/coreboot/+/49140 ) Change subject: soc/intel/skylake/acpi: Add PEP table ...................................................................... soc/intel/skylake/acpi: Add PEP table PEP table is applicable to Skylake platform as well. It is required to make the kernel load `intel_pmc_core`. Skylake boards can also use S0ix hooks. Tested on an out-of-tree Acer Aspire VN7-572G (Skylake-U), intel_pmc_core kernel module is loaded and reports statuses predictably via debugfs. Change-Id: I08d8c1fde4f447e9292a0508649f802fdc2721e1 Signed-off-by: Benjamin Doron <benjamin.doron00(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49140 Reviewed-by: Michael Niewöhner <foss(a)mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/intel/skylake/acpi/pch.asl 1 file changed, 3 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Michael Niewöhner: Looks good to me, approved diff --git a/src/soc/intel/skylake/acpi/pch.asl b/src/soc/intel/skylake/acpi/pch.asl index 02e30f7..9c3385f 100644 --- a/src/soc/intel/skylake/acpi/pch.asl +++ b/src/soc/intel/skylake/acpi/pch.asl @@ -68,3 +68,6 @@ /* Integrated graphics 0:2.0 */ #include <drivers/intel/gma/acpi/gfx.asl> + +/* Intel Power Engine Plug-in */ +#include <soc/intel/common/block/acpi/acpi/pep.asl> -- To view, visit https://review.coreboot.org/c/coreboot/+/49140 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I08d8c1fde4f447e9292a0508649f802fdc2721e1 Gerrit-Change-Number: 49140 Gerrit-PatchSet: 8 Gerrit-Owner: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/razer/blade_stealth_kbl: Configure IRQs as level triggered for HID...
by Michael Niewöhner (Code Review) 10 Feb '21

10 Feb '21

Attention is currently required from: Felix Singer, Furquan Shaikh, Tim Wawrzynczak, Mimoja, Karthik Ramasubramanian. Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50453 ) Change subject: mb/razer/blade_stealth_kbl: Configure IRQs as level triggered for HID over I2C ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/50453 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifdc3f061d919c8db9001c7a4cc26eb21117958d7 Gerrit-Change-Number: 50453 Gerrit-PatchSet: 1 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Mimoja <coreboot(a)mimoja.de> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Felix Singer <felixsinger(a)posteo.net> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Mimoja <coreboot(a)mimoja.de> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Wed, 10 Feb 2021 17:43:47 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/system76/lemp9: Configure IRQs as level triggered for HID over I2C
by Michael Niewöhner (Code Review) 10 Feb '21

10 Feb '21

Attention is currently required from: Furquan Shaikh, Jeremy Soller, Tim Wawrzynczak, Karthik Ramasubramanian. Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50452 ) Change subject: mb/system76/lemp9: Configure IRQs as level triggered for HID over I2C ...................................................................... Patch Set 1: Code-Review+2 (1 comment) Patchset: PS1: Same as clevo/cml-u -- To view, visit https://review.coreboot.org/c/coreboot/+/50452 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ice096777077bd2e9cfbaf744371fc372c0c05606 Gerrit-Change-Number: 50452 Gerrit-PatchSet: 1 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Jeremy Soller <jeremy(a)system76.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Jeremy Soller <jeremy(a)system76.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Wed, 10 Feb 2021 17:43:22 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: drivers/i2c/hid: Enforce level triggered IRQ mode
by Michael Niewöhner (Code Review) 10 Feb '21

10 Feb '21

Attention is currently required from: Furquan Shaikh, Tim Wawrzynczak, Angel Pons, Karthik Ramasubramanian. Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50442 ) Change subject: drivers/i2c/hid: Enforce level triggered IRQ mode ...................................................................... Patch Set 3: (1 comment) File src/drivers/i2c/hid/hid.c: https://review.coreboot.org/c/coreboot/+/50442/comment/df448c02_e288393d PS3, Line 82: dev->enabled = 0; > It's the vendor's fault for making defective hardware. While this is right, we shouldn't make it worse and break the users device that would actually work even with an edge-triggered interrupt. > I believe a level-triggered pad should always catch any edge pulses as well; the other way around could cause problems, but I think if we just print a warning and possibly set the trigger type back to LEVEL, everything should still work, there shouldn't be any need to disable the device. Not sure what you mean with "and possibly set the trigger type back to LEVEL" but I'm inclined to agree on the rest. A warning should be enough. The only case where I'd disable the interrupt is when it'd cause any other problems (it doesn't AFAIK). Also, disabling the whole device is too much. IIRC at least Linux falls back to polling, when there's no interrupt. -- To view, visit https://review.coreboot.org/c/coreboot/+/50442 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3245a9de6e88cd83528823251083e62288192f0d Gerrit-Change-Number: 50442 Gerrit-PatchSet: 3 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Wed, 10 Feb 2021 17:41:53 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Comment-In-Reply-To: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-MessageType: comment

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Change in coreboot[master]: [Just for x86_64 build test] (LGA775 & i945)
by HAOUAS Elyes (Code Review) 10 Feb '21

10 Feb '21

Attention is currently required from: Patrick Rudolph. HAOUAS Elyes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49792 ) Change subject: [Just for x86_64 build test] (LGA775 & i945) ...................................................................... Patch Set 7: (1 comment) File src/northbridge/intel/common/fixed_bars.h: https://review.coreboot.org/c/coreboot/+/49792/comment/8c81ac3e_c91872a1 PS7, Line 12: here Jenkins if missing cast to uintptr_t oops. here Jenkins complain if missing cast to uintptr_t :)) -- To view, visit https://review.coreboot.org/c/coreboot/+/49792 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8e398c690006ae0dff9a53a61da501e3d4deeeb1 Gerrit-Change-Number: 49792 Gerrit-PatchSet: 7 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Wed, 10 Feb 2021 17:39:06 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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