coreboot-gerrit February 2021

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Change in coreboot[master]: soc/amd/cezanne/smihandler: add missing southbridge_io_trap_handler
by Martin Roth (Code Review) 10 Feb '21

10 Feb '21

Attention is currently required from: Jason Glenesk, Raul Rangel, Marshall Dawson, Felix Held. Martin Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50465 ) Change subject: soc/amd/cezanne/smihandler: add missing southbridge_io_trap_handler ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/50465 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4140fbf93e84a2620ffb88e5c65df17b23135553 Gerrit-Change-Number: 50465 Gerrit-PatchSet: 3 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Wed, 10 Feb 2021 16:38:23 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/amd: fully commonize clear_tvalid
by Martin Roth (Code Review) 10 Feb '21

10 Feb '21

Attention is currently required from: Jason Glenesk, Raul Rangel, Marshall Dawson, Felix Held. Martin Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50466 ) Change subject: soc/amd: fully commonize clear_tvalid ...................................................................... Patch Set 5: (1 comment) File src/soc/amd/common/block/cpu/smm/Makefile.inc: https://review.coreboot.org/c/coreboot/+/50466/comment/b8cd7154_f67a23c7 PS5, Line 5: romstage-y += smm_helper.c : postcar-y += smm_helper.c Is this used in romstage or postcar? That just seams a little early to me. -- To view, visit https://review.coreboot.org/c/coreboot/+/50466 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I90526a566a5fbc19a7368f90421067a6c716614e Gerrit-Change-Number: 50466 Gerrit-PatchSet: 5 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Wed, 10 Feb 2021 16:37:54 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/amd/cezanne/cpu: add basic zen_2_3_init functionality
by Martin Roth (Code Review) 10 Feb '21

10 Feb '21

Attention is currently required from: Jason Glenesk, Raul Rangel, Marshall Dawson, Felix Held. Martin Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50482 ) Change subject: soc/amd/cezanne/cpu: add basic zen_2_3_init functionality ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/50482 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I38ce5d11787ffefdd0183c5540ae2683158cbee8 Gerrit-Change-Number: 50482 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Wed, 10 Feb 2021 16:32:38 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/amd/cezanne: add empty mp_init_cpus
by Martin Roth (Code Review) 10 Feb '21

10 Feb '21

Attention is currently required from: Jason Glenesk, Raul Rangel, Marshall Dawson, Felix Held. Martin Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50483 ) Change subject: soc/amd/cezanne: add empty mp_init_cpus ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/50483 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I845a7e2cfea58ca08cd2a6f0d884dbbbe1a7bdef Gerrit-Change-Number: 50483 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Wed, 10 Feb 2021 16:32:01 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/amd/cezanne/chip: set device operations for UART MMIO devices
by Martin Roth (Code Review) 10 Feb '21

10 Feb '21

Attention is currently required from: Jason Glenesk, Raul Rangel, Marshall Dawson, Felix Held. Martin Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50484 ) Change subject: soc/amd/cezanne/chip: set device operations for UART MMIO devices ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/50484 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5df3a61741f05364e2c20725b0b85164b197dbdc Gerrit-Change-Number: 50484 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Wed, 10 Feb 2021 16:31:30 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/amd/*/smihandler: remove replace southbridge references with fch
by Martin Roth (Code Review) 10 Feb '21

10 Feb '21

Attention is currently required from: Jason Glenesk, Raul Rangel, Marshall Dawson, Felix Held. Martin Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50485 ) Change subject: soc/amd/*/smihandler: remove replace southbridge references with fch ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/50485 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I96fc8082263800b731f1d4d9ecdc8a99c28bff32 Gerrit-Change-Number: 50485 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Wed, 10 Feb 2021 16:28:58 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/amd/*/smihandler: use size_t
by Martin Roth (Code Review) 10 Feb '21

10 Feb '21

Attention is currently required from: Jason Glenesk, Raul Rangel, Marshall Dawson, Felix Held. Martin Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50486 ) Change subject: soc/amd/*/smihandler: use size_t ...................................................................... Patch Set 1: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/50486/comment/5daecb35_bdc16661 PS1, Line 10: cases the value shouldn't became negative. I agree with what you're saying, but why not use an unsigned int instead of a size? The core number isn't a size. -- To view, visit https://review.coreboot.org/c/coreboot/+/50486 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iefac021260ff363c76bf5cd3fe3619ea1dbabdba Gerrit-Change-Number: 50486 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Wed, 10 Feb 2021 16:28:35 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/amd/cezanne: Add verstage support
by Martin Roth (Code Review) 10 Feb '21

10 Feb '21

Attention is currently required from: Jason Glenesk, Raul Rangel, Marshall Dawson, Felix Held. Martin Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50342 ) Change subject: soc/amd/cezanne: Add verstage support ...................................................................... Patch Set 2: (1 comment) File src/soc/amd/cezanne/Kconfig: https://review.coreboot.org/c/coreboot/+/50342/comment/b68fa45e_92733190 PS2, Line 128: config VBOOT : select VBOOT_STARTS_IN_BOOTBLOCK : select VBOOT_SEPARATE_VERSTAGE > Wasn't suggesting anything 😊 Only trying to sanity-check. I'm fine with it. I think it should go in the mainboard. We plan on supporting both PSP and x86 verstages again, correct? -- To view, visit https://review.coreboot.org/c/coreboot/+/50342 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I82874d649db3c9c370e32841e6a9898efb70082e Gerrit-Change-Number: 50342 Gerrit-PatchSet: 2 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Wed, 10 Feb 2021 16:25:48 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Raul Rangel <rrangel(a)chromium.org> Comment-In-Reply-To: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/*: Update microcode as specified for MP-init
by Tim Wawrzynczak (Code Review) 10 Feb '21

10 Feb '21

Attention is currently required from: Nico Huber, Patrick Rudolph, Subrata Banik, Andrey Petrov, Nathaniel L Desimone. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49899 ) Change subject: soc/intel/*: Update microcode as specified for MP-init ...................................................................... Patch Set 13: (1 comment) File src/soc/intel/alderlake/cpu.c: https://review.coreboot.org/c/coreboot/+/49899/comment/92f1cbfe_df62e658 PS13, Line 70: PRMRR > Subrata, Nate, where is the sequence documented for platforms without […] For ADL, there is a new MCHECK flow in the FSP, which apparently requires a microcode load immediately preceding it, therefore we have to use the MicrodeRegionBase UPD for ADL to have the FSP load the ucode patch a 2nd time. For TGL, here are the snippets I can find in the BIOS core-uncore specs: ``` 3.3.2.2 Loading Microcode Update on Application Processors (AP) 1. Immediately after wake up at the first time, such as during early MP initialization, load, if current revision is ‘0’. 2. Must reload after memory initialization and PRMRR are configured. 3.3.2.3 Loading Microcode Update During POST After caching is enabled and MTRR/PRMRR are properly configured, the BIOS is required to reload the microcode update on all threads in order to activate certain features, such as SGX. 3.3.4 BIOS based second patch load: Post memory initialization, System BIOS loads the microcode patch a second time on all threads. This step takes care of loading the uncore component of the patch. At this point, MCHECK executes to verify different aspects in the configurations, so far. ``` For CML, #550049 says the following: ``` There are four MP initialization phases executed by the BSP and all APs. • In Phase 1 the BIOS disables caching. • In Phase 2 the BIOS loads the microcode update on all threads. • In Phase 3 the BIOS configures and enables caching on all cores. The MTRRs, PRMRR and DCU prefetcher configuration is copied from the BSP configuration. • In Phase 4 BIOS executes reload of microcode update on all threads and initialize the machine-check banks. ``` I don't see anything in there w/r/t timing of 2nd load & SMM relocation. -- To view, visit https://review.coreboot.org/c/coreboot/+/49899 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idf2b009ac9dd7cd462abe0f787f27b09feb6ec5b Gerrit-Change-Number: 49899 Gerrit-PatchSet: 13 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Nathaniel L Desimone <nathaniel.l.desimone(a)intel.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Nathaniel L Desimone <nathaniel.l.desimone(a)intel.com> Gerrit-Comment-Date: Wed, 10 Feb 2021 16:24:17 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/amd/common/block: Fix guards for PSP transfer buffer
by Martin Roth (Code Review) 10 Feb '21

10 Feb '21

Martin Roth has submitted this change. ( https://review.coreboot.org/c/coreboot/+/50403 ) Change subject: soc/amd/common/block: Fix guards for PSP transfer buffer ...................................................................... soc/amd/common/block: Fix guards for PSP transfer buffer The transfer buffer is only required when using VBOOT_STARTS_BEFORE_BOOTBLOCK. The VBOOT workbuffer is only required when VBOOT_STARTS_BEFORE_BOOTBLOCK or VBOOT_STARTS_IN_BOOTBLOCK. Signed-off-by: Raul E Rangel <rrangel(a)chromium.org> Change-Id: I444bede3f2b716e1900e7621453351d7fddadaa3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/50403 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Felix Held <felix-coreboot(a)felixheld.de> Reviewed-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> --- M src/soc/amd/common/block/cpu/noncar/memlayout_transfer_buffer.inc M src/soc/amd/common/block/cpu/noncar/memlayout_x86.ld 2 files changed, 6 insertions(+), 4 deletions(-) Approvals: build bot (Jenkins): Verified Felix Held: Looks good to me, approved Marshall Dawson: Looks good to me, approved diff --git a/src/soc/amd/common/block/cpu/noncar/memlayout_transfer_buffer.inc b/src/soc/amd/common/block/cpu/noncar/memlayout_transfer_buffer.inc index 1b80f6b..896512a 100644 --- a/src/soc/amd/common/block/cpu/noncar/memlayout_transfer_buffer.inc +++ b/src/soc/amd/common/block/cpu/noncar/memlayout_transfer_buffer.inc @@ -1,10 +1,12 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#if CONFIG(VBOOT) +#if CONFIG(VBOOT_STARTS_BEFORE_BOOTBLOCK) ALIGN_COUNTER(64) _transfer_buffer = .; REGION(transfer_info, ., TRANSFER_INFO_SIZE, 4) +#endif +#if CONFIG(VBOOT_STARTS_BEFORE_BOOTBLOCK) || CONFIG(VBOOT_STARTS_IN_BOOTBLOCK) ALIGN_COUNTER(64) VBOOT2_WORK(., VB2_FIRMWARE_WORKBUF_RECOMMENDED_SIZE) #endif @@ -15,6 +17,6 @@ CBFS_MCACHE(., CONFIG_CBFS_MCACHE_SIZE) FMAP_CACHE(., FMAP_SIZE) -#if CONFIG(VBOOT) +#if CONFIG(VBOOT_STARTS_BEFORE_BOOTBLOCK) _etransfer_buffer = .; #endif diff --git a/src/soc/amd/common/block/cpu/noncar/memlayout_x86.ld b/src/soc/amd/common/block/cpu/noncar/memlayout_x86.ld index e1f2765..ff6aebf 100644 --- a/src/soc/amd/common/block/cpu/noncar/memlayout_x86.ld +++ b/src/soc/amd/common/block/cpu/noncar/memlayout_x86.ld @@ -78,13 +78,13 @@ EARLYRAM_STACK(., CONFIG_EARLYRAM_BSP_STACK_SIZE) REGION(apob, CONFIG_PSP_APOB_DRAM_ADDRESS, 64K, 1) -#if CONFIG(VBOOT) +#if CONFIG(VBOOT_STARTS_BEFORE_BOOTBLOCK) PSP_SHAREDMEM_DRAM_START(CONFIG_PSP_SHAREDMEM_BASE) #endif #include "memlayout_transfer_buffer.inc" -#if CONFIG(VBOOT) +#if CONFIG(VBOOT_STARTS_BEFORE_BOOTBLOCK) PSP_SHAREDMEM_DRAM_END(CONFIG_PSP_SHAREDMEM_BASE + CONFIG_PSP_SHAREDMEM_SIZE) #endif _ = ASSERT(BOOTBLOCK_END == ((BOOTBLOCK_END + 0xFFFF) & 0xFFFF0000), "Bootblock end must be 16 bit aligned"); -- To view, visit https://review.coreboot.org/c/coreboot/+/50403 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I444bede3f2b716e1900e7621453351d7fddadaa3 Gerrit-Change-Number: 50403 Gerrit-PatchSet: 2 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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coreboot-gerrit February 2021