coreboot-gerrit February 2021

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Change in coreboot[master]: soc/amd/cezanne/smihandler: add basic SMI APMC and sleep handler
by Felix Held (Code Review) 10 Feb '21

10 Feb '21

Attention is currently required from: Jason Glenesk, Raul Rangel, Marshall Dawson. Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/50488 ) Change subject: soc/amd/cezanne/smihandler: add basic SMI APMC and sleep handler ...................................................................... soc/amd/cezanne/smihandler: add basic SMI APMC and sleep handler Only the ACPI enable/disable functionality is implemented and sleep is also not implemented yet. This will be added in future patches. Change-Id: I7701944023ce2e86586679c32c4138d4488768a1 Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> --- M src/soc/amd/cezanne/smihandler.c 1 file changed, 76 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/88/50488/1 diff --git a/src/soc/amd/cezanne/smihandler.c b/src/soc/amd/cezanne/smihandler.c index 46164e4..80dbb7b 100644 --- a/src/soc/amd/cezanne/smihandler.c +++ b/src/soc/amd/cezanne/smihandler.c @@ -1,14 +1,90 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ +#include <acpi/acpi.h> +#include <amdblocks/acpi.h> +#include <amdblocks/acpimmio.h> +#include <amdblocks/smi.h> #include <amdblocks/smm.h> +#include <arch/hlt.h> +#include <arch/io.h> +#include <console/console.h> #include <cpu/x86/smm.h> +#include <soc/smi.h> +#include <types.h> + +static void fch_apmc_smi_handler(void) +{ + const uint8_t cmd = inb(pm_acpi_smi_cmd_port()); + + switch (cmd) { + case APM_CNT_ACPI_ENABLE: + acpi_enable_sci(); + break; + case APM_CNT_ACPI_DISABLE: + acpi_disable_sci(); + } + + mainboard_smi_apmc(cmd); +} + +static void fch_slp_typ_handler(void) +{ + uint16_t pm1cnt; + uint8_t slp_typ; + + /* Figure out SLP_TYP */ + pm1cnt = acpi_read16(MMIO_ACPI_PM1_CNT_BLK); + printk(BIOS_SPEW, "SMI#: SLP = 0x%04x\n", pm1cnt); + slp_typ = acpi_sleep_from_pm1(pm1cnt); + + /* Do any mainboard sleep handling */ + mainboard_smi_sleep(slp_typ); + + switch (slp_typ) { + case ACPI_S0: + printk(BIOS_DEBUG, "SMI#: Entering S0 (On)\n"); + break; + case ACPI_S3: + printk(BIOS_DEBUG, "SMI#: Entering S3 (Suspend-To-RAM)\n"); + break; + case ACPI_S4: + printk(BIOS_DEBUG, "SMI#: Entering S4 (Suspend-To-Disk)\n"); + break; + case ACPI_S5: + printk(BIOS_DEBUG, "SMI#: Entering S5 (Soft Power off)\n"); + break; + default: + printk(BIOS_DEBUG, "SMI#: ERROR: SLP_TYP reserved\n"); + break; + } + + if (slp_typ >= ACPI_S3) { + printk(BIOS_ERR, "Error: System did not go to sleep\n"); + hlt(); + } +} int southbridge_io_trap_handler(int smif) { return 0; } +/* + * Table of functions supported in the SMI handler. Note that SMI source setup + * in fch.c is unrelated to this list. + */ +static const struct smi_sources_t smi_sources[] = { + { .type = SMITYPE_SMI_CMD_PORT, .handler = fch_apmc_smi_handler }, + { .type = SMITYPE_SLP_TYP, .handler = fch_slp_typ_handler}, +}; + void *get_smi_source_handler(int source) { + size_t i; + + for (i = 0 ; i < ARRAY_SIZE(smi_sources) ; i++) + if (smi_sources[i].type == source) + return smi_sources[i].handler; + return NULL; } -- To view, visit https://review.coreboot.org/c/coreboot/+/50488 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7701944023ce2e86586679c32c4138d4488768a1 Gerrit-Change-Number: 50488 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/amd/cezanne: select soc-specific APCI functionality
by Felix Held (Code Review) 10 Feb '21

10 Feb '21

Attention is currently required from: Jason Glenesk, Raul Rangel, Marshall Dawson. Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/50487 ) Change subject: soc/amd/cezanne: select soc-specific APCI functionality ...................................................................... soc/amd/cezanne: select soc-specific APCI functionality This doesn't select HAVE_ACPI_TABLES, so no ACPI tables will be generated for now. There's also no globalnvs.asl that corresponds to nvs.h yet. Change-Id: I3d658d284fa67e4da43a89d74686445fd5e93b1f Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> --- M src/soc/amd/cezanne/Kconfig A src/soc/amd/cezanne/include/soc/nvs.h M src/soc/amd/cezanne/include/soc/southbridge.h 3 files changed, 33 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/87/50487/1 diff --git a/src/soc/amd/cezanne/Kconfig b/src/soc/amd/cezanne/Kconfig index 7bd9873..b44a882 100644 --- a/src/soc/amd/cezanne/Kconfig +++ b/src/soc/amd/cezanne/Kconfig @@ -13,6 +13,7 @@ select ARCH_VERSTAGE_X86_32 select ARCH_ROMSTAGE_X86_32 select ARCH_RAMSTAGE_X86_32 + select ACPI_AMD_HARDWARE_SLEEP_VALUES select FSP_COMPRESS_FSP_M_LZMA select FSP_COMPRESS_FSP_S_LZMA select HAVE_CF9_RESET @@ -22,6 +23,7 @@ select PLATFORM_USES_FSP2_0 select RESET_VECTOR_IN_RAM select SOC_AMD_COMMON + select SOC_AMD_COMMON_BLOCK_ACPI select SOC_AMD_COMMON_BLOCK_ACPIMMIO select SOC_AMD_COMMON_BLOCK_AOAC select SOC_AMD_COMMON_BLOCK_BANKED_GPIOS diff --git a/src/soc/amd/cezanne/include/soc/nvs.h b/src/soc/amd/cezanne/include/soc/nvs.h new file mode 100644 index 0000000..7eb6cf6 --- /dev/null +++ b/src/soc/amd/cezanne/include/soc/nvs.h @@ -0,0 +1,27 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +/* + * NOTE: The layout of the global_nvs structure below must match the layout + * in soc/soc/amd/cezanne/acpi/globalnvs.asl !!! + * + */ + +#ifndef AMD_CEZANNE_NVS_H +#define AMD_CEZANNE_NVS_H + +#include <stdint.h> + +struct __packed global_nvs { + /* Miscellaneous */ + uint8_t unused_was_pcnt; /* 0x00 - Processor Count */ + uint8_t lids; /* 0x01 - LID State */ + uint8_t pwrs; /* 0x02 - AC Power State */ + uint32_t cbmc; /* 0x03 - 0x06 - coreboot Memory Console */ + uint64_t pm1i; /* 0x07 - 0x0e - System Wake Source - PM1 Index */ + uint64_t gpei; /* 0x0f - 0x16 - GPE Wake Source */ + uint8_t tmps; /* 0x17 - Temperature Sensor ID */ + uint8_t tcrt; /* 0x18 - Critical Threshold */ + uint8_t tpsv; /* 0x19 - Passive Threshold */ +}; + +#endif /* AMD_CEZANNE_NVS_H */ diff --git a/src/soc/amd/cezanne/include/soc/southbridge.h b/src/soc/amd/cezanne/include/soc/southbridge.h index dcb5ef1..0b5882e 100644 --- a/src/soc/amd/cezanne/include/soc/southbridge.h +++ b/src/soc/amd/cezanne/include/soc/southbridge.h @@ -59,6 +59,10 @@ #define PM_LPC_A20_EN BIT(1) #define PM_LPC_ENABLE BIT(0) +#define PM1_LIMIT 16 +#define GPE0_LIMIT 32 +#define TOTAL_BITS(a) (8 * sizeof(a)) + #define FCH_LEGACY_UART_DECODE (ALINK_AHB_ADDRESS + 0x20) /* 0xfedc0020 */ /* FCH AOAC device offsets for AOAC_DEV_D3_CTL/AOAC_DEV_D3_STATE */ -- To view, visit https://review.coreboot.org/c/coreboot/+/50487 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3d658d284fa67e4da43a89d74686445fd5e93b1f Gerrit-Change-Number: 50487 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/amd/*/smihandler: use size_t
by Felix Held (Code Review) 10 Feb '21

10 Feb '21

Attention is currently required from: Jason Glenesk, Raul Rangel, Marshall Dawson. Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/50486 ) Change subject: soc/amd/*/smihandler: use size_t ...................................................................... soc/amd/*/smihandler: use size_t signed int should only be used when we need negative values and in those cases the value shouldn't became negative. Change-Id: Iefac021260ff363c76bf5cd3fe3619ea1dbabdba Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> --- M src/soc/amd/picasso/smihandler.c M src/soc/amd/stoneyridge/smihandler.c 2 files changed, 6 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/86/50486/1 diff --git a/src/soc/amd/picasso/smihandler.c b/src/soc/amd/picasso/smihandler.c index 735fd77..1b09396 100644 --- a/src/soc/amd/picasso/smihandler.c +++ b/src/soc/amd/picasso/smihandler.c @@ -18,6 +18,7 @@ #include <amdblocks/smm.h> #include <elog.h> #include <soc/smu.h> +#include <types.h> /* bits in smm_io_trap */ #define SMM_IO_TRAP_PORT_OFFSET 16 @@ -33,7 +34,7 @@ static void *find_save_state(int cmd) { - int core; + size_t core; amd64_smm_state_save_area_t *state; u32 smm_io_trap; u8 reg_al; @@ -225,7 +226,7 @@ void *get_smi_source_handler(int source) { - int i; + size_t i; for (i = 0 ; i < ARRAY_SIZE(smi_sources) ; i++) if (smi_sources[i].type == source) diff --git a/src/soc/amd/stoneyridge/smihandler.c b/src/soc/amd/stoneyridge/smihandler.c index 3a65f55..1e1186c 100644 --- a/src/soc/amd/stoneyridge/smihandler.c +++ b/src/soc/amd/stoneyridge/smihandler.c @@ -16,6 +16,7 @@ #include <amdblocks/smi.h> #include <amdblocks/smm.h> #include <elog.h> +#include <types.h> /* bits in smm_io_trap */ #define SMM_IO_TRAP_PORT_OFFSET 16 @@ -31,7 +32,7 @@ static void *find_save_state(int cmd) { - int core; + size_t core; amd64_smm_state_save_area_t *state; u32 smm_io_trap; u8 reg_al; @@ -220,7 +221,7 @@ void *get_smi_source_handler(int source) { - int i; + size_t i; for (i = 0 ; i < ARRAY_SIZE(smi_sources) ; i++) if (smi_sources[i].type == source) -- To view, visit https://review.coreboot.org/c/coreboot/+/50486 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iefac021260ff363c76bf5cd3fe3619ea1dbabdba Gerrit-Change-Number: 50486 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/amd/*/smihandler: remove replace southbridge references with fch
by Felix Held (Code Review) 10 Feb '21

10 Feb '21

Attention is currently required from: Jason Glenesk, Raul Rangel, Marshall Dawson. Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/50485 ) Change subject: soc/amd/*/smihandler: remove replace southbridge references with fch ...................................................................... soc/amd/*/smihandler: remove replace southbridge references with fch Change-Id: I96fc8082263800b731f1d4d9ecdc8a99c28bff32 Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> --- M src/soc/amd/picasso/smihandler.c M src/soc/amd/stoneyridge/smihandler.c 2 files changed, 8 insertions(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/85/50485/1 diff --git a/src/soc/amd/picasso/smihandler.c b/src/soc/amd/picasso/smihandler.c index 928669d..735fd77 100644 --- a/src/soc/amd/picasso/smihandler.c +++ b/src/soc/amd/picasso/smihandler.c @@ -97,7 +97,7 @@ io_smi->rax = smmstore_exec(sub_command, (void *)reg_ebx); } -static void sb_apmc_smi_handler(void) +static void fch_apmc_smi_handler(void) { const uint8_t cmd = inb(pm_acpi_smi_cmd_port()); @@ -124,7 +124,7 @@ mainboard_smi_apmc(cmd); } -static void sb_slp_typ_handler(void) +static void fch_slp_typ_handler(void) { uint32_t pci_ctrl, reg32; uint16_t pm1cnt, reg16; @@ -219,8 +219,8 @@ * in fch.c is unrelated to this list. */ static const struct smi_sources_t smi_sources[] = { - { .type = SMITYPE_SMI_CMD_PORT, .handler = sb_apmc_smi_handler }, - { .type = SMITYPE_SLP_TYP, .handler = sb_slp_typ_handler}, + { .type = SMITYPE_SMI_CMD_PORT, .handler = fch_apmc_smi_handler }, + { .type = SMITYPE_SLP_TYP, .handler = fch_slp_typ_handler}, }; void *get_smi_source_handler(int source) diff --git a/src/soc/amd/stoneyridge/smihandler.c b/src/soc/amd/stoneyridge/smihandler.c index 0b0f5c1..3a65f55 100644 --- a/src/soc/amd/stoneyridge/smihandler.c +++ b/src/soc/amd/stoneyridge/smihandler.c @@ -95,7 +95,7 @@ io_smi->rax = smmstore_exec(sub_command, (void *)reg_ebx); } -static void sb_apmc_smi_handler(void) +static void fch_apmc_smi_handler(void) { const uint8_t cmd = inb(pm_acpi_smi_cmd_port()); @@ -119,7 +119,7 @@ mainboard_smi_apmc(cmd); } -static void sb_slp_typ_handler(void) +static void fch_slp_typ_handler(void) { uint32_t pci_ctrl, reg32; uint16_t pm1cnt, reg16; @@ -214,8 +214,8 @@ * in southbridge.c is unrelated to this list. */ static const struct smi_sources_t smi_sources[] = { - { .type = SMITYPE_SMI_CMD_PORT, .handler = sb_apmc_smi_handler }, - { .type = SMITYPE_SLP_TYP, .handler = sb_slp_typ_handler}, + { .type = SMITYPE_SMI_CMD_PORT, .handler = fch_apmc_smi_handler }, + { .type = SMITYPE_SLP_TYP, .handler = fch_slp_typ_handler}, }; void *get_smi_source_handler(int source) -- To view, visit https://review.coreboot.org/c/coreboot/+/50485 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I96fc8082263800b731f1d4d9ecdc8a99c28bff32 Gerrit-Change-Number: 50485 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/amd/cezanne/chip: set device operations for UART MMIO devices
by Felix Held (Code Review) 10 Feb '21

10 Feb '21

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Change in coreboot[master]: soc/amd/cezanne: add empty mp_init_cpus
by Felix Held (Code Review) 10 Feb '21

10 Feb '21

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Change in coreboot[master]: soc/amd/cezanne/cpu: add basic zen_2_3_init functionality
by Felix Held (Code Review) 10 Feb '21

10 Feb '21

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Change in coreboot[master]: [WIP] soc/amd/cezanne: select ACPI support and make the compiler happy
by Felix Held (Code Review) 10 Feb '21

10 Feb '21

Attention is currently required from: Jason Glenesk, Raul Rangel, Martin Roth, Marshall Dawson. Hello build bot (Jenkins), Jason Glenesk, Raul Rangel, Patrick Georgi, Martin Roth, Marshall Dawson, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/50273 to look at the new patch set (#3). Change subject: [WIP] soc/amd/cezanne: select ACPI support and make the compiler happy ...................................................................... [WIP] soc/amd/cezanne: select ACPI support and make the compiler happy This isn't meant to be submitted in the current state. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I9b806569154e46418fa7d4fa35575a0acfec9132 --- A src/mainboard/amd/majolica/dsdt.asl A src/mainboard/google/guybrush/dsdt.asl M src/soc/amd/cezanne/Kconfig M src/soc/amd/cezanne/Makefile.inc A src/soc/amd/cezanne/acpi.c 5 files changed, 82 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/73/50273/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/50273 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9b806569154e46418fa7d4fa35575a0acfec9132 Gerrit-Change-Number: 50273 Gerrit-PatchSet: 3 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/google/zork/var/shuboz: Modify touchpad setting for Jelboz
by Martin Roth (Code Review) 10 Feb '21

10 Feb '21

Martin Roth has submitted this change. ( https://review.coreboot.org/c/coreboot/+/49742 ) Change subject: mb/google/zork/var/shuboz: Modify touchpad setting for Jelboz ...................................................................... mb/google/zork/var/shuboz: Modify touchpad setting for Jelboz Since Jelboz support number pad, due to one single coreboot for both Jelboz and Shuboz, modify "overridetree.cb" setting to number pad support for Jelboz. BUG=b:174964012 BRANCH=master TEST=emerge-zork coreboot chromeos-bootimage Signed-off-by: Kane Chen <kane_chen(a)pegatron.corp-partner.google.com> Change-Id: Ie0219419834b34b6eac589f28d3604f5f1b65679 Reviewed-on: https://review.coreboot.org/c/coreboot/+/49742 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Kangheui Won <khwon(a)chromium.org> --- M src/mainboard/google/zork/variants/shuboz/overridetree.cb 1 file changed, 8 insertions(+), 7 deletions(-) Approvals: build bot (Jenkins): Verified Kane Chen: Looks good to me, but someone else must approve Kangheui Won: Looks good to me, approved diff --git a/src/mainboard/google/zork/variants/shuboz/overridetree.cb b/src/mainboard/google/zork/variants/shuboz/overridetree.cb index 7160899..65d3692 100644 --- a/src/mainboard/google/zork/variants/shuboz/overridetree.cb +++ b/src/mainboard/google/zork/variants/shuboz/overridetree.cb @@ -58,13 +58,14 @@ register "has_power_resource" = "1" device i2c 10 on end end - chip drivers/i2c/generic - register "hid" = ""ELAN0000"" - register "desc" = ""ELAN Touchpad"" - register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_LOW(GPIO_9)" - register "wake" = "GEVENT_22" - register "probed" = "1" - device i2c 15 on end + chip drivers/i2c/hid + register "generic.hid" = ""ELAN2702"" + register "generic.desc" = ""ELAN Touchpad"" + register "generic.irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPIO_9)" + register "generic.wake" = "GEVENT_22" + register "generic.probed" = "1" + register "hid_desc_reg_offset" = "0x01" + device i2c 15 on end end end # device end # chip soc/amd/picasso -- To view, visit https://review.coreboot.org/c/coreboot/+/49742 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie0219419834b34b6eac589f28d3604f5f1b65679 Gerrit-Change-Number: 49742 Gerrit-PatchSet: 15 Gerrit-Owner: Kane Chen <kane_chen(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Bhanu Prakash Maiya <bhanumaiya(a)google.com> Gerrit-Reviewer: Eric Peers <epeers(a)google.com> Gerrit-Reviewer: Kane Chen <kane_chen(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com> Gerrit-CC: Hank Lin <hank2_lin(a)pegatron.corp-partner.google.com> Gerrit-CC: Ken Lu <ken_lu(a)pegatron.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-CC: Randy I-Fan Wang <ifanw(a)google.com> Gerrit-MessageType: merged

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Change in coreboot[master]: intel/broadwell,lynxpoint: Use HTPS() for HPET visibility
by Kyösti Mälkki (Code Review) 10 Feb '21

10 Feb '21

Attention is currently required from: Patrick Rudolph. Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49485 ) Change subject: intel/broadwell,lynxpoint: Use HTPS() for HPET visibility ...................................................................... Patch Set 2: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/49485/comment/b98b9d55_8092a5a6 PS2, Line 7: intel/broadwell,lynxpoint: Use HTPS() for HPET visibility HPTS -- To view, visit https://review.coreboot.org/c/coreboot/+/49485 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5f030b156355ea407d37cdb2eda8a3161085436f Gerrit-Change-Number: 49485 Gerrit-PatchSet: 2 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Wed, 10 Feb 2021 15:48:06 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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coreboot-gerrit February 2021