coreboot-gerrit February 2021

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Change in coreboot[master]: drivers/spi: Stop using a variable-length array
by Angel Pons (Code Review) 10 Feb '21

10 Feb '21

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/50480 ) Change subject: drivers/spi: Stop using a variable-length array ...................................................................... drivers/spi: Stop using a variable-length array Only the call in `spi_flash_cmd_write_page_program` uses non-constant values for the array length. However, the value for `data_len` has an upper bound: `flash->page_size` is set to `1U << vi->page_size_shift` which depends on the flash chip vendor info, and the largest value it can currently have is 8. Define this number in a macro, and use it to allocate a fixed buffer. Also add an overflow check to guard against buffer overflow problems. Tested on Asrock B85M Pro4, MRC cache is still working. Change-Id: Ib630bff1b496bc276616989d4506a3c96f242e26 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/drivers/spi/adesto.c M src/drivers/spi/amic.c M src/drivers/spi/atmel.c M src/drivers/spi/eon.c M src/drivers/spi/gigadevice.c M src/drivers/spi/macronix.c M src/drivers/spi/spansion.c M src/drivers/spi/spi_flash.c M src/drivers/spi/spi_flash_internal.h M src/drivers/spi/sst.c M src/drivers/spi/stmicro.c M src/drivers/spi/winbond.c 12 files changed, 22 insertions(+), 23 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/80/50480/1 diff --git a/src/drivers/spi/adesto.c b/src/drivers/spi/adesto.c index 6538905..aa31d92 100644 --- a/src/drivers/spi/adesto.c +++ b/src/drivers/spi/adesto.c @@ -91,7 +91,7 @@ const struct spi_flash_vendor_info spi_flash_adesto_vi = { .id = VENDOR_ID_ADESTO, - .page_size_shift = 8, + .page_size_shift = DEFAULT_PAGE_SIZE_SHIFT, .sector_size_kib_shift = 2, .match_id_mask[0] = 0xffff, .ids = flash_table, diff --git a/src/drivers/spi/amic.c b/src/drivers/spi/amic.c index 5e74616..40d11ba 100644 --- a/src/drivers/spi/amic.c +++ b/src/drivers/spi/amic.c @@ -71,7 +71,7 @@ const struct spi_flash_vendor_info spi_flash_amic_vi = { .id = VENDOR_ID_AMIC, - .page_size_shift = 8, + .page_size_shift = DEFAULT_PAGE_SIZE_SHIFT, .sector_size_kib_shift = 2, .match_id_mask[0] = 0xffff, .ids = flash_table, diff --git a/src/drivers/spi/atmel.c b/src/drivers/spi/atmel.c index 4dcc5b5..c8a7b0e 100644 --- a/src/drivers/spi/atmel.c +++ b/src/drivers/spi/atmel.c @@ -61,7 +61,7 @@ const struct spi_flash_vendor_info spi_flash_atmel_vi = { .id = VENDOR_ID_ATMEL, - .page_size_shift = 8, + .page_size_shift = DEFAULT_PAGE_SIZE_SHIFT, .sector_size_kib_shift = 2, .match_id_mask[0] = 0xffff, .ids = flash_table, diff --git a/src/drivers/spi/eon.c b/src/drivers/spi/eon.c index 1212c6b..89b6318 100644 --- a/src/drivers/spi/eon.c +++ b/src/drivers/spi/eon.c @@ -152,7 +152,7 @@ const struct spi_flash_vendor_info spi_flash_eon_vi = { .id = VENDOR_ID_EON, - .page_size_shift = 8, + .page_size_shift = DEFAULT_PAGE_SIZE_SHIFT, .sector_size_kib_shift = 2, .match_id_mask[0] = 0xffff, .ids = flash_table, diff --git a/src/drivers/spi/gigadevice.c b/src/drivers/spi/gigadevice.c index 6c5a167..dabfd6a 100644 --- a/src/drivers/spi/gigadevice.c +++ b/src/drivers/spi/gigadevice.c @@ -103,7 +103,7 @@ const struct spi_flash_vendor_info spi_flash_gigadevice_vi = { .id = VENDOR_ID_GIGADEVICE, - .page_size_shift = 8, + .page_size_shift = DEFAULT_PAGE_SIZE_SHIFT, .sector_size_kib_shift = 2, .match_id_mask[0] = 0xffff, .ids = flash_table, diff --git a/src/drivers/spi/macronix.c b/src/drivers/spi/macronix.c index f3f7e2d..4485752 100644 --- a/src/drivers/spi/macronix.c +++ b/src/drivers/spi/macronix.c @@ -123,7 +123,7 @@ const struct spi_flash_vendor_info spi_flash_macronix_vi = { .id = VENDOR_ID_MACRONIX, - .page_size_shift = 8, + .page_size_shift = DEFAULT_PAGE_SIZE_SHIFT, .sector_size_kib_shift = 2, .match_id_mask[0] = 0xffff, .ids = flash_table, diff --git a/src/drivers/spi/spansion.c b/src/drivers/spi/spansion.c index fe0e265..ee4b8ed 100644 --- a/src/drivers/spi/spansion.c +++ b/src/drivers/spi/spansion.c @@ -117,7 +117,7 @@ const struct spi_flash_vendor_info spi_flash_spansion_ext1_vi = { .id = VENDOR_ID_SPANSION, - .page_size_shift = 8, + .page_size_shift = DEFAULT_PAGE_SIZE_SHIFT, .sector_size_kib_shift = 6, .match_id_mask[0] = 0xffff, .match_id_mask[1] = 0xffff, @@ -128,7 +128,7 @@ const struct spi_flash_vendor_info spi_flash_spansion_ext2_vi = { .id = VENDOR_ID_SPANSION, - .page_size_shift = 8, + .page_size_shift = DEFAULT_PAGE_SIZE_SHIFT, .sector_size_kib_shift = 8, .match_id_mask[0] = 0xffff, .match_id_mask[1] = 0xffff, @@ -139,7 +139,7 @@ const struct spi_flash_vendor_info spi_flash_spansion_vi = { .id = VENDOR_ID_SPANSION, - .page_size_shift = 8, + .page_size_shift = DEFAULT_PAGE_SIZE_SHIFT, .sector_size_kib_shift = 6, .match_id_mask[0] = 0xffff, .ids = flash_table, diff --git a/src/drivers/spi/spi_flash.c b/src/drivers/spi/spi_flash.c index b674749..aa0da70 100644 --- a/src/drivers/spi/spi_flash.c +++ b/src/drivers/spi/spi_flash.c @@ -88,17 +88,15 @@ return ret; } -/* TODO: This code is quite possibly broken and overflowing stacks. Fix ASAP! */ -#pragma GCC diagnostic push -#if defined(__GNUC__) && !defined(__clang__) -#pragma GCC diagnostic ignored "-Wstack-usage=" -#endif -#pragma GCC diagnostic ignored "-Wvla" int spi_flash_cmd_write(const struct spi_slave *spi, const u8 *cmd, size_t cmd_len, const void *data, size_t data_len) { int ret; - u8 buff[cmd_len + data_len]; + u8 buff[4 + (1 << DEFAULT_PAGE_SIZE_SHIFT)]; + + if (ARRAY_SIZE(buff) < cmd_len + data_len) + return -1; + memcpy(buff, cmd, cmd_len); memcpy(buff + cmd_len, data, data_len); @@ -110,7 +108,6 @@ return ret; } -#pragma GCC diagnostic pop /* Perform the read operation honoring spi controller fifo size, reissuing * the read command until the full request completed. */ diff --git a/src/drivers/spi/spi_flash_internal.h b/src/drivers/spi/spi_flash_internal.h index b4d39b3..e656498 100644 --- a/src/drivers/spi/spi_flash_internal.h +++ b/src/drivers/spi/spi_flash_internal.h @@ -24,6 +24,8 @@ /* Common status */ #define STATUS_WIP 0x01 +#define DEFAULT_PAGE_SIZE_SHIFT 8 + /* Send a single-byte command to the device and read the response */ int spi_flash_cmd(const struct spi_slave *spi, u8 cmd, void *response, size_t len); diff --git a/src/drivers/spi/sst.c b/src/drivers/spi/sst.c index 887380f..8c20a3e 100644 --- a/src/drivers/spi/sst.c +++ b/src/drivers/spi/sst.c @@ -250,7 +250,7 @@ const struct spi_flash_vendor_info spi_flash_sst_vi = { .id = VENDOR_ID_SST, - .page_size_shift = 8, + .page_size_shift = DEFAULT_PAGE_SIZE_SHIFT, .sector_size_kib_shift = 2, .match_id_mask[0] = 0xff, .ids = flash_table_pp256, diff --git a/src/drivers/spi/stmicro.c b/src/drivers/spi/stmicro.c index 4cd8c1b..4fb0569 100644 --- a/src/drivers/spi/stmicro.c +++ b/src/drivers/spi/stmicro.c @@ -213,7 +213,7 @@ const struct spi_flash_vendor_info spi_flash_stmicro1_vi = { .id = VENDOR_ID_STMICRO, - .page_size_shift = 8, + .page_size_shift = DEFAULT_PAGE_SIZE_SHIFT, .sector_size_kib_shift = 5, .match_id_mask[0] = 0xffff, .ids = flash_table_se32k, @@ -223,7 +223,7 @@ const struct spi_flash_vendor_info spi_flash_stmicro2_vi = { .id = VENDOR_ID_STMICRO, - .page_size_shift = 8, + .page_size_shift = DEFAULT_PAGE_SIZE_SHIFT, .sector_size_kib_shift = 6, .match_id_mask[0] = 0xffff, .ids = flash_table_se64k, @@ -233,7 +233,7 @@ const struct spi_flash_vendor_info spi_flash_stmicro3_vi = { .id = VENDOR_ID_STMICRO, - .page_size_shift = 8, + .page_size_shift = DEFAULT_PAGE_SIZE_SHIFT, .sector_size_kib_shift = 8, .match_id_mask[0] = 0xffff, .ids = flash_table_se256k, @@ -243,7 +243,7 @@ const struct spi_flash_vendor_info spi_flash_stmicro4_vi = { .id = VENDOR_ID_STMICRO, - .page_size_shift = 8, + .page_size_shift = DEFAULT_PAGE_SIZE_SHIFT, .sector_size_kib_shift = 2, .match_id_mask[0] = 0xffff, .ids = flash_table_sse, diff --git a/src/drivers/spi/winbond.c b/src/drivers/spi/winbond.c index e4151de..e3cc33d 100644 --- a/src/drivers/spi/winbond.c +++ b/src/drivers/spi/winbond.c @@ -533,7 +533,7 @@ const struct spi_flash_vendor_info spi_flash_winbond_vi = { .id = VENDOR_ID_WINBOND, - .page_size_shift = 8, + .page_size_shift = DEFAULT_PAGE_SIZE_SHIFT, .sector_size_kib_shift = 2, .match_id_mask[0] = 0xffff, .ids = flash_table, -- To view, visit https://review.coreboot.org/c/coreboot/+/50480 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib630bff1b496bc276616989d4506a3c96f242e26 Gerrit-Change-Number: 50480 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: device/azalia_device: Add function to program a verb table
by 9elements QA (Code Review) 10 Feb '21

10 Feb '21

9elements QA has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50387 ) Change subject: device/azalia_device: Add function to program a verb table ...................................................................... Patch Set 2: Automatic boot test returned (PASS/FAIL/TOTAL): 8/1/9 "ThinkPad T500" (x86_32) using payload SeaBIOS : SUCCESS : https://lava.9esec.io/r/42319 "HP Z220 SFF Workstation" (x86_32) using payload LinuxBoot_BusyBox_kexec : FAIL : https://lava.9esec.io/r/42318 "HP Compaq 8200 Elite SFF PC" (x86_32) using payload TianoCore : SUCCESS : https://lava.9esec.io/r/42317 "HP Compaq 8200 Elite SFF PC" (x86_32) using payload SeaBIOS : SUCCESS : https://lava.9esec.io/r/42316 "QEMU x86 q35/ich9" (x86_32) using payload TianoCore : SUCCESS : https://lava.9esec.io/r/42315 "QEMU x86 q35/ich9" (x86_32) using payload SeaBIOS : SUCCESS : https://lava.9esec.io/r/42314 "QEMU x86 i440fx/piix4" (x86_64) using payload SeaBIOS : SUCCESS : https://lava.9esec.io/r/42313 "QEMU x86 i440fx/piix4" (x86_32) using payload SeaBIOS : SUCCESS : https://lava.9esec.io/r/42312 "QEMU AArch64" using payload LinuxBoot_u-root_kexec : SUCCESS : https://lava.9esec.io/r/42311 Please note: This test is under development and might not be accurate at all! -- To view, visit https://review.coreboot.org/c/coreboot/+/50387 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie9607f6e733df66f0ca26a4bb70e0864ce1d4512 Gerrit-Change-Number: 50387 Gerrit-PatchSet: 2 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-Comment-Date: Wed, 10 Feb 2021 15:19:32 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: nb/intel/x4x: Correct DDR3 turnaround table
by 9elements QA (Code Review) 10 Feb '21

10 Feb '21

9elements QA has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49388 ) Change subject: nb/intel/x4x: Correct DDR3 turnaround table ...................................................................... Patch Set 3: Automatic boot test returned (PASS/FAIL/TOTAL): 8/1/9 "ThinkPad T500" (x86_32) using payload SeaBIOS : FAIL : https://lava.9esec.io/r/42301 "HP Z220 SFF Workstation" (x86_32) using payload LinuxBoot_BusyBox_kexec : SUCCESS : https://lava.9esec.io/r/42300 "HP Compaq 8200 Elite SFF PC" (x86_32) using payload TianoCore : SUCCESS : https://lava.9esec.io/r/42299 "HP Compaq 8200 Elite SFF PC" (x86_32) using payload SeaBIOS : SUCCESS : https://lava.9esec.io/r/42298 "QEMU x86 q35/ich9" (x86_32) using payload TianoCore : SUCCESS : https://lava.9esec.io/r/42297 "QEMU x86 q35/ich9" (x86_32) using payload SeaBIOS : SUCCESS : https://lava.9esec.io/r/42296 "QEMU x86 i440fx/piix4" (x86_64) using payload SeaBIOS : SUCCESS : https://lava.9esec.io/r/42295 "QEMU x86 i440fx/piix4" (x86_32) using payload SeaBIOS : SUCCESS : https://lava.9esec.io/r/42294 "QEMU AArch64" using payload LinuxBoot_u-root_kexec : SUCCESS : https://lava.9esec.io/r/42293 Please note: This test is under development and might not be accurate at all! -- To view, visit https://review.coreboot.org/c/coreboot/+/49388 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2c99502b8f105c77098c888b024a4c3c2c8877d4 Gerrit-Change-Number: 49388 Gerrit-PatchSet: 3 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Damien Zammit Gerrit-Reviewer: Michael Büchler <michael.buechler(a)posteo.net> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Wed, 10 Feb 2021 14:49:08 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/amd/block/psp/psp: raise log level of PSP failure messages
by Felix Held (Code Review) 10 Feb '21

10 Feb '21

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/50414 ) Change subject: soc/amd/block/psp/psp: raise log level of PSP failure messages ...................................................................... soc/amd/block/psp/psp: raise log level of PSP failure messages If the PSP didn't like a command this should be at least a warning on the console and not just a debug message. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: If7e5f6320631cca86813e98f82b8c0c21bf18af1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/50414 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/soc/amd/common/block/psp/psp.c 1 file changed, 1 insertion(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Marshall Dawson: Looks good to me, approved Angel Pons: Looks good to me, approved diff --git a/src/soc/amd/common/block/psp/psp.c b/src/soc/amd/common/block/psp/psp.c index 2787b73..45d64d8 100644 --- a/src/soc/amd/common/block/psp/psp.c +++ b/src/soc/amd/common/block/psp/psp.c @@ -50,7 +50,7 @@ printk(BIOS_DEBUG, "buffer status=0x%x ", rd_resp_sts(header)); if (cmd_status) - printk(BIOS_DEBUG, "%s\n", status_to_string(cmd_status)); + printk(BIOS_WARNING, "%s\n", status_to_string(cmd_status)); else printk(BIOS_DEBUG, "OK\n"); } -- To view, visit https://review.coreboot.org/c/coreboot/+/50414 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If7e5f6320631cca86813e98f82b8c0c21bf18af1 Gerrit-Change-Number: 50414 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: sb/intel/lynxpoint: Do not mask out TCO status bits
by Angel Pons (Code Review) 10 Feb '21

10 Feb '21

Attention is currently required from: Patrick Rudolph. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50478 ) Change subject: sb/intel/lynxpoint: Do not mask out TCO status bits ...................................................................... Patch Set 1: (1 comment) File src/southbridge/intel/lynxpoint/pmutil.c: https://review.coreboot.org/c/coreboot/+/50478/comment/7283b08b_f337d838 PS1, Line 314: tco_sts > Yeah, but it's not really an issue. We only handle BIOSWR_STS and TIMEOUT. I checked the datasheet, and the TCOx_STS/TCOx_EN bits don't match at all. The masking that the code originally did makes no sense. Plus, we don't enable TCO SMI generation right now. Currently, this change has no effect. -- To view, visit https://review.coreboot.org/c/coreboot/+/50478 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I49abb5a4a99e943e57e0aaa6f06ff63bdf957cd3 Gerrit-Change-Number: 50478 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Comment-Date: Wed, 10 Feb 2021 14:43:42 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Patrick Rudolph <patrick.rudolph(a)9elements.com> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

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Change in coreboot[master]: sb/intel/lynxpoint: Do not mask out TCO status bits
by Angel Pons (Code Review) 10 Feb '21

10 Feb '21

Attention is currently required from: Patrick Rudolph. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50478 ) Change subject: sb/intel/lynxpoint: Do not mask out TCO status bits ...................................................................... Patch Set 1: (1 comment) File src/southbridge/intel/lynxpoint/pmutil.c: https://review.coreboot.org/c/coreboot/+/50478/comment/65d712d1_6d493c69 PS1, Line 314: tco_sts > there might be stale status bits set for events that were enabled but now they aren't Yeah, but it's not really an issue. We only handle BIOSWR_STS and TIMEOUT. -- To view, visit https://review.coreboot.org/c/coreboot/+/50478 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I49abb5a4a99e943e57e0aaa6f06ff63bdf957cd3 Gerrit-Change-Number: 50478 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Comment-Date: Wed, 10 Feb 2021 14:37:43 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/amd: fully commonize clear_tvalid
by Felix Held (Code Review) 10 Feb '21

10 Feb '21

Attention is currently required from: Jason Glenesk, Raul Rangel, Martin Roth, Marshall Dawson, Felix Held. Hello build bot (Jenkins), Jason Glenesk, Raul Rangel, Patrick Georgi, Martin Roth, Marshall Dawson, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/50466 to look at the new patch set (#5). Change subject: soc/amd: fully commonize clear_tvalid ...................................................................... soc/amd: fully commonize clear_tvalid Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I90526a566a5fbc19a7368f90421067a6c716614e --- M src/soc/amd/common/block/cpu/noncar/memmap.c M src/soc/amd/common/block/cpu/smm/Makefile.inc A src/soc/amd/common/block/cpu/smm/smm_helper.c M src/soc/amd/common/block/include/amdblocks/smm.h M src/soc/amd/stoneyridge/memmap.c 5 files changed, 34 insertions(+), 44 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/66/50466/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/50466 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I90526a566a5fbc19a7368f90421067a6c716614e Gerrit-Change-Number: 50466 Gerrit-PatchSet: 5 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: sb/intel/lynxpoint: Do not mask out TCO status bits
by Patrick Rudolph (Code Review) 10 Feb '21

10 Feb '21

Attention is currently required from: Angel Pons. Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50478 ) Change subject: sb/intel/lynxpoint: Do not mask out TCO status bits ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/50478 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I49abb5a4a99e943e57e0aaa6f06ff63bdf957cd3 Gerrit-Change-Number: 50478 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Comment-Date: Wed, 10 Feb 2021 14:19:39 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: sb/intel/lynxpoint: Do not mask out TCO status bits
by Patrick Rudolph (Code Review) 10 Feb '21

10 Feb '21

Attention is currently required from: Angel Pons, Patrick Rudolph. Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50478 ) Change subject: sb/intel/lynxpoint: Do not mask out TCO status bits ...................................................................... Patch Set 1: (1 comment) File src/southbridge/intel/lynxpoint/pmutil.c: https://review.coreboot.org/c/coreboot/+/50478/comment/9398b179_a71e3d1d PS1, Line 314: tco_sts there might be stale status bits set for events that were enabled but now they aren't -- To view, visit https://review.coreboot.org/c/coreboot/+/50478 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I49abb5a4a99e943e57e0aaa6f06ff63bdf957cd3 Gerrit-Change-Number: 50478 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Wed, 10 Feb 2021 14:19:33 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: sb/intel/x/lpc.c: Drop `pch_disable_smm_only_flashing`
by Patrick Rudolph (Code Review) 10 Feb '21

10 Feb '21

Attention is currently required from: Angel Pons. Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50479 ) Change subject: sb/intel/x/lpc.c: Drop `pch_disable_smm_only_flashing` ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/50479 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7ce0ca584cd3d42a10cdb74f45742f1eadc01bfa Gerrit-Change-Number: 50479 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Comment-Date: Wed, 10 Feb 2021 14:16:52 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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coreboot-gerrit February 2021