coreboot-gerrit February 2021

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: soc/amd/common/block: Fix guards for PSP transfer buffer
by Martin Roth (Code Review) 10 Feb '21

10 Feb '21

Attention is currently required from: Jason Glenesk, Raul Rangel, Marshall Dawson, Julius Werner. Martin Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50403 ) Change subject: soc/amd/common/block: Fix guards for PSP transfer buffer ...................................................................... Patch Set 1: (1 comment) File src/soc/amd/common/block/cpu/noncar/memlayout_transfer_buffer.inc: https://review.coreboot.org/c/coreboot/+/50403/comment/184df5a2_e0328d7e PS1, Line 9: #if CONFIG(VBOOT_STARTS_BEFORE_BOOTBLOCK) || CONFIG(VBOOT_STARTS_IN_BOOTBLOCK) > You are right, VBOOT_STARTS_IN_ROMSTAGE is the only other option. […] It accomplishes the same thing. I think this is fine. -- To view, visit https://review.coreboot.org/c/coreboot/+/50403 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I444bede3f2b716e1900e7621453351d7fddadaa3 Gerrit-Change-Number: 50403 Gerrit-PatchSet: 1 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Comment-Date: Wed, 10 Feb 2021 16:23:48 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Raul Rangel <rrangel(a)chromium.org> Comment-In-Reply-To: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/zork: modify ELAN TS i2c IRQ to LEVEL active for dirinboz
by Martin Roth (Code Review) 10 Feb '21

10 Feb '21

Martin Roth has submitted this change. ( https://review.coreboot.org/c/coreboot/+/50416 ) Change subject: mb/google/zork: modify ELAN TS i2c IRQ to LEVEL active for dirinboz ...................................................................... mb/google/zork: modify ELAN TS i2c IRQ to LEVEL active for dirinboz EDGE IRQ from TS might be invalid to HOST, configure IRQs as level triggered to prevent TS lost. BUG=b:179594439 BRANCH=zork TEST=1. emerge-zork coreboot chromeos-bootimage 2. power on, suspend DUT to check TS is functional Change-Id: Ibbbc73b37932ba1359ffe6f572a15564bb341025 Signed-off-by: Kevin Chiu <kevin.chiu(a)quantatw.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50416 Reviewed-by: Kangheui Won <khwon(a)chromium.org> Reviewed-by: Sam McNally <sammc(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/google/zork/variants/dirinboz/overridetree.cb 1 file changed, 1 insertion(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Kangheui Won: Looks good to me, approved Sam McNally: Looks good to me, approved diff --git a/src/mainboard/google/zork/variants/dirinboz/overridetree.cb b/src/mainboard/google/zork/variants/dirinboz/overridetree.cb index 1bfea1d..283b1fc 100644 --- a/src/mainboard/google/zork/variants/dirinboz/overridetree.cb +++ b/src/mainboard/google/zork/variants/dirinboz/overridetree.cb @@ -120,7 +120,7 @@ register "hid" = ""ELAN0001"" register "desc" = ""ELAN Touchscreen"" register "probed" = "1" - register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_LOW(GPIO_12)" + register "irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPIO_12)" register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_32)" register "enable_delay_ms" = "1" register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPIO_140)" -- To view, visit https://review.coreboot.org/c/coreboot/+/50416 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibbbc73b37932ba1359ffe6f572a15564bb341025 Gerrit-Change-Number: 50416 Gerrit-PatchSet: 6 Gerrit-Owner: Kevin Chiu <kevin.chiu.17802(a)gmail.com> Gerrit-Reviewer: Bhanu Prakash Maiya <bhanumaiya(a)google.com> Gerrit-Reviewer: Eric Peers <epeers(a)google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Sam McNally <sammc(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/amd/common/block/cpu/noncar: Remove unneeded whitespace before tab
by Martin Roth (Code Review) 10 Feb '21

10 Feb '21

Martin Roth has submitted this change. ( https://review.coreboot.org/c/coreboot/+/50434 ) Change subject: soc/amd/common/block/cpu/noncar: Remove unneeded whitespace before tab ...................................................................... soc/amd/common/block/cpu/noncar: Remove unneeded whitespace before tab Change-Id: Ib88358ca26876cd25247cd9619fb2b70f6859ac2 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50434 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Frans Hendriks <fhendriks(a)eltan.com> Reviewed-by: Felix Held <felix-coreboot(a)felixheld.de> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/soc/amd/common/block/cpu/noncar/memlayout_transfer_buffer.inc 1 file changed, 1 insertion(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Felix Held: Looks good to me, approved Frans Hendriks: Looks good to me, approved Angel Pons: Looks good to me, approved diff --git a/src/soc/amd/common/block/cpu/noncar/memlayout_transfer_buffer.inc b/src/soc/amd/common/block/cpu/noncar/memlayout_transfer_buffer.inc index d9bd096..1b80f6b 100644 --- a/src/soc/amd/common/block/cpu/noncar/memlayout_transfer_buffer.inc +++ b/src/soc/amd/common/block/cpu/noncar/memlayout_transfer_buffer.inc @@ -11,7 +11,7 @@ ALIGN_COUNTER(64) PRERAM_CBMEM_CONSOLE(., CONFIG_PRERAM_CBMEM_CONSOLE_SIZE) - TIMESTAMP(., TIMESTAMP_BUFFER_SIZE) + TIMESTAMP(., TIMESTAMP_BUFFER_SIZE) CBFS_MCACHE(., CONFIG_CBFS_MCACHE_SIZE) FMAP_CACHE(., FMAP_SIZE) -- To view, visit https://review.coreboot.org/c/coreboot/+/50434 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib88358ca26876cd25247cd9619fb2b70f6859ac2 Gerrit-Change-Number: 50434 Gerrit-PatchSet: 2 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/google/zork/var/shuboz: Adjust touchscreen settings
by Martin Roth (Code Review) 10 Feb '21

10 Feb '21

Martin Roth has submitted this change. ( https://review.coreboot.org/c/coreboot/+/50228 ) Change subject: mb/google/zork/var/shuboz: Adjust touchscreen settings ...................................................................... mb/google/zork/var/shuboz: Adjust touchscreen settings Modify GPIO_140 delay time and add "disable_gpio_export_in_crs" to meet touchscreen controller power on sequence. BUG=b:174442484 BRANCH=master TEST=emerge-zork coreboot chromeos-bootimage Signed-off-by: Kane Chen <kane_chen(a)pegatron.corp-partner.google.com> Change-Id: I36a7055b7be0963479f8a0f4dc49c92bc8fbdc9d Reviewed-on: https://review.coreboot.org/c/coreboot/+/50228 Reviewed-by: Martin Roth <martinroth(a)google.com> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/google/zork/variants/shuboz/overridetree.cb 1 file changed, 2 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Martin Roth: Looks good to me, approved Angel Pons: Looks good to me, but someone else must approve Kane Chen: Looks good to me, but someone else must approve diff --git a/src/mainboard/google/zork/variants/shuboz/overridetree.cb b/src/mainboard/google/zork/variants/shuboz/overridetree.cb index 65d3692..436f0ed 100644 --- a/src/mainboard/google/zork/variants/shuboz/overridetree.cb +++ b/src/mainboard/google/zork/variants/shuboz/overridetree.cb @@ -54,8 +54,9 @@ register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_32)" register "enable_delay_ms" = "1" register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPIO_140)" - register "reset_delay_ms" = "20" + register "reset_delay_ms" = "300" register "has_power_resource" = "1" + register "disable_gpio_export_in_crs" = "1" device i2c 10 on end end chip drivers/i2c/hid -- To view, visit https://review.coreboot.org/c/coreboot/+/50228 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I36a7055b7be0963479f8a0f4dc49c92bc8fbdc9d Gerrit-Change-Number: 50228 Gerrit-PatchSet: 5 Gerrit-Owner: Kane Chen <kane_chen(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Bhanu Prakash Maiya <bhanumaiya(a)google.com> Gerrit-Reviewer: Kane Chen <kane_chen(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com> Gerrit-CC: Hank Lin <hank2_lin(a)pegatron.corp-partner.google.com> Gerrit-CC: Ken Lu <ken_lu(a)pegatron.corp-partner.google.com> Gerrit-CC: Randy I-Fan Wang <ifanw(a)google.com> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/google/zork/var/shuboz: Adjust touchscreen settings
by Martin Roth (Code Review) 10 Feb '21

10 Feb '21

Attention is currently required from: Kane Chen. Martin Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50228 ) Change subject: mb/google/zork/var/shuboz: Adjust touchscreen settings ...................................................................... Patch Set 4: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/50228 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I36a7055b7be0963479f8a0f4dc49c92bc8fbdc9d Gerrit-Change-Number: 50228 Gerrit-PatchSet: 4 Gerrit-Owner: Kane Chen <kane_chen(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Bhanu Prakash Maiya <bhanumaiya(a)google.com> Gerrit-Reviewer: Kane Chen <kane_chen(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com> Gerrit-CC: Hank Lin <hank2_lin(a)pegatron.corp-partner.google.com> Gerrit-CC: Ken Lu <ken_lu(a)pegatron.corp-partner.google.com> Gerrit-CC: Randy I-Fan Wang <ifanw(a)google.com> Gerrit-Attention: Kane Chen <kane_chen(a)pegatron.corp-partner.google.com> Gerrit-Comment-Date: Wed, 10 Feb 2021 16:18:59 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/amd/picasso/smihandler: replace southbridge.c in comment with fch.c
by Martin Roth (Code Review) 10 Feb '21

10 Feb '21

Martin Roth has submitted this change. ( https://review.coreboot.org/c/coreboot/+/50458 ) Change subject: soc/amd/picasso/smihandler: replace southbridge.c in comment with fch.c ...................................................................... soc/amd/picasso/smihandler: replace southbridge.c in comment with fch.c southbridge.c was renamed and split into early_fch.c and fch.c. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: Ie439e746fb3dfe9ec865481a76a09eab378242bb Reviewed-on: https://review.coreboot.org/c/coreboot/+/50458 Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> Reviewed-by: Raul Rangel <rrangel(a)chromium.org> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/amd/picasso/smihandler.c 1 file changed, 1 insertion(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Raul Rangel: Looks good to me, approved Angel Pons: Looks good to me, approved diff --git a/src/soc/amd/picasso/smihandler.c b/src/soc/amd/picasso/smihandler.c index faf4f7b..d6c3ed0 100644 --- a/src/soc/amd/picasso/smihandler.c +++ b/src/soc/amd/picasso/smihandler.c @@ -226,7 +226,7 @@ /* * Table of functions supported in the SMI handler. Note that SMI source setup - * in southbridge.c is unrelated to this list. + * in fch.c is unrelated to this list. */ static const struct smi_sources_t smi_sources[] = { { .type = SMITYPE_SMI_CMD_PORT, .handler = sb_apmc_smi_handler }, -- To view, visit https://review.coreboot.org/c/coreboot/+/50458 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie439e746fb3dfe9ec865481a76a09eab378242bb Gerrit-Change-Number: 50458 Gerrit-PatchSet: 4 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/amd/cezanne/fch: add HAVE_SMI_HANDLER case to fch_init_acpi_ports
by Martin Roth (Code Review) 10 Feb '21

10 Feb '21

Attention is currently required from: Jason Glenesk, Raul Rangel, Marshall Dawson, Felix Held. Martin Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50454 ) Change subject: soc/amd/cezanne/fch: add HAVE_SMI_HANDLER case to fch_init_acpi_ports ...................................................................... Patch Set 3: (1 comment) File src/soc/amd/cezanne/fch.c: https://review.coreboot.org/c/coreboot/+/50454/comment/27b69513_3f566926 PS3, Line 28: : /* : * SMI on SlpTyp requires sending SMI before completion : * response of the I/O write. The BKDG also specifies : * clearing ForceStpClkRetry for SMI trapping. : */ I don't understand how this comment relates to the following code. If we need to clear ForceStpClkRetry, why is it getting set? Where is the SMI that needs to be sent before the completion response? -- To view, visit https://review.coreboot.org/c/coreboot/+/50454 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie7bab29ae8d0e28c392210f8dcbaa4441ca61114 Gerrit-Change-Number: 50454 Gerrit-PatchSet: 3 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Wed, 10 Feb 2021 16:17:38 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: drivers/i2c/hid: Enforce level triggered IRQ mode
by Tim Wawrzynczak (Code Review) 10 Feb '21

10 Feb '21

Attention is currently required from: Furquan Shaikh, Angel Pons, Michael Niewöhner, Karthik Ramasubramanian. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50442 ) Change subject: drivers/i2c/hid: Enforce level triggered IRQ mode ...................................................................... Patch Set 3: (1 comment) File src/drivers/i2c/hid/hid.c: https://review.coreboot.org/c/coreboot/+/50442/comment/4210bf05_37a46463 PS3, Line 82: dev->enabled = 0; > It's the vendor's fault for making defective hardware. I believe a level-triggered pad should always catch any edge pulses as well; the other way around could cause problems, but I think if we just print a warning and possibly set the trigger type back to LEVEL, everything should still work, there shouldn't be any need to disable the device. -- To view, visit https://review.coreboot.org/c/coreboot/+/50442 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3245a9de6e88cd83528823251083e62288192f0d Gerrit-Change-Number: 50442 Gerrit-PatchSet: 3 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Wed, 10 Feb 2021 16:15:51 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Comment-In-Reply-To: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/amd/cezanne/chip: add empty set_mmio_dev_ops
by Felix Held (Code Review) 10 Feb '21

10 Feb '21

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/50439 ) Change subject: soc/amd/cezanne/chip: add empty set_mmio_dev_ops ...................................................................... soc/amd/cezanne/chip: add empty set_mmio_dev_ops Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I2ac5fcd17b6aed464a0d1e55f2860574501f7a8a Reviewed-on: https://review.coreboot.org/c/coreboot/+/50439 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Raul Rangel <rrangel(a)chromium.org> --- M src/soc/amd/cezanne/chip.c 1 file changed, 7 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Raul Rangel: Looks good to me, approved diff --git a/src/soc/amd/cezanne/chip.c b/src/soc/amd/cezanne/chip.c index 9a0ca6a..4aac2ec 100644 --- a/src/soc/amd/cezanne/chip.c +++ b/src/soc/amd/cezanne/chip.c @@ -17,6 +17,10 @@ .scan_bus = pci_domain_scan_bus, }; +static void set_mmio_dev_ops(struct device *dev) +{ +} + static void enable_dev(struct device *dev) { /* Set the operations if it is a special bus type */ @@ -27,6 +31,9 @@ case DEVICE_PATH_CPU_CLUSTER: dev->ops = &cpu_bus_ops; break; + case DEVICE_PATH_MMIO: + set_mmio_dev_ops(dev); + break; default: break; } -- To view, visit https://review.coreboot.org/c/coreboot/+/50439 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2ac5fcd17b6aed464a0d1e55f2860574501f7a8a Gerrit-Change-Number: 50439 Gerrit-PatchSet: 4 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/amd/cezanne/chip: add empty cpu_bus_ops
by Felix Held (Code Review) 10 Feb '21

10 Feb '21

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/50438 ) Change subject: soc/amd/cezanne/chip: add empty cpu_bus_ops ...................................................................... soc/amd/cezanne/chip: add empty cpu_bus_ops Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I658294c84d64c7de0ccfa74b0e830d787a3a42fe Reviewed-on: https://review.coreboot.org/c/coreboot/+/50438 Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> Reviewed-by: Raul Rangel <rrangel(a)chromium.org> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/amd/cezanne/chip.c 1 file changed, 8 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Raul Rangel: Looks good to me, approved Angel Pons: Looks good to me, approved diff --git a/src/soc/amd/cezanne/chip.c b/src/soc/amd/cezanne/chip.c index accd3e9..9a0ca6a 100644 --- a/src/soc/amd/cezanne/chip.c +++ b/src/soc/amd/cezanne/chip.c @@ -6,6 +6,11 @@ #include <types.h> #include "chip.h" +struct device_operations cpu_bus_ops = { + .read_resources = noop_read_resources, + .set_resources = noop_set_resources, +}; + static struct device_operations pci_domain_ops = { .read_resources = pci_domain_read_resources, .set_resources = pci_domain_set_resources, @@ -19,6 +24,9 @@ case DEVICE_PATH_DOMAIN: dev->ops = &pci_domain_ops; break; + case DEVICE_PATH_CPU_CLUSTER: + dev->ops = &cpu_bus_ops; + break; default: break; } -- To view, visit https://review.coreboot.org/c/coreboot/+/50438 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I658294c84d64c7de0ccfa74b0e830d787a3a42fe Gerrit-Change-Number: 50438 Gerrit-PatchSet: 4 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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coreboot-gerrit February 2021