coreboot-gerrit February 2021

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Change in coreboot[master]: sb/intel/x/lpc.c: Drop `pch_disable_smm_only_flashing`
by Angel Pons (Code Review) 10 Feb '21

10 Feb '21

Attention is currently required from: Patrick Rudolph. Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/50479 ) Change subject: sb/intel/x/lpc.c: Drop `pch_disable_smm_only_flashing` ...................................................................... sb/intel/x/lpc.c: Drop `pch_disable_smm_only_flashing` The southbridge common SPI support already does this. Tested on Asrock B85M Pro4, internal flashing and MRC cache still work. Change-Id: I7ce0ca584cd3d42a10cdb74f45742f1eadc01bfa Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/southbridge/intel/bd82x6x/lpc.c M src/southbridge/intel/ibexpeak/lpc.c M src/southbridge/intel/lynxpoint/lpc.c 3 files changed, 0 insertions(+), 30 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/79/50479/1 diff --git a/src/southbridge/intel/bd82x6x/lpc.c b/src/southbridge/intel/bd82x6x/lpc.c index d5d39f5..8bdaa5a 100644 --- a/src/southbridge/intel/bd82x6x/lpc.c +++ b/src/southbridge/intel/bd82x6x/lpc.c @@ -404,13 +404,6 @@ } } -static void pch_disable_smm_only_flashing(struct device *dev) -{ - printk(BIOS_SPEW, "Enabling BIOS updates outside of SMM... "); - - pci_and_config8(dev, BIOS_CNTL, ~(1 << 5)); -} - static void pch_fixups(struct device *dev) { /* Indicate DRAM init done for MRC S3 to know it can resume */ @@ -557,8 +550,6 @@ /* Interrupt 9 should be level triggered (SCI) */ i8259_configure_irq_trigger(9, 1); - pch_disable_smm_only_flashing(dev); - pch_set_acpi_mode(); pch_fixups(dev); diff --git a/src/southbridge/intel/ibexpeak/lpc.c b/src/southbridge/intel/ibexpeak/lpc.c index 361d3a9..0a96473 100644 --- a/src/southbridge/intel/ibexpeak/lpc.c +++ b/src/southbridge/intel/ibexpeak/lpc.c @@ -403,16 +403,6 @@ } } -static void pch_disable_smm_only_flashing(struct device *dev) -{ - u8 reg8; - - printk(BIOS_SPEW, "Enabling BIOS updates outside of SMM... "); - reg8 = pci_read_config8(dev, BIOS_CNTL); - reg8 &= ~(1 << 5); - pci_write_config8(dev, BIOS_CNTL, reg8); -} - static void pch_fixups(struct device *dev) { /* @@ -462,8 +452,6 @@ /* Interrupt 9 should be level triggered (SCI) */ i8259_configure_irq_trigger(9, 1); - pch_disable_smm_only_flashing(dev); - pch_set_acpi_mode(); pch_fixups(dev); diff --git a/src/southbridge/intel/lynxpoint/lpc.c b/src/southbridge/intel/lynxpoint/lpc.c index 3685a41..9c07c34 100644 --- a/src/southbridge/intel/lynxpoint/lpc.c +++ b/src/southbridge/intel/lynxpoint/lpc.c @@ -475,13 +475,6 @@ apm_control(APM_CNT_ACPI_DISABLE); } -static void pch_disable_smm_only_flashing(struct device *dev) -{ - printk(BIOS_SPEW, "Enabling BIOS updates outside of SMM... "); - - pci_and_config8(dev, BIOS_CNTL, ~(1 << 5)); -} - static void pch_fixups(struct device *dev) { /* Indicate DRAM init done for MRC S3 to know it can resume */ @@ -533,8 +526,6 @@ /* Interrupt 9 should be level triggered (SCI) */ i8259_configure_irq_trigger(9, 1); - pch_disable_smm_only_flashing(dev); - pch_set_acpi_mode(); pch_fixups(dev); -- To view, visit https://review.coreboot.org/c/coreboot/+/50479 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7ce0ca584cd3d42a10cdb74f45742f1eadc01bfa Gerrit-Change-Number: 50479 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: sb/intel/lynxpoint: Do not mask out TCO status bits
by Angel Pons (Code Review) 10 Feb '21

10 Feb '21

Attention is currently required from: Patrick Rudolph. Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/50478 ) Change subject: sb/intel/lynxpoint: Do not mask out TCO status bits ...................................................................... sb/intel/lynxpoint: Do not mask out TCO status bits Not all TCO status bits have a corresponding enable bit. Masking out the status register with the enable register causes these events to be lost. Tested on Asrock B85M Pro4, BIOSWR_STS events are now detected. Change-Id: I49abb5a4a99e943e57e0aaa6f06ff63bdf957cd3 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/southbridge/intel/lynxpoint/pmutil.c 1 file changed, 2 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/78/50478/1 diff --git a/src/southbridge/intel/lynxpoint/pmutil.c b/src/southbridge/intel/lynxpoint/pmutil.c index 7b84689..8117b4d 100644 --- a/src/southbridge/intel/lynxpoint/pmutil.c +++ b/src/southbridge/intel/lynxpoint/pmutil.c @@ -298,12 +298,11 @@ * TCO */ -/* Clear TCO status and return events that are enabled and active */ +/* Clear TCO status and return events that are active */ static u32 reset_tco_status(void) { u32 tcobase = get_pmbase() + 0x60; u32 tco_sts = inl(tcobase + 0x04); - u32 tco_en = inl(get_pmbase() + 0x68); /* Don't clear BOOT_STS before SECOND_TO_STS */ outl(tco_sts & ~(1 << 18), tcobase + 0x04); @@ -312,7 +311,7 @@ if (tco_sts & (1 << 18)) outl(tco_sts & (1 << 18), tcobase + 0x04); - return tco_sts & tco_en; + return tco_sts; } /* Print TCO status bits */ -- To view, visit https://review.coreboot.org/c/coreboot/+/50478 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I49abb5a4a99e943e57e0aaa6f06ff63bdf957cd3 Gerrit-Change-Number: 50478 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: sb/intel/lynxpoint: Only generate SerialIO SSDT for PCH-LP
by Angel Pons (Code Review) 10 Feb '21

10 Feb '21

Attention is currently required from: Patrick Rudolph. Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/50477 ) Change subject: sb/intel/lynxpoint: Only generate SerialIO SSDT for PCH-LP ...................................................................... sb/intel/lynxpoint: Only generate SerialIO SSDT for PCH-LP Lynxpoint PCH-H does not have SerialIO, so do not generate its SSDT. Change-Id: Ie816ebd470df93a45826498bf21be59ff0a813bf Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/southbridge/intel/lynxpoint/lpc.c 1 file changed, 8 insertions(+), 7 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/77/50477/1 diff --git a/src/southbridge/intel/lynxpoint/lpc.c b/src/southbridge/intel/lynxpoint/lpc.c index b0ff545..3685a41 100644 --- a/src/southbridge/intel/lynxpoint/lpc.c +++ b/src/southbridge/intel/lynxpoint/lpc.c @@ -692,7 +692,6 @@ struct acpi_rsdp *rsdp) { unsigned long current; - acpi_header_t *ssdt; current = start; @@ -706,12 +705,14 @@ current = acpi_align_current(current); - printk(BIOS_DEBUG, "ACPI: * SSDT2\n"); - ssdt = (acpi_header_t *)current; - acpi_create_serialio_ssdt(ssdt); - current += ssdt->length; - acpi_add_table(rsdp, ssdt); - current = acpi_align_current(current); + if (pch_is_lp()) { + printk(BIOS_DEBUG, "ACPI: * SSDT2\n"); + acpi_header_t *ssdt = (acpi_header_t *)current; + acpi_create_serialio_ssdt(ssdt); + current += ssdt->length; + acpi_add_table(rsdp, ssdt); + current = acpi_align_current(current); + } printk(BIOS_DEBUG, "current = %lx\n", current); return current; -- To view, visit https://review.coreboot.org/c/coreboot/+/50477 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie816ebd470df93a45826498bf21be59ff0a813bf Gerrit-Change-Number: 50477 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: sb/intel/lynxpoint/pch.h: Guard macro parameters
by Angel Pons (Code Review) 10 Feb '21

10 Feb '21

Attention is currently required from: Patrick Rudolph. Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/50476 ) Change subject: sb/intel/lynxpoint/pch.h: Guard macro parameters ...................................................................... sb/intel/lynxpoint/pch.h: Guard macro parameters Guard against unintended operator precedence and associativity issues. Tested on Asrock B85M Pro4, still boots. Change-Id: I2b22af17816e5383c7eb215a773eb6750d4ed9bc Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/southbridge/intel/lynxpoint/pch.h 1 file changed, 10 insertions(+), 10 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/76/50476/1 diff --git a/src/southbridge/intel/lynxpoint/pch.h b/src/southbridge/intel/lynxpoint/pch.h index 2833356..9c6a668 100644 --- a/src/southbridge/intel/lynxpoint/pch.h +++ b/src/southbridge/intel/lynxpoint/pch.h @@ -205,7 +205,7 @@ #define COMB_LPC_EN (1 << 1) /* LPC_IO_DEC[6:4] */ #define COMA_LPC_EN (1 << 0) /* LPC_IO_DEC[2:0] */ #define LPC_IBDF 0x6C /* I/O APIC bus/dev/fn */ -#define LPC_HnBDF(n) (0x70 + n * 2) /* HPET n bus/dev/fn */ +#define LPC_HnBDF(n) (0x70 + (n) * 2) /* HPET n bus/dev/fn */ #define LPC_GEN1_DEC 0x84 /* LPC IF Generic Decode Range 1 */ #define LPC_GEN2_DEC 0x88 /* LPC IF Generic Decode Range 2 */ #define LPC_GEN3_DEC 0x8c /* LPC IF Generic Decode Range 3 */ @@ -249,7 +249,7 @@ #define EHCI_USB_CMD_RUN (1 << 0) #define EHCI_USB_CMD_PSE (1 << 4) #define EHCI_USB_CMD_ASE (1 << 5) -#define EHCI_PORTSC(port) (0x64 + (port * 4)) +#define EHCI_PORTSC(port) (0x64 + (port) * 4) #define EHCI_PORTSC_ENABLED (1 << 2) #define EHCI_PORTSC_SUSPEND (1 << 7) @@ -267,7 +267,7 @@ #define XHCI_USB3PDO 0xe8 /* XHCI Memory Registers */ -#define XHCI_USB3_PORTSC(port) ((pch_is_lp() ? 0x510 : 0x570) + (port * 0x10)) +#define XHCI_USB3_PORTSC(port) ((pch_is_lp() ? 0x510 : 0x570) + ((port) * 0x10)) #define XHCI_USB3_PORTSC_CHST (0x7f << 17) #define XHCI_USB3_PORTSC_WCE (1 << 25) /* Wake on Connect */ #define XHCI_USB3_PORTSC_WDE (1 << 26) /* Wake on Disconnect */ @@ -335,7 +335,7 @@ #define SIO_REG_PPR_GEN 0x808 #define SIO_REG_PPR_GEN_LTR_MODE_MASK (1 << 2) #define SIO_REG_PPR_GEN_VOLTAGE_MASK (1 << 3) -#define SIO_REG_PPR_GEN_VOLTAGE(x) ((x & 1) << 3) +#define SIO_REG_PPR_GEN_VOLTAGE(x) (((x) & 1) << 3) #define SIO_REG_AUTO_LTR 0x814 #define SIO_REG_SDIO_PPR_GEN 0x1008 @@ -492,7 +492,7 @@ #define PCH_DISABLE_EHCI2 (1 << 13) #define PCH_DISABLE_LPC (1 << 14) #define PCH_DISABLE_EHCI1 (1 << 15) -#define PCH_DISABLE_PCIE(x) (1 << (16 + x)) +#define PCH_DISABLE_PCIE(x) (1 << (16 + (x))) #define PCH_DISABLE_THERMAL (1 << 24) #define PCH_DISABLE_SATA2 (1 << 25) #define PCH_DISABLE_XHCI (1 << 27) @@ -594,9 +594,9 @@ */ #define SPIBAR_OFFSET 0x3800 -#define SPIBAR8(x) RCBA8(x + SPIBAR_OFFSET) -#define SPIBAR16(x) RCBA16(x + SPIBAR_OFFSET) -#define SPIBAR32(x) RCBA32(x + SPIBAR_OFFSET) +#define SPIBAR8(x) RCBA8((x) + SPIBAR_OFFSET) +#define SPIBAR16(x) RCBA16((x) + SPIBAR_OFFSET) +#define SPIBAR32(x) RCBA32((x) + SPIBAR_OFFSET) /* Reigsters within the SPIBAR */ #define SSFC 0x91 @@ -609,13 +609,13 @@ #define SPIBAR_HSFS_FCERR (1 << 1) /* SPI Flash Cycle Error */ #define SPIBAR_HSFS_FDONE (1 << 0) /* SPI Flash Cycle Done */ #define SPIBAR_HSFC 0x3806 /* SPI hardware sequence control */ -#define SPIBAR_HSFC_BYTE_COUNT(c) (((c - 1) & 0x3f) << 8) +#define SPIBAR_HSFC_BYTE_COUNT(c) ((((c) - 1) & 0x3f) << 8) #define SPIBAR_HSFC_CYCLE_READ (0 << 1) /* Read cycle */ #define SPIBAR_HSFC_CYCLE_WRITE (2 << 1) /* Write cycle */ #define SPIBAR_HSFC_CYCLE_ERASE (3 << 1) /* Erase cycle */ #define SPIBAR_HSFC_GO (1 << 0) /* GO: start SPI transaction */ #define SPIBAR_FADDR 0x3808 /* SPI flash address */ -#define SPIBAR_FDATA(n) (0x3810 + (4 * n)) /* SPI flash data */ +#define SPIBAR_FDATA(n) (0x3810 + (4 * (n))) /* SPI flash data */ #endif /* __ACPI__ */ #endif /* SOUTHBRIDGE_INTEL_LYNXPOINT_PCH_H */ -- To view, visit https://review.coreboot.org/c/coreboot/+/50476 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2b22af17816e5383c7eb215a773eb6750d4ed9bc Gerrit-Change-Number: 50476 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: sb/intel/common: Move named packages out of method
by Angel Pons (Code Review) 10 Feb '21

10 Feb '21

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/50475 ) Change subject: sb/intel/common: Move named packages out of method ...................................................................... sb/intel/common: Move named packages out of method IASL complains that creation of named objects within a method is highly inefficient. Avoid this by moving these named objects out of the method. Change-Id: Iabfb20dcb3f655658844d99ab7a3b479684d9d19 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/southbridge/intel/common/acpi/pcie.asl 1 file changed, 48 insertions(+), 48 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/75/50475/1 diff --git a/src/southbridge/intel/common/acpi/pcie.asl b/src/southbridge/intel/common/acpi/pcie.asl index c1bfcfd..cd584ab 100644 --- a/src/southbridge/intel/common/acpi/pcie.asl +++ b/src/southbridge/intel/common/acpi/pcie.asl @@ -2,56 +2,56 @@ /* Intel southbridge PCIe support */ +/* Interrupt Map INTA->INTA, INTB->INTB, INTC->INTC, INTD->INTD */ +Name (IQAA, Package() { + Package() { 0x0000ffff, 0, 0, 16 }, + Package() { 0x0000ffff, 1, 0, 17 }, + Package() { 0x0000ffff, 2, 0, 18 }, + Package() { 0x0000ffff, 3, 0, 19 } }) +Name (IQAP, Package() { + Package() { 0x0000ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, + Package() { 0x0000ffff, 1, \_SB.PCI0.LPCB.LNKB, 0 }, + Package() { 0x0000ffff, 2, \_SB.PCI0.LPCB.LNKC, 0 }, + Package() { 0x0000ffff, 3, \_SB.PCI0.LPCB.LNKD, 0 } }) + +/* Interrupt Map INTA->INTB, INTB->INTC, INTC->INTD, INTD->INTA */ +Name (IQBA, Package() { + Package() { 0x0000ffff, 0, 0, 17 }, + Package() { 0x0000ffff, 1, 0, 18 }, + Package() { 0x0000ffff, 2, 0, 19 }, + Package() { 0x0000ffff, 3, 0, 16 } }) +Name (IQBP, Package() { + Package() { 0x0000ffff, 0, \_SB.PCI0.LPCB.LNKB, 0 }, + Package() { 0x0000ffff, 1, \_SB.PCI0.LPCB.LNKC, 0 }, + Package() { 0x0000ffff, 2, \_SB.PCI0.LPCB.LNKD, 0 }, + Package() { 0x0000ffff, 3, \_SB.PCI0.LPCB.LNKA, 0 } }) + +/* Interrupt Map INTA->INTC, INTB->INTD, INTC->INTA, INTD->INTB */ +Name (IQCA, Package() { + Package() { 0x0000ffff, 0, 0, 18 }, + Package() { 0x0000ffff, 1, 0, 19 }, + Package() { 0x0000ffff, 2, 0, 16 }, + Package() { 0x0000ffff, 3, 0, 17 } }) +Name (IQCP, Package() { + Package() { 0x0000ffff, 0, \_SB.PCI0.LPCB.LNKC, 0 }, + Package() { 0x0000ffff, 1, \_SB.PCI0.LPCB.LNKD, 0 }, + Package() { 0x0000ffff, 2, \_SB.PCI0.LPCB.LNKA, 0 }, + Package() { 0x0000ffff, 3, \_SB.PCI0.LPCB.LNKB, 0 } }) + +/* Interrupt Map INTA->INTD, INTB->INTA, INTC->INTB, INTD->INTC */ +Name (IQDA, Package() { + Package() { 0x0000ffff, 0, 0, 19 }, + Package() { 0x0000ffff, 1, 0, 16 }, + Package() { 0x0000ffff, 2, 0, 17 }, + Package() { 0x0000ffff, 3, 0, 18 } }) +Name (IQDP, Package() { + Package() { 0x0000ffff, 0, \_SB.PCI0.LPCB.LNKD, 0 }, + Package() { 0x0000ffff, 1, \_SB.PCI0.LPCB.LNKA, 0 }, + Package() { 0x0000ffff, 2, \_SB.PCI0.LPCB.LNKB, 0 }, + Package() { 0x0000ffff, 3, \_SB.PCI0.LPCB.LNKC, 0 } }) + Method (IRQM, 1, Serialized) { - /* Interrupt Map INTA->INTA, INTB->INTB, INTC->INTC, INTD->INTD */ - Name (IQAA, Package() { - Package() { 0x0000ffff, 0, 0, 16 }, - Package() { 0x0000ffff, 1, 0, 17 }, - Package() { 0x0000ffff, 2, 0, 18 }, - Package() { 0x0000ffff, 3, 0, 19 } }) - Name (IQAP, Package() { - Package() { 0x0000ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, - Package() { 0x0000ffff, 1, \_SB.PCI0.LPCB.LNKB, 0 }, - Package() { 0x0000ffff, 2, \_SB.PCI0.LPCB.LNKC, 0 }, - Package() { 0x0000ffff, 3, \_SB.PCI0.LPCB.LNKD, 0 } }) - - /* Interrupt Map INTA->INTB, INTB->INTC, INTC->INTD, INTD->INTA */ - Name (IQBA, Package() { - Package() { 0x0000ffff, 0, 0, 17 }, - Package() { 0x0000ffff, 1, 0, 18 }, - Package() { 0x0000ffff, 2, 0, 19 }, - Package() { 0x0000ffff, 3, 0, 16 } }) - Name (IQBP, Package() { - Package() { 0x0000ffff, 0, \_SB.PCI0.LPCB.LNKB, 0 }, - Package() { 0x0000ffff, 1, \_SB.PCI0.LPCB.LNKC, 0 }, - Package() { 0x0000ffff, 2, \_SB.PCI0.LPCB.LNKD, 0 }, - Package() { 0x0000ffff, 3, \_SB.PCI0.LPCB.LNKA, 0 } }) - - /* Interrupt Map INTA->INTC, INTB->INTD, INTC->INTA, INTD->INTB */ - Name (IQCA, Package() { - Package() { 0x0000ffff, 0, 0, 18 }, - Package() { 0x0000ffff, 1, 0, 19 }, - Package() { 0x0000ffff, 2, 0, 16 }, - Package() { 0x0000ffff, 3, 0, 17 } }) - Name (IQCP, Package() { - Package() { 0x0000ffff, 0, \_SB.PCI0.LPCB.LNKC, 0 }, - Package() { 0x0000ffff, 1, \_SB.PCI0.LPCB.LNKD, 0 }, - Package() { 0x0000ffff, 2, \_SB.PCI0.LPCB.LNKA, 0 }, - Package() { 0x0000ffff, 3, \_SB.PCI0.LPCB.LNKB, 0 } }) - - /* Interrupt Map INTA->INTD, INTB->INTA, INTC->INTB, INTD->INTC */ - Name (IQDA, Package() { - Package() { 0x0000ffff, 0, 0, 19 }, - Package() { 0x0000ffff, 1, 0, 16 }, - Package() { 0x0000ffff, 2, 0, 17 }, - Package() { 0x0000ffff, 3, 0, 18 } }) - Name (IQDP, Package() { - Package() { 0x0000ffff, 0, \_SB.PCI0.LPCB.LNKD, 0 }, - Package() { 0x0000ffff, 1, \_SB.PCI0.LPCB.LNKA, 0 }, - Package() { 0x0000ffff, 2, \_SB.PCI0.LPCB.LNKB, 0 }, - Package() { 0x0000ffff, 3, \_SB.PCI0.LPCB.LNKC, 0 } }) - Switch (ToInteger (Arg0)) { /* PCIe Root Port 1 and 5 */ Case (Package() { 1, 5 }) { -- To view, visit https://review.coreboot.org/c/coreboot/+/50475 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iabfb20dcb3f655658844d99ab7a3b479684d9d19 Gerrit-Change-Number: 50475 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: tint: update the patch version numbers according to a new tint version
by Mike Banon (Code Review) 10 Feb '21

10 Feb '21

Attention is currently required from: Martin Roth, Stefan Reinauer, Mike Banon. Hello build bot (Jenkins), Martin Roth, Stefan Reinauer, Angel Pons, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/50468 to look at the new patch set (#2). Change subject: tint: update the patch version numbers according to a new tint version ...................................................................... tint: update the patch version numbers according to a new tint version Rebase the libpayload_tint.patch to update its internal version numbers from 0.04+nmu1 to 0.05. Signed-off-by: Mike Banon <mikebdp2(a)gmail.com> Change-Id: I91f780f80026147c3c35330625a4106c65a1ddf0 --- M payloads/external/tint/libpayload_tint.patch 1 file changed, 44 insertions(+), 46 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/68/50468/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/50468 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I91f780f80026147c3c35330625a4106c65a1ddf0 Gerrit-Change-Number: 50468 Gerrit-PatchSet: 2 Gerrit-Owner: Mike Banon <mikebdp2(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: Mike Banon <mikebdp2(a)gmail.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: tests: Add lib/stack-test test case
by Name of user not set (Code Review) 10 Feb '21

10 Feb '21

Attention is currently required from: Martin Roth, Paul Fagerburg, Jan Dabros. jacz(a)semihalf.com has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50305 ) Change subject: tests: Add lib/stack-test test case ...................................................................... Patch Set 4: (1 comment) File tests/lib/stack-test.c: https://review.coreboot.org/c/coreboot/+/50305/comment/fc92ad97_25b841a5 PS1, Line 102: stack[i] = 0x42420707; > I agree, the stack is almost always an even number of machine words, often a power of 2. […] Ok, I changed it back to previous form. Thank you :) -- To view, visit https://review.coreboot.org/c/coreboot/+/50305 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icf0cceac290618a50ecc4e65f1f9551dbf31bd32 Gerrit-Change-Number: 50305 Gerrit-PatchSet: 4 Gerrit-Owner: jacz(a)semihalf.com Gerrit-Reviewer: Jan Dabros <jsd(a)semihalf.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Fagerburg <pfagerburg(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Paul Fagerburg <pfagerburg(a)chromium.org> Gerrit-Attention: Jan Dabros <jsd(a)semihalf.com> Gerrit-Comment-Date: Wed, 10 Feb 2021 10:16:43 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: jacz(a)semihalf.com Comment-In-Reply-To: Paul Fagerburg <pfagerburg(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: nb/intel/sandybridge: Fix description of auto-precharge bit
by Angel Pons (Code Review) 10 Feb '21

10 Feb '21

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/50473 ) Change subject: nb/intel/sandybridge: Fix description of auto-precharge bit ...................................................................... nb/intel/sandybridge: Fix description of auto-precharge bit This bit is primarily used to issue RDA commands. There doesn't seem to be any limitation regarding the number of address bits. Change-Id: I2804f67319c9bc736f9086af408853056aabedd6 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/northbridge/intel/sandybridge/raminit_common.c M src/northbridge/intel/sandybridge/registers/mchbar.h 2 files changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/73/50473/1 diff --git a/src/northbridge/intel/sandybridge/raminit_common.c b/src/northbridge/intel/sandybridge/raminit_common.c index cef0131..8e54101 100644 --- a/src/northbridge/intel/sandybridge/raminit_common.c +++ b/src/northbridge/intel/sandybridge/raminit_common.c @@ -1712,7 +1712,7 @@ .rank = slotrank, }, }, - /* DRAM command RD */ + /* DRAM command RDA */ [2] = { .sp_cmd_ctrl = { .command = IOSAV_RD, diff --git a/src/northbridge/intel/sandybridge/registers/mchbar.h b/src/northbridge/intel/sandybridge/registers/mchbar.h index 2fe6b24..6adf428 100644 --- a/src/northbridge/intel/sandybridge/registers/mchbar.h +++ b/src/northbridge/intel/sandybridge/registers/mchbar.h @@ -112,7 +112,7 @@ * end architecture RTL; * * [16] Chip Select mode control. - * [17] Auto Precharge. Only valid when using 10 row bits! + * [17] Auto Precharge. Used to send RDA commands. * * IOSAV_n_SUBSEQ_CTRL_ch(channel, index) * The parameters of the subseq: number of repetitions of the command, -- To view, visit https://review.coreboot.org/c/coreboot/+/50473 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2804f67319c9bc736f9086af408853056aabedd6 Gerrit-Change-Number: 50473 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: tests: Add lib/stack-test test case
by Name of user not set (Code Review) 10 Feb '21

10 Feb '21

Attention is currently required from: Martin Roth, Jan Dabros. Hello build bot (Jenkins), Patrick Georgi, Martin Roth, Paul Fagerburg, Jan Dabros, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/50305 to look at the new patch set (#4). Change subject: tests: Add lib/stack-test test case ...................................................................... tests: Add lib/stack-test test case Signed-off-by: Jakub Czapiga <jacz(a)semihalf.com> Change-Id: Icf0cceac290618a50ecc4e65f1f9551dbf31bd32 --- M tests/lib/Makefile.inc A tests/lib/stack-test.c 2 files changed, 138 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/05/50305/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/50305 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icf0cceac290618a50ecc4e65f1f9551dbf31bd32 Gerrit-Change-Number: 50305 Gerrit-PatchSet: 4 Gerrit-Owner: jacz(a)semihalf.com Gerrit-Reviewer: Jan Dabros <jsd(a)semihalf.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Fagerburg <pfagerburg(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Jan Dabros <jsd(a)semihalf.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: nb/intel/common/fixed_bars.h: Add casts to `uintptr_t`
by Patrick Rudolph (Code Review) 10 Feb '21

10 Feb '21

Attention is currently required from: Nico Huber, Angel Pons, Arthur Heymans. Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50469 ) Change subject: nb/intel/common/fixed_bars.h: Add casts to `uintptr_t` ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/50469 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I570374f92394f839a97e28fabc8fa07a7e673e83 Gerrit-Change-Number: 50469 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Wed, 10 Feb 2021 09:46:11 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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coreboot-gerrit February 2021