coreboot-gerrit February 2021

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Change in coreboot[master]: soc/intel/xeon_sp/include/soc/acpi_asl.h: Convert to ASL 2.0
by Michael Niewöhner (Code Review) 10 Feb '21

10 Feb '21

Michael Niewöhner has submitted this change. ( https://review.coreboot.org/c/coreboot/+/50324 ) Change subject: soc/intel/xeon_sp/include/soc/acpi_asl.h: Convert to ASL 2.0 ...................................................................... soc/intel/xeon_sp/include/soc/acpi_asl.h: Convert to ASL 2.0 Change-Id: Ie1d31b9d02584b97b85afe970894cfe557174733 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50324 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> Reviewed-by: Michael Niewöhner <foss(a)mniewoehner.de> --- M src/soc/intel/xeon_sp/include/soc/acpi_asl.h 1 file changed, 6 insertions(+), 6 deletions(-) Approvals: build bot (Jenkins): Verified Angel Pons: Looks good to me, but someone else must approve Michael Niewöhner: Looks good to me, approved diff --git a/src/soc/intel/xeon_sp/include/soc/acpi_asl.h b/src/soc/intel/xeon_sp/include/soc/acpi_asl.h index e08e02b..befce2e 100644 --- a/src/soc/intel/xeon_sp/include/soc/acpi_asl.h +++ b/src/soc/intel/xeon_sp/include/soc/acpi_asl.h @@ -44,22 +44,22 @@ IRQ (Level, ActiveLow, Shared) {} \ }) \ CreateWordField (RTLA, 1, IRQ0) \ - Store (Zero, IRQ0) \ + IRQ0 = 0 \ \ /* Set the bit from PIRQ Routing Register */ \ - ShiftLeft (1, And (^^PIR##id, ^^IREM), IRQ0) \ + IRQ0 = 1 << (^^PIR##id & ^^IREM) \ Return (RTLA) \ } \ Method (_SRS, 1, Serialized) \ { \ CreateWordField (Arg0, 1, IRQ0) \ FindSetRightBit (IRQ0, Local0) \ - Decrement (Local0) \ - Store (Local0, ^^PIR##id) \ + Local0-- \ + ^^PIR##id = Local0 \ } \ Method (_STA, 0, Serialized) \ { \ - If (And (^^PIR##id, ^^IREN)) { \ + If (^^PIR##id & ^^IREN) { \ Return (0x9) \ } Else { \ Return (0xb) \ @@ -67,7 +67,7 @@ } \ Method (_DIS, 0, Serialized) \ { \ - Or (^^PIR##id, ^^IREN, ^^PIR##id) \ + ^^PIR##id |= ^^IREN \ } \ } -- To view, visit https://review.coreboot.org/c/coreboot/+/50324 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie1d31b9d02584b97b85afe970894cfe557174733 Gerrit-Change-Number: 50324 Gerrit-PatchSet: 2 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/intel/xeon_sp/include/soc/acpi_asl.h: Convert to ASL 2.0
by Michael Niewöhner (Code Review) 10 Feb '21

10 Feb '21

Attention is currently required from: Patrick Rudolph, HAOUAS Elyes. Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50324 ) Change subject: soc/intel/xeon_sp/include/soc/acpi_asl.h: Convert to ASL 2.0 ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/50324 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie1d31b9d02584b97b85afe970894cfe557174733 Gerrit-Change-Number: 50324 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Comment-Date: Wed, 10 Feb 2021 18:02:37 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/poppy/var/baseboard: Convert to ASL 2.0
by Michael Niewöhner (Code Review) 10 Feb '21

10 Feb '21

Michael Niewöhner has submitted this change. ( https://review.coreboot.org/c/coreboot/+/50321 ) Change subject: mb/google/poppy/var/baseboard: Convert to ASL 2.0 ...................................................................... mb/google/poppy/var/baseboard: Convert to ASL 2.0 Change-Id: Ic3d0ea9893c3c25305e2da94681cb5ac466782fc Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50321 Reviewed-by: Michael Niewöhner <foss(a)mniewoehner.de> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/google/poppy/variants/baseboard/include/baseboard/acpi/camera_pmic.asl 1 file changed, 47 insertions(+), 48 deletions(-) Approvals: build bot (Jenkins): Verified Angel Pons: Looks good to me, but someone else must approve Michael Niewöhner: Looks good to me, approved diff --git a/src/mainboard/google/poppy/variants/baseboard/include/baseboard/acpi/camera_pmic.asl b/src/mainboard/google/poppy/variants/baseboard/include/baseboard/acpi/camera_pmic.asl index 842005a..4b1254d 100644 --- a/src/mainboard/google/poppy/variants/baseboard/include/baseboard/acpi/camera_pmic.asl +++ b/src/mainboard/google/poppy/variants/baseboard/include/baseboard/acpi/camera_pmic.asl @@ -25,7 +25,7 @@ Method (PMOF, 0, Serialized) { /* Make Sure all PMIC outputs are off. */ - If (LEqual (VSIC, Zero)) { + If (VSIC == 0) { CTXS(EN_PP3300_DX_CAM) } } @@ -39,7 +39,7 @@ Method (_ON, 0, Serialized) { PMON() /* Do not reset PMIC across S3 and S0ix cycle */ - if (Lequal (RSTO, 1)) { + if (RSTO == 1) { CTXS(EN_CAM_PMIC_RST_L) Sleep(1) STXS(EN_CAM_PMIC_RST_L) @@ -64,46 +64,45 @@ Name (AVB3, Zero) Method (_REG, 2, NotSerialized) { - If (LEqual (Arg0, 0x08)) + If (Arg0 == 0x08) { /* Marks the availability of GeneralPurposeIO * 0x08: opregion space for GeneralPurposeIO */ - Store (Arg1, AVGP) + AVGP = Arg1 } - If (LEqual (Arg0, 0xB0)) + If (Arg0 == 0xb0) { /* Marks the availability of * TI_PMIC_POWER_OPREGION_ID */ - Store (Arg1, AVB0) + AVB0 = Arg1 } - If (LEqual (Arg0, 0xB1)) + If (Arg0 == 0xb1) { /* Marks the availability of * TI_PMIC_VR_VAL_OPREGION_ID */ - Store (Arg1, AVB1) + AVB1 = Arg1 } - If (LEqual (Arg0, 0xB2)) + If (Arg0 == 0xb2) { /* Marks the availability of * TI_PMIC_CLK_OPREGION_ID */ - Store (Arg1, AVB2) + AVB2 = Arg1 } - If (LEqual (Arg0, 0xB3)) + If (Arg0 == 0xb3) { /* Marks the availability of * TI_PMIC_CLK_FREQ_OPREGION_ID */ - Store (Arg1, AVB3) + AVB3 = Arg1 } - If (LAnd (AVGP, LAnd (LAnd (AVB0, AVB1), - LAnd(AVB2, AVB3)))) + If (AVGP && AVB0 && AVB1 && AVB2 && AVB3) { /* Marks the availability of all opregions */ - Store (1, AVBL) + AVBL = 1 } Else { - Store (0, AVBL) + AVBL = 0 } } @@ -314,7 +313,7 @@ } Method (CLK, 1, Serialized) { - If (LEqual (Arg0, Zero)) { + If (Arg0 == 0) { BODI = 0 BUDI = 0 PSWR = 0 @@ -328,7 +327,7 @@ CFG1 = 0 PCTL = 0 Sleep(1) - } ElseIf (LEqual (Arg0, 1)) { + } ElseIf (Arg0 == 1) { /* Set boost clock divider */ BODI = 3 /* Set buck clock divider */ @@ -364,37 +363,37 @@ Name (VSIC, 0) Method (DOVD, 1, Serialized) { /* Turn off VSIO */ - If (LEqual (Arg0, Zero)) { + If (Arg0 == 0) { /* Decrement only if VSIC > 0 */ - if (LGreater (VSIC, 0)) { - Decrement (VSIC) - If (LEqual (VSIC, Zero)) { + if (VSIC > 0) { + VSIC-- + If (VSIC == 0) { VSIO = 0 Sleep(1) PMOF() } } - } ElseIf (LEqual (Arg0, 1)) { + } ElseIf (Arg0 == 1) { /* Increment only if VSIC < 4 */ - If (LLess (VSIC, 4)) { + If (VSIC < 4) { /* Turn on VSIO */ - If (LEqual (VSIC, Zero)) { + If (VSIC == 0) { PMON() VSIO = 3 - if (LNotEqual (IOVA, 52)) { + if (IOVA != 52) { /* Set VSIO value as 1.8006 V */ IOVA = 52 } - if (LNotEqual (SIOV, 52)) { + if (SIOV != 52) { /* Set VSIO value as 1.8006 V */ SIOV = 52 } Sleep(3) } - Increment (VSIC) + VSIC++ } } } @@ -403,8 +402,8 @@ PowerResource (OVCM, 0, 0) { Name (STA, 0) Method (_ON, 0, Serialized) { - If (LEqual (AVBL, 1)) { - If (LEqual (STA, 0)) { + If (AVBL == 1) { + If (STA == 0) { /* Enable VSIO regulator + daisy chain */ DOVD(1) @@ -415,8 +414,8 @@ } } Method (_OFF, 0, Serialized) { - If (LEqual (AVBL, 1)) { - If (LEqual (STA, 1)) { + If (AVBL == 1) { + If (STA == 1) { CLK(0) Sleep(2) DOVD(0) @@ -434,8 +433,8 @@ Name (STA, 0) Method (_ON, 0, Serialized) { /* TODO: Read Voltage and Sleep values from Sensor Obj */ - If (LEqual (AVBL, 1)) { - If (LEqual (STA, 0)) { + If (AVBL == 1) { + If (STA == 0) { \_SB.PCI0.I2C2.PMIC.CGP1() \_SB.PCI0.I2C2.PMIC.CGP2() @@ -467,8 +466,8 @@ } Method (_OFF, 0, Serialized) { - If (LEqual (AVBL, 1)) { - If (LEqual (STA, 1)) { + If (AVBL == 1) { + If (STA == 1) { Sleep(2) \_SB.PCI0.I2C2.PMIC.CRST(0) Sleep(3) @@ -490,8 +489,8 @@ Name (STA, 0) Method (_ON, 0, Serialized) { /* TODO: Read Voltage and Sleep values from Sensor Obj */ - If (LEqual (AVBL, 1)) { - If (LEqual (STA, 0)) { + If (AVBL == 1) { + If (STA == 0) { /* Set VAUX2 as 1.8006 V */ AX2V = 52 VAX2 = 1 /* Enable VAUX2 */ @@ -523,8 +522,8 @@ } Method (_OFF, 0, Serialized) { - If (LEqual (AVBL, 1)) { - If (LEqual (STA, 1)) { + If (AVBL == 1) { + If (STA == 1) { Sleep(2) \_SB.PCI0.I2C2.PMIC.CGP5(0) Sleep(3) @@ -548,8 +547,8 @@ PowerResource (VCMP, 0, 0) { Name (STA, 0) Method (_ON, 0, Serialized) { - If (LEqual (AVBL, 1)) { - If (LEqual (STA, 0)) { + If (AVBL == 1) { + If (STA == 0) { /* Enable VSIO regulator + daisy chain */ DOVD(1) @@ -566,8 +565,8 @@ } Method (_OFF, 0, Serialized) { - If (LEqual (AVBL, 1)) { - If (LEqual (STA, 1)) { + If (AVBL == 1) { + If (STA == 1) { VCMC = 0 /* Disable regulator */ Sleep(1) DOVD(0) /* Disable regulator */ @@ -585,8 +584,8 @@ PowerResource (NVMP, 0, 0) { Name (STA, 0) Method (_ON, 0, Serialized) { - If (LEqual (AVBL, 1)) { - If (LEqual (STA, 0)) { + If (AVBL == 1) { + If (STA == 0) { /* Enable VSIO regulator + daisy chain */ DOVD(1) @@ -596,8 +595,8 @@ } Method (_OFF, 0, Serialized) { - If (LEqual (AVBL, 1)) { - If (LEqual (STA, 1)) { + If (AVBL == 1) { + If (STA == 1) { DOVD(0) /* Disable regulator */ STA = 0 } -- To view, visit https://review.coreboot.org/c/coreboot/+/50321 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic3d0ea9893c3c25305e2da94681cb5ac466782fc Gerrit-Change-Number: 50321 Gerrit-PatchSet: 3 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/google/poppy/var/baseboard: Convert to ASL 2.0
by Michael Niewöhner (Code Review) 10 Feb '21

10 Feb '21

Attention is currently required from: Angel Pons, HAOUAS Elyes. Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50321 ) Change subject: mb/google/poppy/var/baseboard: Convert to ASL 2.0 ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/50321 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic3d0ea9893c3c25305e2da94681cb5ac466782fc Gerrit-Change-Number: 50321 Gerrit-PatchSet: 2 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Comment-Date: Wed, 10 Feb 2021 18:01:30 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: src/ec/quanta/ene_kb3940q/acpi/battery.asl: Convert to ASL 2.0
by Michael Niewöhner (Code Review) 10 Feb '21

10 Feb '21

Attention is currently required from: HAOUAS Elyes. Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50318 ) Change subject: src/ec/quanta/ene_kb3940q/acpi/battery.asl: Convert to ASL 2.0 ...................................................................... Patch Set 1: Code-Review+1 (2 comments) File src/ec/quanta/ene_kb3940q/acpi/battery.asl: https://review.coreboot.org/c/coreboot/+/50318/comment/2727f60a_8a5176bd PS1, Line 42: One 1 https://review.coreboot.org/c/coreboot/+/50318/comment/ef0b8674_9aaa775f PS1, Line 79: BATD, 0x00)) // Model Number : PBIF [10] = ToDecimalString(BSN0) // Serial Number : PBIF [11] = ToString(Concatenate(BCHM, 0x00)) // Battery Type nit: maybe align comments? -- To view, visit https://review.coreboot.org/c/coreboot/+/50318 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7cc47536b0c1e2c903df29402090abfccde82406 Gerrit-Change-Number: 50318 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Comment-Date: Wed, 10 Feb 2021 18:00:04 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/system76/lemp9: Configure IRQs as level triggered for HID over I2C
by Furquan Shaikh (Code Review) 10 Feb '21

10 Feb '21

Attention is currently required from: Jeremy Soller, Tim Wawrzynczak, Karthik Ramasubramanian. Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50452 ) Change subject: mb/system76/lemp9: Configure IRQs as level triggered for HID over I2C ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/50452 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ice096777077bd2e9cfbaf744371fc372c0c05606 Gerrit-Change-Number: 50452 Gerrit-PatchSet: 1 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Jeremy Soller <jeremy(a)system76.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jeremy Soller <jeremy(a)system76.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Wed, 10 Feb 2021 17:58:33 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/amd/common/block/acpi/pm_state: don't rely on undefined behavior
by Felix Held (Code Review) 10 Feb '21

10 Feb '21

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/50492 ) Change subject: soc/amd/common/block/acpi/pm_state: don't rely on undefined behavior ...................................................................... soc/amd/common/block/acpi/pm_state: don't rely on undefined behavior Change-Id: I5a76a38f8d84666f6b9c0bfffecca064fa82d593 Found-by: Coverity CID 1445994 Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> --- M src/soc/amd/common/block/acpi/pm_state.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/92/50492/1 diff --git a/src/soc/amd/common/block/acpi/pm_state.c b/src/soc/amd/common/block/acpi/pm_state.c index ea22ec5..643cb02 100644 --- a/src/soc/amd/common/block/acpi/pm_state.c +++ b/src/soc/amd/common/block/acpi/pm_state.c @@ -18,7 +18,7 @@ return -1; /* get a mask of valid bits. Ex limit = 3, set bits 0-2 */ - t = (1 << limit) - 1; + t = (1ULL << limit) - 1; if ((value & t) == 0) return -1; t = 1; -- To view, visit https://review.coreboot.org/c/coreboot/+/50492 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5a76a38f8d84666f6b9c0bfffecca064fa82d593 Gerrit-Change-Number: 50492 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

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Change in coreboot[master]: drivers/i2c/hid: Enforce level triggered IRQ mode
by Angel Pons (Code Review) 10 Feb '21

10 Feb '21

Attention is currently required from: Furquan Shaikh, Tim Wawrzynczak, Michael Niewöhner, Karthik Ramasubramanian. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50442 ) Change subject: drivers/i2c/hid: Enforce level triggered IRQ mode ...................................................................... Patch Set 3: (1 comment) File src/drivers/i2c/hid/hid.c: https://review.coreboot.org/c/coreboot/+/50442/comment/5039df27_83446411 PS3, Line 82: dev->enabled = 0; > > Not sure what you mean with "and possibly set the trigger type back to LEVEL" […] You can use BUG(). With CONFIG_FATAL_ASSERTS=y, a misconfigured devicetree will result in a boot failure. -- To view, visit https://review.coreboot.org/c/coreboot/+/50442 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3245a9de6e88cd83528823251083e62288192f0d Gerrit-Change-Number: 50442 Gerrit-PatchSet: 3 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Wed, 10 Feb 2021 17:57:48 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Comment-In-Reply-To: Michael Niewöhner <foss(a)mniewoehner.de> Comment-In-Reply-To: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: src/ec/lenovo/h8/acpi/battery.asl: Convert to ASL 2.0
by Michael Niewöhner (Code Review) 10 Feb '21

10 Feb '21

Attention is currently required from: Alexander Couzens, HAOUAS Elyes. Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50317 ) Change subject: src/ec/lenovo/h8/acpi/battery.asl: Convert to ASL 2.0 ...................................................................... Patch Set 1: Code-Review+1 (1 comment) File src/ec/lenovo/h8/acpi/battery.asl: https://review.coreboot.org/c/coreboot/+/50317/comment/3d5a83ea_fef41872 PS1, Line 130: > >= -- To view, visit https://review.coreboot.org/c/coreboot/+/50317 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5de6c7da2440d682378a4ceb89b4bedd689dad60 Gerrit-Change-Number: 50317 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Attention: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Comment-Date: Wed, 10 Feb 2021 17:54:39 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: drivers/i2c/hid: Enforce level triggered IRQ mode
by Karthik Ramasubramanian (Code Review) 10 Feb '21

10 Feb '21

Attention is currently required from: Furquan Shaikh, Tim Wawrzynczak, Angel Pons, Michael Niewöhner. Karthik Ramasubramanian has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50442 ) Change subject: drivers/i2c/hid: Enforce level triggered IRQ mode ...................................................................... Patch Set 3: (1 comment) File src/drivers/i2c/hid/hid.c: https://review.coreboot.org/c/coreboot/+/50442/comment/58747c45_6a89ebea PS3, Line 82: dev->enabled = 0; > Not sure what you mean with "and possibly set the trigger type back to LEVEL" Forcefully set the IRQ mode to ACPI_IRQ_LEVEL_TRIGGERED even if it is set as EDGE triggered. > I agree with Tim that we don't need to disable the device: updating the devicetree to use level-triggered IRQs should be enough. Furquan brought the same point earlier. I am happy to set the IRQ to level-triggered as long as there are no corner cases. My only point is that it is easy to miss the warnings when things are working fine most of the time. -- To view, visit https://review.coreboot.org/c/coreboot/+/50442 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3245a9de6e88cd83528823251083e62288192f0d Gerrit-Change-Number: 50442 Gerrit-PatchSet: 3 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Comment-Date: Wed, 10 Feb 2021 17:52:36 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Comment-In-Reply-To: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-MessageType: comment

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coreboot-gerrit February 2021