coreboot-gerrit February 2021

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Change in coreboot[master]: soc/amd/cezanne: Add verstage support
by Raul Rangel (Code Review) 10 Feb '21

10 Feb '21

Attention is currently required from: Jason Glenesk, Martin Roth, Marshall Dawson, Felix Held. Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50342 ) Change subject: soc/amd/cezanne: Add verstage support ...................................................................... Patch Set 3: (1 comment) File src/soc/amd/cezanne/Kconfig: https://review.coreboot.org/c/coreboot/+/50342/comment/dc272bbd_df50ca5e PS2, Line 128: config VBOOT : select VBOOT_STARTS_IN_BOOTBLOCK : select VBOOT_SEPARATE_VERSTAGE > I think it should go in the mainboard. […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/50342 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I82874d649db3c9c370e32841e6a9898efb70082e Gerrit-Change-Number: 50342 Gerrit-PatchSet: 3 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Wed, 10 Feb 2021 18:28:01 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Raul Rangel <rrangel(a)chromium.org> Comment-In-Reply-To: Martin Roth <martinroth(a)google.com> Comment-In-Reply-To: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/amd/cezanne: Add verstage support
by Raul Rangel (Code Review) 10 Feb '21

10 Feb '21

Attention is currently required from: Jason Glenesk, Martin Roth, Marshall Dawson, Felix Held. Hello build bot (Jenkins), Jason Glenesk, Marshall Dawson, Angel Pons, Felix Held, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/50342 to look at the new patch set (#3). Change subject: soc/amd/cezanne: Add verstage support ...................................................................... soc/amd/cezanne: Add verstage support We don't currently support VBOOT_STARTS_BEFORE_BOOTBLOCK. This sets up verstage to run after bootblock. The offsets are the same as picasso. Signed-off-by: Raul E Rangel <rrangel(a)chromium.org> Change-Id: I82874d649db3c9c370e32841e6a9898efb70082e --- M src/soc/amd/cezanne/Kconfig 1 file changed, 21 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/42/50342/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/50342 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I82874d649db3c9c370e32841e6a9898efb70082e Gerrit-Change-Number: 50342 Gerrit-PatchSet: 3 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/amd: fully commonize clear_tvalid
by Felix Held (Code Review) 10 Feb '21

10 Feb '21

Attention is currently required from: Jason Glenesk, Raul Rangel, Martin Roth, Marshall Dawson. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50466 ) Change subject: soc/amd: fully commonize clear_tvalid ...................................................................... Patch Set 5: (1 comment) File src/soc/amd/common/block/cpu/smm/Makefile.inc: https://review.coreboot.org/c/coreboot/+/50466/comment/38e97ff9_4745af8b PS5, Line 5: romstage-y += smm_helper.c : postcar-y += smm_helper.c > stoneyridge uses it there and not adding it will break the build. […] *many -- To view, visit https://review.coreboot.org/c/coreboot/+/50466 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I90526a566a5fbc19a7368f90421067a6c716614e Gerrit-Change-Number: 50466 Gerrit-PatchSet: 5 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Comment-Date: Wed, 10 Feb 2021 18:12:47 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Martin Roth <martinroth(a)google.com> Comment-In-Reply-To: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/amd: fully commonize clear_tvalid
by Felix Held (Code Review) 10 Feb '21

10 Feb '21

Attention is currently required from: Jason Glenesk, Raul Rangel, Martin Roth, Marshall Dawson. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50466 ) Change subject: soc/amd: fully commonize clear_tvalid ...................................................................... Patch Set 5: (1 comment) File src/soc/amd/common/block/cpu/smm/Makefile.inc: https://review.coreboot.org/c/coreboot/+/50466/comment/80d98cde_722bc8d0 PS5, Line 5: romstage-y += smm_helper.c : postcar-y += smm_helper.c > Is this used in romstage or postcar? That just seams a little early to me. stoneyridge uses it there and not adding it will break the build. feel free to fix stoneyridge; i'm not really planning to look into that any time soon. see the maybe attempts where it failed building -- To view, visit https://review.coreboot.org/c/coreboot/+/50466 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I90526a566a5fbc19a7368f90421067a6c716614e Gerrit-Change-Number: 50466 Gerrit-PatchSet: 5 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Comment-Date: Wed, 10 Feb 2021 18:11:09 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Martin Roth <martinroth(a)google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: drivers/i2c/hid: Enforce level triggered IRQ mode
by Michael Niewöhner (Code Review) 10 Feb '21

10 Feb '21

Attention is currently required from: Furquan Shaikh, Tim Wawrzynczak, Angel Pons, Karthik Ramasubramanian. Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50442 ) Change subject: drivers/i2c/hid: Enforce level triggered IRQ mode ...................................................................... Patch Set 3: (1 comment) File src/drivers/i2c/hid/hid.c: https://review.coreboot.org/c/coreboot/+/50442/comment/d7567971_ac9a92b5 PS3, Line 82: dev->enabled = 0; > >Not sure what you mean with "and possibly set the trigger type back to LEVEL" > Forcefully set the IRQ mode to ACPI_IRQ_LEVEL_TRIGGERED even if it is set as EDGE triggered. Hm, I don't really like that idea tbh. Using BUG() sounds good -- To view, visit https://review.coreboot.org/c/coreboot/+/50442 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3245a9de6e88cd83528823251083e62288192f0d Gerrit-Change-Number: 50442 Gerrit-PatchSet: 3 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Furquan Shaikh <furquan(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Wed, 10 Feb 2021 18:09:54 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Comment-In-Reply-To: Michael Niewöhner <foss(a)mniewoehner.de> Comment-In-Reply-To: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: [NOTFORMERGE] Squashed replace some CONFIG(CHROMEOS)
by Kyösti Mälkki (Code Review) 10 Feb '21

10 Feb '21

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/50493 ) Change subject: [NOTFORMERGE] Squashed replace some CONFIG(CHROMEOS) ...................................................................... [NOTFORMERGE] Squashed replace some CONFIG(CHROMEOS) Change-Id: Ie046facd722e56eaccb201128dfeb325f7200604 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/acpi/acpigen_extern.asl M src/acpi/dsdt_top.asl M src/acpi/gnvs.c M src/arch/x86/smbios.c M src/mainboard/google/auron/Kconfig M src/mainboard/google/butterfly/acpi_tables.c M src/mainboard/google/jecht/Kconfig M src/mainboard/google/parrot/acpi_tables.c M src/mainboard/google/stout/acpi_tables.c M src/mainboard/intel/wtm2/Kconfig M src/mainboard/samsung/lumpy/acpi_tables.c M src/northbridge/intel/haswell/acpi/hostbridge.asl M src/northbridge/intel/haswell/northbridge.c M src/northbridge/intel/sandybridge/acpi/sandybridge.asl M src/northbridge/intel/sandybridge/northbridge.c M src/security/vboot/Kconfig M src/soc/amd/picasso/Kconfig M src/soc/intel/alderlake/Kconfig M src/soc/intel/apollolake/Kconfig M src/soc/intel/baytrail/northcluster.c M src/soc/intel/braswell/northcluster.c M src/soc/intel/broadwell/northbridge.c M src/soc/intel/broadwell/pch/me.c M src/soc/intel/cannonlake/Kconfig M src/soc/intel/elkhartlake/Kconfig M src/soc/intel/icelake/Kconfig M src/soc/intel/jasperlake/Kconfig M src/soc/intel/skylake/Kconfig M src/soc/intel/tigerlake/Kconfig M src/southbridge/intel/bd82x6x/me_common.c M src/southbridge/intel/lynxpoint/me_9.x.c M src/vendorcode/google/chromeos/Kconfig M src/vendorcode/google/chromeos/chromeos.h M src/vendorcode/google/chromeos/gnvs.c M src/vendorcode/google/chromeos/ramoops.c 35 files changed, 27 insertions(+), 175 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/93/50493/1 diff --git a/src/acpi/acpigen_extern.asl b/src/acpi/acpigen_extern.asl index 5e380b5..0d9081c 100644 --- a/src/acpi/acpigen_extern.asl +++ b/src/acpi/acpigen_extern.asl @@ -19,7 +19,7 @@ OperationRegion (DNVS, SystemMemory, NVB1, NVS1) #endif -#if CONFIG(CHROMEOS) +#if CONFIG(VBOOT_NVS) External (NVB2, IntObj) External (NVS2, IntObj) OperationRegion (CNVS, SystemMemory, NVB2, NVS2) diff --git a/src/acpi/dsdt_top.asl b/src/acpi/dsdt_top.asl index d2fcfa6..d9a9109 100644 --- a/src/acpi/dsdt_top.asl +++ b/src/acpi/dsdt_top.asl @@ -2,7 +2,7 @@ #include <acpi/acpigen_extern.asl> -#if CONFIG(CHROMEOS) +#if CONFIG(VBOOT_NVS) /* Chrome OS specific */ #include <vendorcode/google/chromeos/acpi/gnvs.asl> #include <vendorcode/google/chromeos/acpi/chromeos.asl> diff --git a/src/acpi/gnvs.c b/src/acpi/gnvs.c index 63740d0..2dbfa4a 100644 --- a/src/acpi/gnvs.c +++ b/src/acpi/gnvs.c @@ -26,7 +26,7 @@ gnvs_size = 0x100; if (CONFIG(ACPI_HAS_DEVICE_NVS)) gnvs_size = 0x2000; - else if (CONFIG(CHROMEOS)) + else if (CONFIG(VBOOT_NVS)) gnvs_size = 0x1000; gnvs = cbmem_add(CBMEM_ID_ACPI_GNVS, gnvs_size); @@ -38,7 +38,7 @@ if (CONFIG(CONSOLE_CBMEM)) gnvs->cbmc = (uintptr_t)cbmem_find(CBMEM_ID_CONSOLE); - if (CONFIG(CHROMEOS)) + if (CONFIG(VBOOT_NVS)) gnvs_assign_chromeos((u8 *)gnvs + GNVS_CHROMEOS_ACPI_OFFSET); } @@ -78,7 +78,7 @@ acpigen_write_name_dword("NVS0", 0x100); acpigen_pop_len(); - if (CONFIG(CHROMEOS)) { + if (CONFIG(VBOOT_NVS)) { acpigen_write_scope("\\"); acpigen_write_name_dword("NVB2", (uintptr_t)gnvs + GNVS_CHROMEOS_ACPI_OFFSET); acpigen_write_name_dword("NVS2", 0xf00); diff --git a/src/arch/x86/smbios.c b/src/arch/x86/smbios.c index 8bc49b1..9a1ac2b 100644 --- a/src/arch/x86/smbios.c +++ b/src/arch/x86/smbios.c @@ -422,7 +422,7 @@ t->vendor = smbios_add_string(t->eos, "coreboot"); t->bios_release_date = smbios_add_string(t->eos, coreboot_dmi_date); - if (CONFIG(CHROMEOS) && CONFIG(HAVE_ACPI_TABLES)) { + if (CONFIG(VBOOT_NVS) && CONFIG(HAVE_ACPI_TABLES)) { uintptr_t version_address = (uintptr_t)t->eos; /* SMBIOS offsets start at 1 rather than 0 */ version_address += (u32)smbios_string_table_len(t->eos) - 1; diff --git a/src/mainboard/google/auron/Kconfig b/src/mainboard/google/auron/Kconfig index 5301e32..45e4e3af 100644 --- a/src/mainboard/google/auron/Kconfig +++ b/src/mainboard/google/auron/Kconfig @@ -19,9 +19,6 @@ if BOARD_GOOGLE_BASEBOARD_AURON -config CHROMEOS - select CHROMEOS_RAMOOPS_DYNAMIC - config VBOOT select EC_GOOGLE_CHROMEEC_SWITCHES select VBOOT_LID_SWITCH diff --git a/src/mainboard/google/butterfly/acpi_tables.c b/src/mainboard/google/butterfly/acpi_tables.c index 29faea3..66e1c31 100644 --- a/src/mainboard/google/butterfly/acpi_tables.c +++ b/src/mainboard/google/butterfly/acpi_tables.c @@ -18,7 +18,7 @@ // The firmware read/write status is a "virtual" switch and // will be handled elsewhere. Until then hard-code to // read/write instead of read-only for developer mode. - if (CONFIG(CHROMEOS)) + if (CONFIG(VBOOT_NVS)) gnvs_set_ecfw_rw(); // the lid is open by default. diff --git a/src/mainboard/google/jecht/Kconfig b/src/mainboard/google/jecht/Kconfig index b04cc46..dac8f3b 100644 --- a/src/mainboard/google/jecht/Kconfig +++ b/src/mainboard/google/jecht/Kconfig @@ -14,9 +14,6 @@ if BOARD_GOOGLE_BASEBOARD_JECHT -config CHROMEOS - select CHROMEOS_RAMOOPS_DYNAMIC - config VBOOT select VBOOT_VBNV_CMOS diff --git a/src/mainboard/google/parrot/acpi_tables.c b/src/mainboard/google/parrot/acpi_tables.c index 1cb4597..d3973c1 100644 --- a/src/mainboard/google/parrot/acpi_tables.c +++ b/src/mainboard/google/parrot/acpi_tables.c @@ -21,7 +21,7 @@ gnvs->s5u0 = 0; gnvs->s5u1 = 0; - if (CONFIG(CHROMEOS) && !parrot_ec_running_ro()) + if (CONFIG(VBOOT_NVS) && !parrot_ec_running_ro()) gnvs_set_ecfw_rw(); /* EC handles all active thermal and fan control on Parrot. */ diff --git a/src/mainboard/google/stout/acpi_tables.c b/src/mainboard/google/stout/acpi_tables.c index fe12e30..864178d 100644 --- a/src/mainboard/google/stout/acpi_tables.c +++ b/src/mainboard/google/stout/acpi_tables.c @@ -22,7 +22,7 @@ gnvs->s5u0 = 0; gnvs->s5u1 = 0; - if (CONFIG(CHROMEOS) && !get_recovery_mode_switch()) + if (CONFIG(VBOOT_NVS) && !get_recovery_mode_switch()) gnvs_set_ecfw_rw(); /* EC handles all thermal and fan control on Stout. */ diff --git a/src/mainboard/intel/wtm2/Kconfig b/src/mainboard/intel/wtm2/Kconfig index 7ac5f1c..6312220 100644 --- a/src/mainboard/intel/wtm2/Kconfig +++ b/src/mainboard/intel/wtm2/Kconfig @@ -11,9 +11,6 @@ select MAINBOARD_HAS_LPC_TPM select INTEL_INT15 -config CHROMEOS - select CHROMEOS_RAMOOPS_DYNAMIC - config VBOOT select VBOOT_VBNV_CMOS diff --git a/src/mainboard/samsung/lumpy/acpi_tables.c b/src/mainboard/samsung/lumpy/acpi_tables.c index c697457..07c1fbc 100644 --- a/src/mainboard/samsung/lumpy/acpi_tables.c +++ b/src/mainboard/samsung/lumpy/acpi_tables.c @@ -44,6 +44,6 @@ gnvs->tmax = MAX_TEMPERATURE; gnvs->flvl = 5; - if (CONFIG(CHROMEOS) && ec_read(0xcb)) + if (CONFIG(VBOOT_NVS) && ec_read(0xcb)) gnvs_set_ecfw_rw(); } diff --git a/src/northbridge/intel/haswell/acpi/hostbridge.asl b/src/northbridge/intel/haswell/acpi/hostbridge.asl index 1ff2826..a378f3f 100644 --- a/src/northbridge/intel/haswell/acpi/hostbridge.asl +++ b/src/northbridge/intel/haswell/acpi/hostbridge.asl @@ -182,11 +182,6 @@ Memory32Fixed (ReadWrite, 0xfed20000, 0x00020000) // Misc ICH Memory32Fixed (ReadWrite, 0xfed40000, 0x00005000) // Misc ICH Memory32Fixed (ReadWrite, 0xfed45000, 0x0004b000) // Misc ICH - -#if CONFIG(CHROMEOS_RAMOOPS) - Memory32Fixed (ReadWrite, CONFIG_CHROMEOS_RAMOOPS_RAM_START, - CONFIG_CHROMEOS_RAMOOPS_RAM_SIZE) -#endif }) // Current Resource Settings diff --git a/src/northbridge/intel/haswell/northbridge.c b/src/northbridge/intel/haswell/northbridge.c index c2c8143..b04cfec 100644 --- a/src/northbridge/intel/haswell/northbridge.c +++ b/src/northbridge/intel/haswell/northbridge.c @@ -335,11 +335,6 @@ mmio_resource(dev, index++, (0xa0000 >> 10), (0xc0000 - 0xa0000) >> 10); reserved_ram_resource(dev, index++, (0xc0000 >> 10), (0x100000 - 0xc0000) >> 10); -#if CONFIG(CHROMEOS_RAMOOPS) - reserved_ram_resource(dev, index++, - CONFIG_CHROMEOS_RAMOOPS_RAM_START >> 10, - CONFIG_CHROMEOS_RAMOOPS_RAM_SIZE >> 10); -#endif *resource_cnt = index; } diff --git a/src/northbridge/intel/sandybridge/acpi/sandybridge.asl b/src/northbridge/intel/sandybridge/acpi/sandybridge.asl index 5d7a777..cf1d61c 100644 --- a/src/northbridge/intel/sandybridge/acpi/sandybridge.asl +++ b/src/northbridge/intel/sandybridge/acpi/sandybridge.asl @@ -20,11 +20,6 @@ Memory32Fixed(ReadWrite, 0xfed40000, 0x00005000) // TPM TIS Memory32Fixed(ReadWrite, 0xfed45000, 0x0004b000) // Misc ICH -#if CONFIG(CHROMEOS_RAMOOPS) - Memory32Fixed(ReadWrite, CONFIG_CHROMEOS_RAMOOPS_RAM_START, - CONFIG_CHROMEOS_RAMOOPS_RAM_SIZE) -#endif - /* Required for SandyBridge sighting 3715511 */ Memory32Fixed(ReadWrite, 0x20000000, 0x00200000) Memory32Fixed(ReadWrite, 0x40000000, 0x00200000) diff --git a/src/northbridge/intel/sandybridge/northbridge.c b/src/northbridge/intel/sandybridge/northbridge.c index 2274355..fbed687 100644 --- a/src/northbridge/intel/sandybridge/northbridge.c +++ b/src/northbridge/intel/sandybridge/northbridge.c @@ -67,12 +67,6 @@ reserved_ram_resource(dev, index++, 0xc0000 >> 10, (0x100000 - 0xc0000) >> 10); -#if CONFIG(CHROMEOS_RAMOOPS) - reserved_ram_resource(dev, index++, - CONFIG_CHROMEOS_RAMOOPS_RAM_START >> 10, - CONFIG_CHROMEOS_RAMOOPS_RAM_SIZE >> 10); -#endif - if (is_sandybridge()) { /* Required for SandyBridge sighting 3715511 */ bad_ram_resource(dev, index++, 0x20000000 >> 10, 0x00200000 >> 10); diff --git a/src/security/vboot/Kconfig b/src/security/vboot/Kconfig index e202333..b09508f 100644 --- a/src/security/vboot/Kconfig +++ b/src/security/vboot/Kconfig @@ -71,6 +71,11 @@ help VBNV is stored in flash storage +config VBOOT_NVS + bool + default n + depends on HAVE_ACPI_TABLES + config VBOOT_STARTS_BEFORE_BOOTBLOCK def_bool n select VBOOT_SEPARATE_VERSTAGE diff --git a/src/soc/amd/picasso/Kconfig b/src/soc/amd/picasso/Kconfig index 4868d84..818b4d3 100644 --- a/src/soc/amd/picasso/Kconfig +++ b/src/soc/amd/picasso/Kconfig @@ -313,7 +313,6 @@ choose to generate _PSD object to allow cores to transition together. config CHROMEOS - select CHROMEOS_RAMOOPS_DYNAMIC select ALWAYS_LOAD_OPROM select ALWAYS_RUN_OPROM diff --git a/src/soc/intel/alderlake/Kconfig b/src/soc/intel/alderlake/Kconfig index 1c69454..916e5f3 100644 --- a/src/soc/intel/alderlake/Kconfig +++ b/src/soc/intel/alderlake/Kconfig @@ -213,9 +213,6 @@ hex default 0x7fff -config CHROMEOS - select CHROMEOS_RAMOOPS_DYNAMIC - config VBOOT select VBOOT_SEPARATE_VERSTAGE select VBOOT_MUST_REQUEST_DISPLAY diff --git a/src/soc/intel/apollolake/Kconfig b/src/soc/intel/apollolake/Kconfig index 62049b5..9fe2c29 100644 --- a/src/soc/intel/apollolake/Kconfig +++ b/src/soc/intel/apollolake/Kconfig @@ -114,9 +114,6 @@ int default 4 -config CHROMEOS - select CHROMEOS_RAMOOPS_DYNAMIC - config VBOOT select VBOOT_SEPARATE_VERSTAGE select VBOOT_MUST_REQUEST_DISPLAY diff --git a/src/soc/intel/baytrail/northcluster.c b/src/soc/intel/baytrail/northcluster.c index 310ce4d..e8f9768 100644 --- a/src/soc/intel/baytrail/northcluster.c +++ b/src/soc/intel/baytrail/northcluster.c @@ -10,7 +10,6 @@ #include <soc/iosf.h> #include <soc/pci_devs.h> #include <soc/ramstage.h> -#include <vendorcode/google/chromeos/chromeos.h> /* * Host Memory Map: @@ -119,9 +118,6 @@ */ mmio_resource(dev, index++, (0xa0000 >> 10), (0xc0000 - 0xa0000) >> 10); reserved_ram_resource(dev, index++, (0xc0000 >> 10), (0x100000 - 0xc0000) >> 10); - - if (CONFIG(CHROMEOS)) - chromeos_reserve_ram_oops(dev, index++); } static void nc_generate_ssdt(const struct device *dev) diff --git a/src/soc/intel/braswell/northcluster.c b/src/soc/intel/braswell/northcluster.c index 0ef58b2..b7ddee4 100644 --- a/src/soc/intel/braswell/northcluster.c +++ b/src/soc/intel/braswell/northcluster.c @@ -13,7 +13,6 @@ #include <soc/iosf.h> #include <soc/pci_devs.h> #include <soc/ramstage.h> -#include <vendorcode/google/chromeos/chromeos.h> #include <stddef.h> /* @@ -145,9 +144,6 @@ base_k = RES_IN_KiB(LAPIC_DEFAULT_BASE); size_k = RES_IN_KiB(0x00100000); mmio_resource(dev, index++, base_k, size_k); - - if (CONFIG(CHROMEOS)) - chromeos_reserve_ram_oops(dev, index++); } static void nc_generate_ssdt(const struct device *dev) diff --git a/src/soc/intel/broadwell/northbridge.c b/src/soc/intel/broadwell/northbridge.c index bc26388..f89552c 100644 --- a/src/soc/intel/broadwell/northbridge.c +++ b/src/soc/intel/broadwell/northbridge.c @@ -9,7 +9,6 @@ #include <device/device.h> #include <device/pci.h> #include <device/pci_ids.h> -#include <vendorcode/google/chromeos/chromeos.h> #include <soc/acpi.h> #include <soc/iomap.h> #include <soc/pci_devs.h> @@ -372,9 +371,6 @@ reserved_ram_resource(dev, index++, (0xc0000 >> 10), (0x100000 - 0xc0000) >> 10); - if (CONFIG(CHROMEOS)) - chromeos_reserve_ram_oops(dev, index++); - *resource_cnt = index; } diff --git a/src/soc/intel/broadwell/pch/me.c b/src/soc/intel/broadwell/pch/me.c index 88d2172..97e062f 100644 --- a/src/soc/intel/broadwell/pch/me.c +++ b/src/soc/intel/broadwell/pch/me.c @@ -770,7 +770,7 @@ printk(BIOS_DEBUG, "\n"); /* Save hash in NVS for the OS to verify */ - if (CONFIG(CHROMEOS)) + if (CONFIG(VBOOT_NVS)) chromeos_set_me_hash(extend, count); return 0; diff --git a/src/soc/intel/cannonlake/Kconfig b/src/soc/intel/cannonlake/Kconfig index 49ec1b1..dd7d699 100644 --- a/src/soc/intel/cannonlake/Kconfig +++ b/src/soc/intel/cannonlake/Kconfig @@ -260,9 +260,6 @@ hex default 0xc35 -config CHROMEOS - select CHROMEOS_RAMOOPS_DYNAMIC - config VBOOT select VBOOT_SEPARATE_VERSTAGE select VBOOT_MUST_REQUEST_DISPLAY diff --git a/src/soc/intel/elkhartlake/Kconfig b/src/soc/intel/elkhartlake/Kconfig index 25804d7..3b17a0ed 100644 --- a/src/soc/intel/elkhartlake/Kconfig +++ b/src/soc/intel/elkhartlake/Kconfig @@ -171,9 +171,6 @@ hex default 0xc35 -config CHROMEOS - select CHROMEOS_RAMOOPS_DYNAMIC - config VBOOT select VBOOT_SEPARATE_VERSTAGE select VBOOT_MUST_REQUEST_DISPLAY diff --git a/src/soc/intel/icelake/Kconfig b/src/soc/intel/icelake/Kconfig index 501e6c3..f28209f 100644 --- a/src/soc/intel/icelake/Kconfig +++ b/src/soc/intel/icelake/Kconfig @@ -164,9 +164,6 @@ hex default 0xc35 -config CHROMEOS - select CHROMEOS_RAMOOPS_DYNAMIC - config VBOOT select VBOOT_SEPARATE_VERSTAGE select VBOOT_MUST_REQUEST_DISPLAY diff --git a/src/soc/intel/jasperlake/Kconfig b/src/soc/intel/jasperlake/Kconfig index 08bd4be..72912f7 100644 --- a/src/soc/intel/jasperlake/Kconfig +++ b/src/soc/intel/jasperlake/Kconfig @@ -172,9 +172,6 @@ hex default 0xc35 -config CHROMEOS - select CHROMEOS_RAMOOPS_DYNAMIC - config VBOOT select VBOOT_SEPARATE_VERSTAGE select VBOOT_MUST_REQUEST_DISPLAY diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig index 7401d5e..a7e25b1 100644 --- a/src/soc/intel/skylake/Kconfig +++ b/src/soc/intel/skylake/Kconfig @@ -92,9 +92,6 @@ int default 10 -config CHROMEOS - select CHROMEOS_RAMOOPS_DYNAMIC - config VBOOT select VBOOT_SEPARATE_VERSTAGE select VBOOT_MUST_REQUEST_DISPLAY diff --git a/src/soc/intel/tigerlake/Kconfig b/src/soc/intel/tigerlake/Kconfig index 3e080cc..c6bb167 100644 --- a/src/soc/intel/tigerlake/Kconfig +++ b/src/soc/intel/tigerlake/Kconfig @@ -191,9 +191,6 @@ hex default 0x7fff -config CHROMEOS - select CHROMEOS_RAMOOPS_DYNAMIC - # Tiger Lake SoC requires at least 100us interrupt pulses in order to guarantee detection # in all low power states. Cr50 TPM, if used, needs to be told to generate longer pulses. config TPM_CR50 diff --git a/src/southbridge/intel/bd82x6x/me_common.c b/src/southbridge/intel/bd82x6x/me_common.c index e229956..64c372f 100644 --- a/src/southbridge/intel/bd82x6x/me_common.c +++ b/src/southbridge/intel/bd82x6x/me_common.c @@ -405,7 +405,7 @@ printk(BIOS_DEBUG, "\n"); /* Save hash in NVS for the OS to verify */ - if (CONFIG(CHROMEOS)) + if (CONFIG(VBOOT_NVS)) chromeos_set_me_hash(extend, count); return 0; diff --git a/src/southbridge/intel/lynxpoint/me_9.x.c b/src/southbridge/intel/lynxpoint/me_9.x.c index 69192e6..366e3bc 100644 --- a/src/southbridge/intel/lynxpoint/me_9.x.c +++ b/src/southbridge/intel/lynxpoint/me_9.x.c @@ -753,7 +753,7 @@ printk(BIOS_DEBUG, "\n"); /* Save hash in NVS for the OS to verify */ - if (CONFIG(CHROMEOS)) + if (CONFIG(VBOOT_NVS)) chromeos_set_me_hash(extend, count); return 0; diff --git a/src/vendorcode/google/chromeos/Kconfig b/src/vendorcode/google/chromeos/Kconfig index d5254ac..88eab8c 100644 --- a/src/vendorcode/google/chromeos/Kconfig +++ b/src/vendorcode/google/chromeos/Kconfig @@ -12,6 +12,7 @@ select ELOG if BOOT_DEVICE_SUPPORTS_WRITES select COLLECT_TIMESTAMPS select VBOOT + select VBOOT_NVS select VPD select VBOOT_SLOTS_RW_AB help @@ -29,21 +30,6 @@ bool "Reserve space for Chrome OS ramoops" default y -config CHROMEOS_RAMOOPS_DYNAMIC - bool "Allocate RAM oops buffer in cbmem" - default n - depends on CHROMEOS_RAMOOPS && HAVE_ACPI_TABLES - -config CHROMEOS_RAMOOPS_NON_ACPI - bool "Allocate RAM oops buffer in cbmem passed through cb tables to payload" - default y if !HAVE_ACPI_TABLES - depends on CHROMEOS_RAMOOPS && !HAVE_ACPI_TABLES - -config CHROMEOS_RAMOOPS_RAM_START - hex "Physical address of preserved RAM" - default 0x00f00000 - depends on CHROMEOS_RAMOOPS && !CHROMEOS_RAMOOPS_DYNAMIC - config CHROMEOS_RAMOOPS_RAM_SIZE hex "Size of preserved RAM" default 0x00100000 diff --git a/src/vendorcode/google/chromeos/chromeos.h b/src/vendorcode/google/chromeos/chromeos.h index 315d693..db46d86 100644 --- a/src/vendorcode/google/chromeos/chromeos.h +++ b/src/vendorcode/google/chromeos/chromeos.h @@ -30,19 +30,6 @@ struct romstage_handoff; #include "gnvs.h" -struct device; - -#if CONFIG(CHROMEOS_RAMOOPS) -void chromeos_ram_oops_init(chromeos_acpi_t *chromeos); -#if CONFIG(CHROMEOS_RAMOOPS_DYNAMIC) -static inline void chromeos_reserve_ram_oops(struct device *dev, int idx) {} -#else /* CONFIG_CHROMEOS_RAMOOPS_DYNAMIC */ -void chromeos_reserve_ram_oops(struct device *dev, int idx); -#endif /* CONFIG_CHROMEOS_RAMOOPS_DYNAMIC */ -#else /* !CONFIG_CHROMEOS_RAMOOPS */ -static inline void chromeos_ram_oops_init(chromeos_acpi_t *chromeos) {} -static inline void chromeos_reserve_ram_oops(struct device *dev, int idx) {} -#endif /* CONFIG_CHROMEOS_RAMOOPS */ void cbmem_add_vpd_calibration_data(void); void chromeos_set_me_hash(u32*, int); diff --git a/src/vendorcode/google/chromeos/gnvs.c b/src/vendorcode/google/chromeos/gnvs.c index f0e8e5b..62d19d6 100644 --- a/src/vendorcode/google/chromeos/gnvs.c +++ b/src/vendorcode/google/chromeos/gnvs.c @@ -38,8 +38,6 @@ /* Copy saved ME hash into NVS */ memcpy(chromeos_acpi->mehh, me_hash_saved, sizeof(chromeos_acpi->mehh)); - chromeos_ram_oops_init(chromeos_acpi); - vpd_size = chromeos_vpd_region("RO_VPD", &vpd_base); if (vpd_size && vpd_base) { chromeos_acpi->vpd_ro_base = vpd_base; diff --git a/src/vendorcode/google/chromeos/ramoops.c b/src/vendorcode/google/chromeos/ramoops.c index 119912b..a74552d 100644 --- a/src/vendorcode/google/chromeos/ramoops.c +++ b/src/vendorcode/google/chromeos/ramoops.c @@ -10,7 +10,6 @@ #include <device/device.h> #include "chromeos.h" -#if CONFIG(HAVE_ACPI_TABLES) static void set_ramoops(chromeos_acpi_t *chromeos, void *ram_oops, size_t size) { @@ -24,82 +23,26 @@ chromeos->ramoops_len = size; } -static void reserve_ram_oops_dynamic(chromeos_acpi_t *chromeos) +static void ramoops_alloc(void *arg) { const size_t size = CONFIG_CHROMEOS_RAMOOPS_RAM_SIZE; void *ram_oops; - if (!CONFIG(CHROMEOS_RAMOOPS_DYNAMIC)) - return; - - ram_oops = cbmem_add(CBMEM_ID_RAM_OOPS, size); - - set_ramoops(chromeos, ram_oops, size); -} - -#if CONFIG(CHROMEOS_RAMOOPS_DYNAMIC) -static inline void set_global_chromeos_pointer(chromeos_acpi_t *chromeos) {} -#else /* !CONFIG_CHROMEOS_RAMOOPS_DYNAMIC */ - -static const unsigned long ramoops_base = CONFIG_CHROMEOS_RAMOOPS_RAM_START; -static const unsigned long ramoops_size = CONFIG_CHROMEOS_RAMOOPS_RAM_SIZE; - -/* - * Save pointer to chromeos structure in memory. This is needed because the - * memory reservation is not done when chromeos_init() is called. However, - * the pointer to the chromeos_acpi_t structure is needed to update the - * fields with the rserved base and size. - */ -static chromeos_acpi_t *g_chromeos; - -static void set_global_chromeos_pointer(chromeos_acpi_t *chromeos) -{ - g_chromeos = chromeos; -} - -static void update_gnvs(void *arg) -{ - chromeos_acpi_t **chromeos = arg; - - set_ramoops(*chromeos, (void *)ramoops_base, ramoops_size); -} - -static BOOT_STATE_CALLBACK(bscb_ramoops, update_gnvs, &g_chromeos); - -void chromeos_reserve_ram_oops(struct device *dev, int idx) -{ - const unsigned long base = ramoops_base >> 10; - const unsigned long size = ramoops_size >> 10; - - reserved_ram_resource(dev, idx, base, size); - - boot_state_sched_on_exit(&bscb_ramoops, BS_WRITE_TABLES); -} -#endif /* CONFIG_CHROMEOS_RAMOOPS_DYNAMIC */ - -void chromeos_ram_oops_init(chromeos_acpi_t *chromeos) -{ - set_global_chromeos_pointer(chromeos); - reserve_ram_oops_dynamic(chromeos); -} - -#elif CONFIG(CHROMEOS_RAMOOPS_NON_ACPI) - -static void ramoops_alloc(void *arg) -{ - const size_t size = CONFIG_CHROMEOS_RAMOOPS_RAM_SIZE; - if (size == 0) return; - if (cbmem_add(CBMEM_ID_RAM_OOPS, size) == NULL) + ram_oops = cbmem_add(CBMEM_ID_RAM_OOPS, size); + if (ram_oops == NULL) { printk(BIOS_ERR, "Could not allocate RAMOOPS buffer\n"); + return; + } + + if (CONFIG(VBOOT_NVS)) + set_ramoops(chromeos, ram_oops, size); } BOOT_STATE_INIT_ENTRY(BS_WRITE_TABLES, BS_ON_ENTRY, ramoops_alloc, NULL); -#endif - void lb_ramoops(struct lb_header *header) { void *buffer = cbmem_find(CBMEM_ID_RAM_OOPS); -- To view, visit https://review.coreboot.org/c/coreboot/+/50493 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie046facd722e56eaccb201128dfeb325f7200604 Gerrit-Change-Number: 50493 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

1 0

Change in coreboot[master]: mb/razer/blade_stealth_kbl: Configure IRQs as level triggered for HID...
by Furquan Shaikh (Code Review) 10 Feb '21

10 Feb '21

Attention is currently required from: Felix Singer, Tim Wawrzynczak, Mimoja, Karthik Ramasubramanian. Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50453 ) Change subject: mb/razer/blade_stealth_kbl: Configure IRQs as level triggered for HID over I2C ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/50453 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifdc3f061d919c8db9001c7a4cc26eb21117958d7 Gerrit-Change-Number: 50453 Gerrit-PatchSet: 1 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Mimoja <coreboot(a)mimoja.de> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Felix Singer <felixsinger(a)posteo.net> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Mimoja <coreboot(a)mimoja.de> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Wed, 10 Feb 2021 18:07:56 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

Change in coreboot[master]: mb/razer/blade_stealth_kbl: Configure IRQs as level triggered for HID...
by Furquan Shaikh (Code Review) 10 Feb '21

10 Feb '21

Attention is currently required from: Felix Singer, Tim Wawrzynczak, Mimoja, Karthik Ramasubramanian. Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50453 ) Change subject: mb/razer/blade_stealth_kbl: Configure IRQs as level triggered for HID over I2C ...................................................................... Patch Set 1: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/50453 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifdc3f061d919c8db9001c7a4cc26eb21117958d7 Gerrit-Change-Number: 50453 Gerrit-PatchSet: 1 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Mimoja <coreboot(a)mimoja.de> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Felix Singer <felixsinger(a)posteo.net> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Mimoja <coreboot(a)mimoja.de> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Wed, 10 Feb 2021 18:07:47 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

Change in coreboot[master]: sb/intel/bd82x6x/acpi: Convert to ASL 2.0
by Michael Niewöhner (Code Review) 10 Feb '21

10 Feb '21

Michael Niewöhner has submitted this change. ( https://review.coreboot.org/c/coreboot/+/50327 ) Change subject: sb/intel/bd82x6x/acpi: Convert to ASL 2.0 ...................................................................... sb/intel/bd82x6x/acpi: Convert to ASL 2.0 Change-Id: Ib587d7a982852e7123e43337407ef20d96811719 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50327 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Michael Niewöhner <foss(a)mniewoehner.de> --- M src/southbridge/intel/bd82x6x/acpi/globalnvs.asl M src/southbridge/intel/bd82x6x/acpi/usb.asl 2 files changed, 53 insertions(+), 53 deletions(-) Approvals: build bot (Jenkins): Verified Michael Niewöhner: Looks good to me, approved diff --git a/src/southbridge/intel/bd82x6x/acpi/globalnvs.asl b/src/southbridge/intel/bd82x6x/acpi/globalnvs.asl index 25dcfe0..20e32ef 100644 --- a/src/southbridge/intel/bd82x6x/acpi/globalnvs.asl +++ b/src/southbridge/intel/bd82x6x/acpi/globalnvs.asl @@ -111,53 +111,53 @@ /* Set flag to enable USB charging in S3 */ Method (S3UE) { - Store (One, \S3U0) - Store (One, \S3U1) + \S3U0 = 1 + \S3U1 = 1 } /* Set flag to disable USB charging in S3 */ Method (S3UD) { - Store (Zero, \S3U0) - Store (Zero, \S3U1) + \S3U0 = 0 + \S3U1 = 0 } /* Set flag to enable USB charging in S5 */ Method (S5UE) { - Store (One, \S5U0) - Store (One, \S5U1) + \S5U0 = 1 + \S5U1 = 1 } /* Set flag to disable USB charging in S5 */ Method (S5UD) { - Store (Zero, \S5U0) - Store (Zero, \S5U1) + \S5U0 = 0 + \S5U1 = 0 } /* Set flag to enable 3G module in S3 */ Method (S3GE) { - Store (One, \S33G) + \S33G = 1 } /* Set flag to disable 3G module in S3 */ Method (S3GD) { - Store (Zero, \S33G) + \S33G = 0 } /* Set XHCI Mode enable */ Method (XHCE) { - Store (One, \XHCI) + \XHCI = 1 } /* Set XHCI Mode disable */ Method (XHCD) { - Store (Zero, \XHCI) + \XHCI = 0 } External (\_TZ.SKIN) @@ -179,46 +179,46 @@ /* Update Fan 0 thresholds */ Method (F0UT, 2) { - Store (Arg0, \F0OF) - Store (Arg1, \F0ON) + \F0OF = Arg0 + \F0ON = Arg1 TZUP () } /* Update Fan 1 thresholds */ Method (F1UT, 2) { - Store (Arg0, \F1OF) - Store (Arg1, \F1ON) + \F1OF = Arg0 + \F1ON = Arg1 TZUP () } /* Update Fan 2 thresholds */ Method (F2UT, 2) { - Store (Arg0, \F2OF) - Store (Arg1, \F2ON) + \F2OF = Arg0 + \F2ON = Arg1 TZUP () } /* Update Fan 3 thresholds */ Method (F3UT, 2) { - Store (Arg0, \F3OF) - Store (Arg1, \F3ON) + \F3OF = Arg0 + \F3ON = Arg1 TZUP () } /* Update Fan 4 thresholds */ Method (F4UT, 2) { - Store (Arg0, \F4OF) - Store (Arg1, \F4ON) + \F4OF = Arg0 + \F4ON = Arg1 TZUP () } /* Update Temperature Sensor ID */ Method (TMPU, 1) { - Store (Arg0, \TMPS) + \TMPS = Arg0 TZUP () } diff --git a/src/southbridge/intel/bd82x6x/acpi/usb.asl b/src/southbridge/intel/bd82x6x/acpi/usb.asl index 309053f..15a2f9b 100644 --- a/src/southbridge/intel/bd82x6x/acpi/usb.asl +++ b/src/southbridge/intel/bd82x6x/acpi/usb.asl @@ -37,12 +37,12 @@ }) // REV: Revision 0x02 for ACPI 5.0 - CreateField (DerefOf (Index (PCKG, Zero)), Zero, 0x07, REV) - Store (0x02, REV) + CreateField (DerefOf (PCKG [0]), 0, 0x07, REV) + REV = 0x02 // VISI: Port visibility to user per port - CreateField (DerefOf (Index (PCKG, Zero)), 0x40, One, VISI) - Store (Arg0, VISI) + CreateField (DerefOf (PCKG [0]), 0x40, 1, VISI) + VISI = Arg0 Return (PCKG) } @@ -90,12 +90,12 @@ }) // REV: Revision 0x02 for ACPI 5.0 - CreateField (DerefOf (Index (PCKG, Zero)), Zero, 0x07, REV) - Store (0x02, REV) + CreateField (DerefOf (PCKG [0]), 0, 0x07, REV) + REV = 0x02 // VISI: Port visibility to user per port - CreateField (DerefOf (Index (PCKG, Zero)), 0x40, One, VISI) - Store (Arg0, VISI) + CreateField (DerefOf (PCKG [0]), 0x40, 1, VISI) + VISI = Arg0 Return (PCKG) } @@ -137,38 +137,38 @@ CreateDWordField(Arg1,0,CDW1) // Check revision - If(LNotEqual(Arg0,One)) { + If(Arg0 != 1) { // Set unknown revision bit - Or(CDW1,0x8,CDW1) + CDW1 |= 8 } // Set failure if xHCI is disabled by coreboot - If(LEqual(XHCI, 0)) { - Or(CDW1,0x2,CDW1) + If(XHCI == 0) { + CDW1 |= 2 } // Query flag clear and xHCI in auto mode - If(LAnd(LNot(And(CDW1,0x1)),LOr(LEqual(XHCI ,2), LEqual(XHCI ,3)))) { - Store ("XHCI Switch", Debug) - Store(Zero, Local0) - And(XPRT, 0x3, Local0) - If(LOr(LEqual(Local0, 0), LEqual(Local0, 1))) { - Store(0xF, Local1) + If(!(CDW1 & 0x1) && (XHCI == 2 || XHCI == 3)) { + Debug = "XHCI Switch" + Local0 = 0 + Local0 = XPRT & 0x03 + If(Local0 == 0 || Local0 == 1) { + Local1 = 0x0f } - ElseIf(LEqual(Local0, 2)) { - Store(0x3, Local1) + ElseIf(Local0 == 2) { + Local1 = 3 } - ElseIf(LEqual(Local0, 3)) { - Store(Zero, Local1) + ElseIf(Local0 == 3) { + Local1 = 0 } - And(RPM3, 0xFFFFFFF0, Local0) - Or(Local0, Local1, RPM3) - And(PRM2, 0xFFFFFFF0, Local0) - Or(Local0, Local1, PRM2) - And(SSEN, 0xFFFFFFF0, Local0) - Or(Local0, Local1, SSEN) - And(X2PR, 0xFFFFFFF0, Local0) - Or(Local0, Local1, X2PR) + Local0 = RPM3 & 0xfffffff0 + RPM3 = Local0 | Local1 + Local0 = PRM2 & 0xfffffff0 + PRM2 = Local0 | Local1 + Local0 = SSEN & 0xfffffff0 + SSEN = Local0 | Local1 + Local0 = X2PR & 0xfffffff0 + X2PR = Local0 | Local1 } Return(Arg1) } -- To view, visit https://review.coreboot.org/c/coreboot/+/50327 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib587d7a982852e7123e43337407ef20d96811719 Gerrit-Change-Number: 50327 Gerrit-PatchSet: 2 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: sb/intel/bd82x6x/acpi: Convert to ASL 2.0
by Michael Niewöhner (Code Review) 10 Feb '21

10 Feb '21

Attention is currently required from: Patrick Rudolph, HAOUAS Elyes. Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50327 ) Change subject: sb/intel/bd82x6x/acpi: Convert to ASL 2.0 ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/50327 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib587d7a982852e7123e43337407ef20d96811719 Gerrit-Change-Number: 50327 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Comment-Date: Wed, 10 Feb 2021 18:04:45 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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